mx6: Factor out common HDMI setup code
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 8f0f9b8..1b82633 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -480,22 +480,9 @@
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
}
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- printf("%s: setup HDMI monitor\n", __func__);
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
-
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+ imx_enable_hdmi_phy();
}
static int detect_i2c(struct display_info_t const *dev)
@@ -528,7 +515,7 @@
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
- .enable = enable_hdmi,
+ .enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
@@ -653,25 +640,15 @@
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
int reg;
+ enable_ipu_clock();
+ imx_setup_hdmi();
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
- |MXC_CCM_CCGR3_LDB_DI0_MASK;
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
- /* Turn on HDMI PHY clock */
- reg = __raw_readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
- |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
-
- /* clear HDMI PHY reset */
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
@@ -689,15 +666,8 @@
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
- |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
- |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
- |(CHSCCDR_PODF_DIVIDE_BY_3
- <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- |(CHSCCDR_IPU_PRE_CLK_540M_PFD
- <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 43c02ac..6cd28ed 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -211,23 +211,6 @@
}
#if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(void)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
-
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
-}
-
static struct fb_videomode const hdmi = {
.name = "HDMI",
.refresh = 60,
@@ -253,7 +236,7 @@
if (ret)
printf("HDMI cannot be configured: %d\n", ret);
- enable_hdmi();
+ imx_enable_hdmi_phy();
return ret;
}
@@ -261,33 +244,14 @@
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg;
- /* Turn on IPU clock */
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* Turn on HDMI PHY clock */
- reg = readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
- | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
-
- /* clear HDMI PHY reset */
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+ enable_ipu_clock();
+ imx_setup_hdmi();
reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
- | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
- | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
- | (CHSCCDR_PODF_DIVIDE_BY_3
- << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- | (CHSCCDR_IPU_PRE_CLK_540M_PFD
- << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
}
#endif /* CONFIG_VIDEO_IPUV3 */