Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5a64fcc..85ef00a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -661,6 +661,7 @@
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
+ imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb
dtb-$(CONFIG_RCAR_GEN2) += \
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 5d50eb0..80d6475 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -3,6 +3,11 @@
* Copyright 2018 NXP
*/
+&{/imx8qm-pm} {
+
+ u-boot,dm-spl;
+};
+
&mu {
u-boot,dm-spl;
};
@@ -67,6 +72,14 @@
u-boot,dm-spl;
};
+&pd_dma {
+ u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 2015590..771ab63 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -72,6 +72,14 @@
u-boot,dm-spl;
};
+&pd_dma {
+ u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 16093f2..3502602 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -11,6 +11,9 @@
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
};
&osc_24m {
@@ -110,3 +113,7 @@
&pinctrl_pmic {
u-boot,dm-spl;
};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
index faefb71..ef249ff 100644
--- a/arch/arm/dts/imx8mm-evk.dts
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -464,7 +464,7 @@
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
@@ -480,7 +480,7 @@
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
@@ -496,7 +496,7 @@
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
new file mode 100644
index 0000000..8d61597
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts
new file mode 100644
index 0000000..9b2c172
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-evk.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR4 EVK board";
+ compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ at803x,led-act-blind-workaround;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart2 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx8mn-pinfunc.h b/arch/arm/dts/imx8mn-pinfunc.h
new file mode 100644
index 0000000..3de8168
--- /dev/null
+++ b/arch/arm/dts/imx8mn-pinfunc.h
@@ -0,0 +1,646 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#ifndef __DTS_IMX8MN_PINFUNC_H
+#define __DTS_IMX8MN_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x0020 0x025C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x0020 0x025C 0x055C 0x1 0x3
+#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x0024 0x0260 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x0024 0x0260 0x056C 0x1 0x3
+#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0028 0x0290 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x0028 0x0290 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0028 0x0290 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x0028 0x0290 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x002C 0x0294 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x002C 0x0294 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x002C 0x0294 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x002C 0x0294 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x0030 0x0298 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x0030 0x0298 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x0030 0x0298 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x0034 0x029C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x0034 0x029C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x0034 0x029C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x0034 0x029C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0038 0x02A0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0038 0x02A0 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x0038 0x02A0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x0038 0x02A0 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x003C 0x02A4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x003C 0x02A4 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x003C 0x02A4 0x04BC 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x003C 0x02A4 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0040 0x02A8 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x0040 0x02A8 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x0040 0x02A8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x0040 0x02A8 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0044 0x02AC 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x0044 0x02AC 0x04C0 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x0044 0x02AC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x0044 0x02AC 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0048 0x02B0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x0048 0x02B0 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x0048 0x02B0 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x0048 0x02B0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x0048 0x02B0 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x004C 0x02B4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x004C 0x02B4 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x004C 0x02B4 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x004C 0x02B4 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x004C 0x02B4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x004C 0x02B4 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0050 0x02B8 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x0050 0x02B8 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x0050 0x02B8 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x0054 0x02BC 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x0054 0x02BC 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x0054 0x02BC 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x0054 0x02BC 0x04BC 0x5 0x1
+#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x0054 0x02BC 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x0058 0x02C0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x0058 0x02C0 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x0058 0x02C0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x0058 0x02C0 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x005C 0x02C4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x005C 0x02C4 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x005C 0x02C4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x005C 0x02C4 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0060 0x02C8 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x0060 0x02C8 0x0598 0x4 0x2
+#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x0060 0x02C8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x0060 0x02C8 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0064 0x02CC 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x0064 0x02CC 0x05B8 0x4 0x2
+#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x0064 0x02CC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x0064 0x02CC 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x0068 0x02D0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x0068 0x02D0 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x0068 0x02D0 0x0540 0x3 0x1
+#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x0068 0x02D0 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x0068 0x02D0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x0068 0x02D0 0x059C 0x6 0x1
+#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x006C 0x02D4 0x04C0 0x0 0x1
+#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x006C 0x02D4 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x006C 0x02D4 0x053C 0x3 0x1
+#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x006C 0x02D4 0x05CC 0x4 0x1
+#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x006C 0x02D4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x006C 0x02D4 0x0550 0x6 0x1
+#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x0070 0x02D8 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x0070 0x02D8 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x0070 0x02D8 0x0538 0x3 0x1
+#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x0070 0x02D8 0x0568 0x4 0x1
+#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x0070 0x02D8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x0070 0x02D8 0x0584 0x6 0x1
+#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x0074 0x02DC 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x0074 0x02DC 0x05A4 0x1 0x0
+#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0074 0x02DC 0x05A4 0x1 0x0
+#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x0074 0x02DC 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x0074 0x02DC 0x0540 0x3 0x2
+#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x0074 0x02DC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x0074 0x02DC 0x054C 0x6 0x1
+#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x0078 0x02E0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x0078 0x02E0 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x0078 0x02E0 0x053C 0x3 0x2
+#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x0078 0x02E0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x0078 0x02E0 0x0598 0x6 0x3
+#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x007C 0x02E4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x007C 0x02E4 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x007C 0x02E4 0x0538 0x3 0x2
+#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x007C 0x02E4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x007C 0x02E4 0x05B8 0x6 0x3
+#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x0080 0x02E8 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x0080 0x02E8 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x0080 0x02E8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x0080 0x02E8 0x05B4 0x6 0x1
+#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x0084 0x02EC 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x0084 0x02EC 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x0084 0x02EC 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x0084 0x02EC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x0084 0x02EC 0x05B0 0x6 0x1
+#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x0088 0x02F0 0x0574 0x0 0x0
+#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x0088 0x02F0 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x0088 0x02F0 0x0540 0x3 0x3
+#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x0088 0x02F0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x0088 0x02F0 0x05E4 0x6 0x1
+#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x008C 0x02F4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x008C 0x02F4 0x05C8 0x1 0x0
+#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x008C 0x02F4 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x008C 0x02F4 0x053C 0x3 0x3
+#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x008C 0x02F4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x008C 0x02F4 0x05E0 0x6 0x1
+#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x0090 0x02F8 0x057C 0x0 0x0
+#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x0090 0x02F8 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x0090 0x02F8 0x0538 0x3 0x3
+#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x0090 0x02F8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x0090 0x02F8 0x0558 0x6 0x1
+#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x0094 0x02FC 0x0554 0x0 0x0
+#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x0094 0x02FC 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x0094 0x02FC 0x0534 0x3 0x1
+#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x0094 0x02FC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x0094 0x02FC 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x0098 0x0300 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x0098 0x0300 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x0098 0x0300 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x0098 0x0300 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x0098 0x0300 0x05A0 0x6 0x1
+#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x009C 0x0304 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x009C 0x0304 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x009C 0x0304 0x05CC 0x3 0x5
+#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x009C 0x0304 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x009C 0x0304 0x05DC 0x6 0x1
+#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x00A0 0x0308 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x00A0 0x0308 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x00A0 0x0308 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x00A0 0x0308 0x04F4 0x4 0x4
+#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x00A0 0x0308 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x00A4 0x030C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x00A4 0x030C 0x04C0 0x1 0x3
+#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x00A4 0x030C 0x04F4 0x4 0x5
+#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x00A4 0x030C 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x00A4 0x030C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x00A8 0x0310 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x00A8 0x0310 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x00A8 0x0310 0x04F0 0x4 0x4
+#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x00A8 0x0310 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x00A8 0x0310 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x00AC 0x0314 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x00AC 0x0314 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x00AC 0x0314 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x00AC 0x0314 0x04F0 0x4 0x5
+#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x00AC 0x0314 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x00B0 0x0318 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x00B0 0x0318 0x057C 0x1 0x1
+#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x00B0 0x0318 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x00B0 0x0318 0x04FC 0x4 0x4
+#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x00B0 0x0318 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x00B4 0x031C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x00B4 0x031C 0x0554 0x1 0x1
+#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x00B4 0x031C 0x04FC 0x4 0x5
+#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x00B4 0x031C 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x00B4 0x031C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x00B8 0x0320 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x00B8 0x0320 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x00B8 0x0320 0x055C 0x3 0x1
+#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x00B8 0x0320 0x04F8 0x4 0x4
+#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x00B8 0x0320 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00B8 0x0320 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x00BC 0x0324 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x00BC 0x0324 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x00BC 0x0324 0x056C 0x3 0x1
+#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x00BC 0x0324 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x00BC 0x0324 0x04F8 0x4 0x5
+#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00BC 0x0324 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x00C0 0x0328 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x00C0 0x0328 0x0574 0x1 0x1
+#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x00C0 0x0328 0x05D0 0x3 0x1
+#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x00C0 0x0328 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x00C0 0x0328 0x0504 0x4 0x4
+#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00C0 0x0328 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x00C4 0x032C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x00C4 0x032C 0x05C8 0x1 0x1
+#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x00C4 0x032C 0x0560 0x3 0x1
+#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x00C4 0x032C 0x0504 0x4 0x5
+#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x00C4 0x032C 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00C4 0x032C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x00C8 0x0330 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x00C8 0x0330 0x05A4 0x1 0x1
+#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x00C8 0x0330 0x05A4 0x1 0x0
+#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x00C8 0x0330 0x0588 0x3 0x1
+#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x00C8 0x0330 0x0500 0x4 0x2
+#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x00C8 0x0330 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x00C8 0x0330 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x00CC 0x0334 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x00CC 0x0334 0x05BC 0x3 0x1
+#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x00CC 0x0334 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x00CC 0x0334 0x0500 0x4 0x3
+#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x00CC 0x0334 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x00D0 0x0338 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x00D0 0x0338 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x00D0 0x0338 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x00D4 0x033C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x00D4 0x033C 0x04E4 0x1 0x1
+#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x00D4 0x033C 0x0580 0x2 0x1
+#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x00D4 0x033C 0x050C 0x3 0x4
+#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x00D4 0x033C 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x00D4 0x033C 0x0594 0x4 0x1
+#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x00D4 0x033C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x00D4 0x033C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x00D8 0x0340 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x00D8 0x0340 0x04D0 0x1 0x1
+#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x00D8 0x0340 0x0590 0x2 0x1
+#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x00D8 0x0340 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x00D8 0x0340 0x050C 0x3 0x5
+#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x00D8 0x0340 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x00D8 0x0340 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x00D8 0x0340 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x00DC 0x0344 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x00DC 0x0344 0x04D4 0x1 0x1
+#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x00DC 0x0344 0x058C 0x2 0x1
+#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x00DC 0x0344 0x04FC 0x3 0x6
+#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x00DC 0x0344 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x00DC 0x0344 0x0534 0x4 0x2
+#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x00DC 0x0344 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x00DC 0x0344 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x00E0 0x0348 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x00E0 0x0348 0x04EC 0x1 0x1
+#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x00E0 0x0348 0x05D4 0x2 0x1
+#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x00E0 0x0348 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x00E0 0x0348 0x04FC 0x3 0x7
+#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x00E0 0x0348 0x0538 0x4 0x4
+#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x00E0 0x0348 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x00E0 0x0348 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x00E4 0x034C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x00E4 0x034C 0x04E8 0x1 0x1
+#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x00E4 0x034C 0x0570 0x2 0x2
+#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x00E4 0x034C 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x00E4 0x034C 0x053C 0x4 0x4
+#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x00E4 0x034C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x00E4 0x034C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x00E8 0x0350 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x00E8 0x0350 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x00E8 0x0350 0x0578 0x2 0x1
+#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x00E8 0x0350 0x05CC 0x3 0x2
+#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x00E8 0x0350 0x0540 0x4 0x4
+#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x00E8 0x0350 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x00E8 0x0350 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x00EC 0x0354 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x00EC 0x0354 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x00EC 0x0354 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x00F0 0x0358 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x00F0 0x0358 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x00F0 0x0358 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00F4 0x035C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x00F4 0x035C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x00F4 0x035C 0x0534 0x3 0x3
+#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x00F4 0x035C 0x0504 0x4 0x6
+#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x00F4 0x035C 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x00F4 0x035C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x00F4 0x035C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00F8 0x0360 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x00F8 0x0360 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x00F8 0x0360 0x0538 0x3 0x5
+#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x00F8 0x0360 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x00F8 0x0360 0x0504 0x4 0x7
+#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00F8 0x0360 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x00F8 0x0360 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00FC 0x0364 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x00FC 0x0364 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x00FC 0x0364 0x059C 0x2 0x0
+#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x00FC 0x0364 0x0534 0x3 0x4
+#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x00FC 0x0364 0x05D4 0x4 0x2
+#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x00FC 0x0364 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x00FC 0x0364 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x0100 0x0368 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x0100 0x0368 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x0100 0x0368 0x0550 0x2 0x0
+#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x0100 0x0368 0x0538 0x3 0x6
+#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x0100 0x0368 0x058C 0x4 0x2
+#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x0100 0x0368 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x0100 0x0368 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x0104 0x036C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x0104 0x036C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x0104 0x036C 0x0584 0x2 0x0
+#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x0104 0x036C 0x053C 0x3 0x5
+#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x0104 0x036C 0x05BC 0x4 0x2
+#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x0104 0x036C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x0104 0x036C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x0108 0x0370 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x0108 0x0370 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x0108 0x0370 0x054C 0x2 0x0
+#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x0108 0x0370 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x0108 0x0370 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x010C 0x0374 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x010C 0x0374 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x010C 0x0374 0x053C 0x3 0x6
+#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x010C 0x0374 0x050C 0x4 0x6
+#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x010C 0x0374 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x010C 0x0374 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x010C 0x0374 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x0110 0x0378 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x0110 0x0378 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x0110 0x0378 0x0540 0x3 0x5
+#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x0110 0x0378 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x0110 0x0378 0x050C 0x4 0x7
+#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x0110 0x0378 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x0110 0x0378 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x0114 0x037C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x0114 0x037C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x0114 0x037C 0x0598 0x2 0x0
+#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x0114 0x037C 0x058C 0x4 0x3
+#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0114 0x037C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x0114 0x037C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x0118 0x0380 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x0118 0x0380 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x0118 0x0380 0x05B8 0x2 0x0
+#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0118 0x0380 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x0118 0x0380 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x011C 0x0384 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x011C 0x0384 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x011C 0x0384 0x05B4 0x2 0x0
+#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x011C 0x0384 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x011C 0x0384 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x0120 0x0388 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x0120 0x0388 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x0120 0x0388 0x05B0 0x2 0x0
+#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x0120 0x0388 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x0120 0x0388 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x0124 0x038C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x0124 0x038C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x0124 0x038C 0x05E4 0x2 0x0
+#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x0124 0x038C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x0124 0x038C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x0128 0x0390 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x0128 0x0390 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x0128 0x0390 0x05E0 0x2 0x0
+#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x0128 0x0390 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x0128 0x0390 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x012C 0x0394 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x012C 0x0394 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x012C 0x0394 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x012C 0x0394 0x0588 0x4 0x2
+#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x012C 0x0394 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x012C 0x0394 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x0130 0x0398 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x0130 0x0398 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x0130 0x0398 0x0558 0x2 0x0
+#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x0130 0x0398 0x0538 0x3 0x7
+#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x0130 0x0398 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x0130 0x0398 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x0134 0x039C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x0134 0x039C 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x0134 0x039C 0x0540 0x3 0x6
+#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x0134 0x039C 0x0588 0x4 0x3
+#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x0134 0x039C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x0134 0x039C 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x0138 0x03A0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x0138 0x03A0 0x05A0 0x2 0x0
+#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x0138 0x03A0 0x05BC 0x4 0x3
+#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x0138 0x03A0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x0138 0x03A0 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x013C 0x03A4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x013C 0x03A4 0x05DC 0x2 0x0
+#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x013C 0x03A4 0x058C 0x4 0x4
+#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x013C 0x03A4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x013C 0x03A4 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x0140 0x03A8 0x04E4 0x0 0x0
+#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0140 0x03A8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x0144 0x03AC 0x04D0 0x0 0x0
+#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x0144 0x03AC 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x0144 0x03AC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0148 0x03B0 0x04D4 0x0 0x0
+#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x0148 0x03B0 0x0534 0x4 0x0
+#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x0148 0x03B0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x014C 0x03B4 0x04D8 0x0 0x0
+#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x014C 0x03B4 0x04EC 0x3 0x0
+#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x014C 0x03B4 0x0538 0x4 0x0
+#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x014C 0x03B4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x0150 0x03B8 0x04DC 0x0 0x0
+#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x0150 0x03B8 0x04E8 0x3 0x0
+#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x0150 0x03B8 0x053C 0x4 0x0
+#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x0150 0x03B8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x0154 0x03BC 0x04E0 0x0 0x0
+#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x0154 0x03BC 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x0154 0x03BC 0x0540 0x4 0x0
+#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x0154 0x03BC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x0158 0x03C0 0x0594 0x0 0x0
+#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0158 0x03C0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x01B0 0x0418 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x01B0 0x0418 0x04EC 0x1 0x2
+#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x01B0 0x0418 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x01B0 0x0418 0x05AC 0x3 0x0
+#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x01B0 0x0418 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x01B0 0x0418 0x04F4 0x4 0x2
+#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x01B0 0x0418 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x01B0 0x0418 0x053C 0x6 0x7
+#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x01B4 0x041C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x01B4 0x041C 0x04E8 0x1 0x2
+#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x01B4 0x041C 0x04F4 0x4 0x3
+#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x01B4 0x041C 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x01B4 0x041C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x01B4 0x041C 0x0538 0x6 0x8
+#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x01B8 0x0420 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x01B8 0x0420 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x01B8 0x0420 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x01B8 0x0420 0x04F0 0x4 0x2
+#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x01B8 0x0420 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x01B8 0x0420 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x01B8 0x0420 0x0540 0x6 0x7
+#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x01BC 0x0424 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x01BC 0x0424 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x01BC 0x0424 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x01BC 0x0424 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x01BC 0x0424 0x04F0 0x4 0x3
+#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x01BC 0x0424 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x01BC 0x0424 0x053C 0x6 0x8
+#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x01C0 0x0428 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x01C0 0x0428 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x01C0 0x0428 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x01C0 0x0428 0x0538 0x6 0x9
+#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x01C4 0x042C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x01C4 0x042C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x01C4 0x042C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x01C4 0x042C 0x0540 0x6 0x8
+#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x01C8 0x0430 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x01C8 0x0430 0x0594 0x1 0x2
+#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x01C8 0x0430 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x01C8 0x0430 0x05C0 0x6 0x1
+#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x01CC 0x0434 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x01CC 0x0434 0x05F0 0x1 0x0
+#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x01CC 0x0434 0x04E4 0x2 0x2
+#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x01CC 0x0434 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x01CC 0x0434 0x05CC 0x4 0x3
+#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x01CC 0x0434 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x01CC 0x0434 0x0534 0x6 0x5
+#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x01D0 0x0438 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x01D0 0x0438 0x05E8 0x1 0x0
+#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x01D0 0x0438 0x04D0 0x2 0x2
+#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x01D0 0x0438 0x05AC 0x3 0x2
+#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x01D0 0x0438 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x01D0 0x0438 0x04F8 0x4 0x2
+#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x01D0 0x0438 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x01D0 0x0438 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x01D4 0x043C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x01D4 0x043C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x01D4 0x043C 0x04D4 0x2 0x2
+#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x01D4 0x043C 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x01D4 0x043C 0x04F8 0x4 0x3
+#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x01D4 0x043C 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x01D4 0x043C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x01D4 0x043C 0x0538 0x6 0x10
+#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x01D8 0x0440 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x01D8 0x0440 0x05EC 0x1 0x0
+#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x01D8 0x0440 0x04D8 0x2 0x1
+#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x01D8 0x0440 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x01D8 0x0440 0x04FC 0x4 0x2
+#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x01D8 0x0440 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x01D8 0x0440 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x01D8 0x0440 0x0540 0x6 0x9
+#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x01DC 0x0444 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x01DC 0x0444 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x01DC 0x0444 0x04DC 0x2 0x1
+#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x01DC 0x0444 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x01DC 0x0444 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x01DC 0x0444 0x04FC 0x4 0x3
+#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x01DC 0x0444 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x01DC 0x0444 0x053C 0x6 0x9
+#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x01E0 0x0448 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x01E0 0x0448 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x01E0 0x0448 0x04E0 0x2 0x1
+#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x01E0 0x0448 0x0568 0x4 0x2
+#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x01E0 0x0448 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x01E0 0x0448 0x0000 0x6 0x0
+#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x01E4 0x044C 0x05C0 0x0 0x0
+#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x01E4 0x044C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x01E4 0x044C 0x0594 0x2 0x3
+#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x01E4 0x044C 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x01E4 0x044C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x01E4 0x044C 0x05CC 0x6 0x4
+#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x01E8 0x0450 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x01E8 0x0450 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x01E8 0x0450 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x01EC 0x0454 0x05CC 0x0 0x0
+#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x01EC 0x0454 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x01EC 0x0454 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x01F0 0x0458 0x0568 0x0 0x0
+#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x01F0 0x0458 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x01F0 0x0458 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x01F4 0x045C 0x05D8 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x01F4 0x045C 0x0504 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x01F4 0x045C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x01F4 0x045C 0x055C 0x2 0x2
+#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x01F4 0x045C 0x04DC 0x3 0x2
+#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x01F4 0x045C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x01F8 0x0460 0x05A8 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x01F8 0x0460 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x01F8 0x0460 0x0504 0x1 0x1
+#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x01F8 0x0460 0x056C 0x2 0x2
+#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x01F8 0x0460 0x04D0 0x3 0x3
+#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x01F8 0x0460 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x01FC 0x0464 0x05C4 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x01FC 0x0464 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x01FC 0x0464 0x0500 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x01FC 0x0464 0x05D0 0x2 0x2
+#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x01FC 0x0464 0x04D4 0x3 0x3
+#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x01FC 0x0464 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x0200 0x0468 0x0564 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x0200 0x0468 0x0500 0x1 0x1
+#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x0200 0x0468 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x0200 0x0468 0x0560 0x2 0x2
+#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x0200 0x0468 0x04D8 0x3 0x2
+#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x0200 0x0468 0x04EC 0x4 0x3
+#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0200 0x0468 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0204 0x046C 0x0580 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x0204 0x046C 0x050C 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x0204 0x046C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x0204 0x046C 0x0588 0x2 0x4
+#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x0204 0x046C 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x0204 0x046C 0x04E8 0x4 0x3
+#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x0204 0x046C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0208 0x0470 0x0590 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x0208 0x0470 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x0208 0x0470 0x050C 0x1 0x1
+#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x0208 0x0470 0x05BC 0x2 0x4
+#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x0208 0x0470 0x04E0 0x3 0x2
+#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x0208 0x0470 0x0000 0x4 0x0
+#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x0208 0x0470 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x020C 0x0474 0x0578 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x020C 0x0474 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x020C 0x0474 0x0508 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x020C 0x0474 0x05D4 0x2 0x3
+#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x020C 0x0474 0x0594 0x3 0x4
+#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x020C 0x0474 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x0210 0x0478 0x0570 0x0 0x0
+#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x0210 0x0478 0x0508 0x1 0x1
+#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x0210 0x0478 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x0210 0x0478 0x058C 0x2 0x5
+#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0210 0x0478 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x0214 0x047C 0x055C 0x0 0x0
+#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x0214 0x047C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x0214 0x047C 0x05D8 0x3 0x1
+#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x0214 0x047C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x0218 0x0480 0x056C 0x0 0x0
+#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x0218 0x0480 0x04C0 0x1 0x2
+#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x0218 0x0480 0x05A8 0x3 0x1
+#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x0218 0x0480 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x021C 0x0484 0x05D0 0x0 0x0
+#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x021C 0x0484 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x021C 0x0484 0x0598 0x2 0x1
+#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x021C 0x0484 0x05C4 0x3 0x1
+#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x021C 0x0484 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x0220 0x0488 0x0560 0x0 0x0
+#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x0220 0x0488 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x0220 0x0488 0x05B8 0x2 0x1
+#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x0220 0x0488 0x0564 0x3 0x1
+#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x0220 0x0488 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x0224 0x048C 0x0588 0x0 0x0
+#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x0224 0x048C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x0224 0x048C 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x0224 0x048C 0x0580 0x3 0x2
+#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x0224 0x048C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x0228 0x0490 0x05BC 0x0 0x0
+#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x0228 0x0490 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x0228 0x0490 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x0228 0x0490 0x0590 0x3 0x2
+#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x0228 0x0490 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x022C 0x0494 0x05D4 0x0 0x0
+#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x022C 0x0494 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x022C 0x0494 0x0578 0x3 0x2
+#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x022C 0x0494 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x0230 0x0498 0x058C 0x0 0x0
+#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x0230 0x0498 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x0230 0x0498 0x0570 0x3 0x1
+#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x0230 0x0498 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x0234 0x049C 0x04F4 0x0 0x0
+#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x0234 0x049C 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x0234 0x049C 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x0234 0x049C 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x0238 0x04A0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x0238 0x04A0 0x04F4 0x0 0x1
+#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x0238 0x04A0 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x0238 0x04A0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x023C 0x04A4 0x04FC 0x0 0x0
+#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x023C 0x04A4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x023C 0x04A4 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x023C 0x04A4 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x023C 0x04A4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x0240 0x04A8 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x0240 0x04A8 0x04FC 0x0 0x1
+#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x0240 0x04A8 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x0240 0x04A8 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x0240 0x04A8 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x0244 0x04AC 0x0504 0x0 0x2
+#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x0244 0x04AC 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x0244 0x04AC 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x0244 0x04AC 0x04F0 0x1 0x0
+#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x0244 0x04AC 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x0244 0x04AC 0x05EC 0x3 0x1
+#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x0244 0x04AC 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x0248 0x04B0 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x0248 0x04B0 0x0504 0x0 0x3
+#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x0248 0x04B0 0x04F0 0x1 0x1
+#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x0248 0x04B0 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x0248 0x04B0 0x0000 0x2 0x0
+#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x0248 0x04B0 0x05E8 0x3 0x1
+#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x0248 0x04B0 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x024C 0x04B4 0x050C 0x0 0x2
+#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x024C 0x04B4 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x024C 0x04B4 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x024C 0x04B4 0x04F8 0x1 0x0
+#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x024C 0x04B4 0x0000 0x3 0x0
+#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x024C 0x04B4 0x0000 0x5 0x0
+#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0250 0x04B8 0x0000 0x0 0x0
+#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x0250 0x04B8 0x050C 0x0 0x3
+#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x0250 0x04B8 0x04F8 0x1 0x1
+#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x0250 0x04B8 0x0000 0x1 0x0
+#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x0250 0x04B8 0x05F0 0x3 0x1
+#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x0250 0x04B8 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX8MN_PINFUNC_H */
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
new file mode 100644
index 0000000..f5eff35
--- /dev/null
+++ b/arch/arm/dts/imx8mn.dtsi
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx8mn-pinfunc.h"
+
+/ {
+ compatible = "fsl,imx8mn";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-latency = <61036>;
+ clocks = <&clk IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-latency = <61036>;
+ clocks = <&clk IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-latency = <61036>;
+ clocks = <&clk IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-latency = <61036>;
+ clocks = <&clk IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext2";
+ };
+
+ clk_ext3: clock-ext3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext3";
+ };
+
+ clk_ext4: clock-ext4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <133000000>;
+ clock-output-names = "clk_ext4";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <8000000>;
+ arm,no-tick-in-suspend;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x3e000000>;
+
+ aips1: bus@30000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x30000000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: gpio@30200000 {
+ compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
+ reg = <0x30200000 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@30210000 {
+ compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
+ reg = <0x30210000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@30220000 {
+ compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
+ reg = <0x30220000 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@30230000 {
+ compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
+ reg = <0x30230000 0x10000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@30240000 {
+ compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
+ reg = <0x30240000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wdog1: watchdog@30280000 {
+ compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
+ reg = <0x30280000 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
+ status = "disabled";
+ };
+
+ wdog2: watchdog@30290000 {
+ compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
+ reg = <0x30290000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
+ status = "disabled";
+ };
+
+ wdog3: watchdog@302a0000 {
+ compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
+ reg = <0x302a0000 0x10000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
+ status = "disabled";
+ };
+
+ sdma3: dma-controller@302b0000 {
+ compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
+ reg = <0x302b0000 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
+ <&clk IMX8MN_CLK_SDMA3_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ sdma2: dma-controller@302c0000 {
+ compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
+ reg = <0x302c0000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
+ <&clk IMX8MN_CLK_SDMA2_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ iomuxc: pinctrl@30330000 {
+ compatible = "fsl,imx8mn-iomuxc";
+ reg = <0x30330000 0x10000>;
+ };
+
+ gpr: iomuxc-gpr@30340000 {
+ compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
+ reg = <0x30340000 0x10000>;
+ };
+
+ ocotp: ocotp-ctrl@30350000 {
+ compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
+ reg = <0x30350000 0x10000>;
+ clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
+ };
+
+ anatop: anatop@30360000 {
+ compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
+ "syscon", "simple-bus";
+ reg = <0x30360000 0x10000>;
+ };
+
+ snvs: snvs@30370000 {
+ compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
+ reg = <0x30370000 0x10000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "snvs-rtc";
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
+ clk: clock-controller@30380000 {
+ compatible = "fsl,imx8mn-ccm";
+ reg = <0x30380000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+
+ src: reset-controller@30390000 {
+ compatible = "fsl,imx8mn-src", "syscon";
+ reg = <0x30390000 0x10000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+ };
+
+ aips2: bus@30400000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x30400000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pwm1: pwm@30660000 {
+ compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
+ reg = <0x30660000 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
+ <&clk IMX8MN_CLK_PWM1_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@30670000 {
+ compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
+ reg = <0x30670000 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
+ <&clk IMX8MN_CLK_PWM2_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@30680000 {
+ compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
+ reg = <0x30680000 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
+ <&clk IMX8MN_CLK_PWM3_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@30690000 {
+ compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
+ reg = <0x30690000 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
+ <&clk IMX8MN_CLK_PWM4_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ aips3: bus@30800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x30800000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ecspi1: spi@30820000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi2: spi@30830000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi3: spi@30840000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
+ <&clk IMX8MN_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
+ <&clk IMX8MN_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
+ <&clk IMX8MN_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c1: i2c@30a20000 {
+ compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30a20000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@30a30000 {
+ compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30a30000 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@30a40000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
+ reg = <0x30a40000 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@30a50000 {
+ compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30a50000 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
+ status = "disabled";
+ };
+
+ uart4: serial@30a60000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30a60000 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
+ <&clk IMX8MN_CLK_UART4_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ usdhc1: mmc@30b40000 {
+ compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x30b40000 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MN_CLK_USDHC1_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@30b50000 {
+ compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x30b50000 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MN_CLK_USDHC2_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@30b60000 {
+ compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x30b60000 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MN_CLK_USDHC3_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ sdma1: dma-controller@30bd0000 {
+ compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
+ reg = <0x30bd0000 0x10000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
+ <&clk IMX8MN_CLK_SDMA1_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ fec1: ethernet@30be0000 {
+ compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
+ reg = <0x30be0000 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
+ <&clk IMX8MN_CLK_ENET1_ROOT>,
+ <&clk IMX8MN_CLK_ENET_TIMER>,
+ <&clk IMX8MN_CLK_ENET_REF>,
+ <&clk IMX8MN_CLK_ENET_PHY_REF>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
+ <&clk IMX8MN_CLK_ENET_TIMER>,
+ <&clk IMX8MN_CLK_ENET_REF>,
+ <&clk IMX8MN_CLK_ENET_TIMER>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+ <&clk IMX8MN_SYS_PLL2_100M>,
+ <&clk IMX8MN_SYS_PLL2_125M>;
+ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+ fsl,num-tx-queues = <3>;
+ fsl,num-rx-queues = <3>;
+ status = "disabled";
+ };
+
+ };
+
+ aips4: bus@32c00000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x32c00000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbotg1: usb@32e40000 {
+ compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
+ reg = <0x32e40000 0x200>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
+ clock-names = "usb1_ctrl_root_clk";
+ assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
+ <&clk IMX8MN_CLK_USB_CORE_REF>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
+ <&clk IMX8MN_SYS_PLL1_100M>;
+ fsl,usbphy = <&usbphynop1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@32e40200 {
+ compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
+ #index-cells = <1>;
+ reg = <0x32e40200 0x200>;
+ };
+
+ usbotg2: usb@32e50000 {
+ compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
+ reg = <0x32e50000 0x200>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
+ clock-names = "usb1_ctrl_root_clk";
+ assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
+ <&clk IMX8MN_CLK_USB_CORE_REF>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
+ <&clk IMX8MN_SYS_PLL1_100M>;
+ fsl,usbphy = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@32e50200 {
+ compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
+ #index-cells = <1>;
+ reg = <0x32e50200 0x200>;
+ };
+
+ };
+
+ dma_apbh: dma-controller@33000000 {
+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x33000000 0x2000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+ };
+
+ gpmi: nand-controller@33002000 {
+ compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
+ <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+ clock-names = "gpmi_io", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@38800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x38800000 0x10000>,
+ <0x38880000 0xc0000>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
+ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
+ clock-names = "main_clk";
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
+ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
+ clock-names = "main_clk";
+ };
+};
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 3a85492..b0f4dd0 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -32,6 +32,7 @@
#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
+#define MXC_CPU_IMX8MN 0x8b /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index dded6e0..c910b61 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -9,7 +9,7 @@
#ifdef CONFIG_IMX8MQ
#include <asm/arch/clock_imx8mq.h>
-#elif defined(CONFIG_IMX8MM)
+#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
#include <asm/arch/clock_imx8mm.h>
#else
#error "Error no clock.h"
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index 305514a..76c73ed 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -52,6 +52,83 @@
ANATOP_DRAM_PLL,
};
+#ifdef CONFIG_IMX8MN
+enum clk_root_index {
+ ARM_A53_CLK_ROOT = 0,
+ ARM_M7_CLK_ROOT = 1,
+ GPU_CORE_CLK_ROOT = 3,
+ GPU_SHADER_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ DISPLAY_AXI_CLK_ROOT = 20,
+ DISPLAY_APB_CLK_ROOT = 21,
+ USB_BUS_CLK_ROOT = 23,
+ GPU_AXI_CLK_ROOT = 24,
+ GPU_AHB_CLK_ROOT = 25,
+ NOC_CLK_ROOT = 26,
+ AHB_CLK_ROOT = 32,
+ IPG_CLK_ROOT = 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ DRAM_SEL_CFG = 48,
+ CORE_SEL_CFG = 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ DISPLAY_PIXEL_CLK_ROOT = 74,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT = 87,
+ USDHC1_CLK_ROOT = 88,
+ USDHC2_CLK_ROOT = 89,
+ I2C1_CLK_ROOT = 90,
+ I2C2_CLK_ROOT = 91,
+ I2C3_CLK_ROOT = 92,
+ I2C4_CLK_ROOT = 93,
+ UART1_CLK_ROOT = 94,
+ UART2_CLK_ROOT = 95,
+ UART3_CLK_ROOT = 96,
+ UART4_CLK_ROOT = 97,
+ USB_CORE_REF_CLK_ROOT = 98,
+ USB_PHY_REF_CLK_ROOT = 99,
+ GIC_CLK_ROOT = 100,
+ ECSPI1_CLK_ROOT = 101,
+ ECSPI2_CLK_ROOT = 102,
+ PWM1_CLK_ROOT = 103,
+ PWM2_CLK_ROOT = 104,
+ PWM3_CLK_ROOT = 105,
+ PWM4_CLK_ROOT = 106,
+ GPT1_CLK_ROOT = 107,
+ GPT2_CLK_ROOT = 108,
+ GPT3_CLK_ROOT = 109,
+ GPT4_CLK_ROOT = 110,
+ GPT5_CLK_ROOT = 111,
+ GPT6_CLK_ROOT = 112,
+ TRACE_CLK_ROOT = 113,
+ WDOG_CLK_ROOT = 114,
+ WRCLK_CLK_ROOT = 115,
+ IPP_DO_CLKO1 = 116,
+ IPP_DO_CLKO2 = 117,
+ MIPI_DSI_CORE_CLK_ROOT = 118,
+ DISPLAY_DSI_PHY_REF_CLK_ROOT = 119,
+ MIPI_DSI_DBI_CLK_ROOT = 120,
+ USDHC3_CLK_ROOT = 121,
+ DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122,
+ MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
+ MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
+ MIPI_CSI2_ESC_CLK_ROOT = 127,
+ ECSPI3_CLK_ROOT = 131,
+ PDM_CLK_ROOT = 132,
+ SAI7_CLK_ROOT = 134,
+ CLK_ROOT_MAX,
+};
+#else
enum clk_root_index {
ARM_A53_CLK_ROOT = 0,
ARM_M4_CLK_ROOT = 1,
@@ -148,6 +225,7 @@
VPU_H1_CLK_ROOT = 133,
CLK_ROOT_MAX,
};
+#endif
enum clk_root_src {
OSC_24M_CLK,
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h
new file mode 100644
index 0000000..b4298f2
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h
@@ -0,0 +1,763 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MN_PINS_H__
+#define __ASM_ARCH_IMX8MN_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+ IMX8MN_PAD_BOOT_MODE2__CCMSRCGPCMIX_BOOT_MODE2 = IOMUX_PAD(0x025C, 0x0020, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_BOOT_MODE2__I2C1_SCL = IOMUX_PAD(0x025C, 0x0020, 1, 0x055C, 3, 0),
+
+ IMX8MN_PAD_BOOT_MODE3__CCMSRCGPCMIX_BOOT_MODE3 = IOMUX_PAD(0x0260, 0x0024, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_BOOT_MODE3__I2C1_SDA = IOMUX_PAD(0x0260, 0x0024, 1, 0x056C, 3, 0),
+
+ IMX8MN_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO03__ANAMIX_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO05__M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+ IMX8MN_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO06__ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO07__ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+ IMX8MN_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO08__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x02B0, 0x0048, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO09__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x02B4, 0x004C, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO09__USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x02B8, 0x0050, 2, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO11__USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+ IMX8MN_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO14__USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0598, 2, 0),
+ IMX8MN_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO15__USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x05B8, 2, 0),
+ IMX8MN_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ENET_MDC__ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_MDC__SAI6_TX_DATA0 = IOMUX_PAD(0x02D0, 0x0068, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_MDC__PDM_BIT_STREAM3 = IOMUX_PAD(0x02D0, 0x0068, 3, 0x0540, 1, 0),
+ IMX8MN_PAD_ENET_MDC__SPDIF1_OUT = IOMUX_PAD(0x02D0, 0x0068, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_MDC__USDHC3_STROBE = IOMUX_PAD(0x02D0, 0x0068, 6, 0x059C, 1, 0),
+
+ IMX8MN_PAD_ENET_MDIO__ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+ IMX8MN_PAD_ENET_MDIO__SAI6_TX_SYNC = IOMUX_PAD(0x02D4, 0x006C, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_MDIO__PDM_BIT_STREAM2 = IOMUX_PAD(0x02D4, 0x006C, 3, 0x053C, 1, 0),
+ IMX8MN_PAD_ENET_MDIO__SPDIF1_IN = IOMUX_PAD(0x02D4, 0x006C, 4, 0x05CC, 1, 0),
+ IMX8MN_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_MDIO__USDHC3_DATA5 = IOMUX_PAD(0x02D4, 0x006C, 6, 0x0550, 1, 0),
+
+ IMX8MN_PAD_ENET_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD3__SAI6_TX_BCLK = IOMUX_PAD(0x02D8, 0x0070, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD3__PDM_BIT_STREAM1 = IOMUX_PAD(0x02D8, 0x0070, 3, 0x0538, 1, 0),
+ IMX8MN_PAD_ENET_TD3__SPDIF1_EXT_CLK = IOMUX_PAD(0x02D8, 0x0070, 4, 0x0568, 1, 0),
+ IMX8MN_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD3__USDHC3_DATA6 = IOMUX_PAD(0x02D8, 0x0070, 6, 0x0584, 1, 0),
+
+ IMX8MN_PAD_ENET_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD2__ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x05A4, 0, 0),
+ IMX8MN_PAD_ENET_TD2__CCMSRCGPCMIX_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x05A4, 0, 0),
+ IMX8MN_PAD_ENET_TD2__SAI6_RX_DATA0 = IOMUX_PAD(0x02DC, 0x0074, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD2__PDM_BIT_STREAM3 = IOMUX_PAD(0x02DC, 0x0074, 3, 0x0540, 2, 0),
+ IMX8MN_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD2__USDHC3_DATA7 = IOMUX_PAD(0x02DC, 0x0074, 6, 0x054C, 1, 0),
+
+ IMX8MN_PAD_ENET_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD1__SAI6_RX_SYNC = IOMUX_PAD(0x02E0, 0x0078, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD1__PDM_BIT_STREAM2 = IOMUX_PAD(0x02E0, 0x0078, 3, 0x053C, 2, 0),
+ IMX8MN_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD1__USDHC3_CD_B = IOMUX_PAD(0x02E0, 0x0078, 6, 0x0598, 3, 0),
+
+ IMX8MN_PAD_ENET_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD0__SAI6_RX_BCLK = IOMUX_PAD(0x02E4, 0x007C, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD0__PDM_BIT_STREAM1 = IOMUX_PAD(0x02E4, 0x007C, 3, 0x0538, 2, 0),
+ IMX8MN_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TD0__USDHC3_WP = IOMUX_PAD(0x02E4, 0x007C, 6, 0x05B8, 3, 0),
+
+ IMX8MN_PAD_ENET_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TX_CTL__SAI6_MCLK = IOMUX_PAD(0x02E8, 0x0080, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TX_CTL__USDHC3_DATA0 = IOMUX_PAD(0x02E8, 0x0080, 6, 0x05B4, 1, 0),
+
+ IMX8MN_PAD_ENET_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TXC__ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TXC__SAI7_TX_DATA0 = IOMUX_PAD(0x02EC, 0x0084, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_TXC__USDHC3_DATA1 = IOMUX_PAD(0x02EC, 0x0084, 6, 0x05B0, 1, 0),
+
+ IMX8MN_PAD_ENET_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0574, 0, 0),
+ IMX8MN_PAD_ENET_RX_CTL__SAI7_TX_SYNC = IOMUX_PAD(0x02F0, 0x0088, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RX_CTL__PDM_BIT_STREAM3 = IOMUX_PAD(0x02F0, 0x0088, 3, 0x0540, 3, 0),
+ IMX8MN_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RX_CTL__USDHC3_DATA2 = IOMUX_PAD(0x02F0, 0x0088, 6, 0x05E4, 1, 0),
+
+ IMX8MN_PAD_ENET_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RXC__ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x05C8, 0, 0),
+ IMX8MN_PAD_ENET_RXC__SAI7_TX_BCLK = IOMUX_PAD(0x02F4, 0x008C, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RXC__PDM_BIT_STREAM2 = IOMUX_PAD(0x02F4, 0x008C, 3, 0x053C, 3, 0),
+ IMX8MN_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RXC__USDHC3_DATA3 = IOMUX_PAD(0x02F4, 0x008C, 6, 0x05E0, 1, 0),
+
+ IMX8MN_PAD_ENET_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x057C, 0, 0),
+ IMX8MN_PAD_ENET_RD0__SAI7_RX_DATA0 = IOMUX_PAD(0x02F8, 0x0090, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD0__PDM_BIT_STREAM1 = IOMUX_PAD(0x02F8, 0x0090, 3, 0x0538, 3, 0),
+ IMX8MN_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD0__USDHC3_DATA4 = IOMUX_PAD(0x02F8, 0x0090, 6, 0x0558, 1, 0),
+
+ IMX8MN_PAD_ENET_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0554, 0, 0),
+ IMX8MN_PAD_ENET_RD1__SAI7_RX_SYNC = IOMUX_PAD(0x02FC, 0x0094, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD1__PDM_BIT_STREAM0 = IOMUX_PAD(0x02FC, 0x0094, 3, 0x0534, 1, 0),
+ IMX8MN_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD1__USDHC3_RESET_B = IOMUX_PAD(0x02FC, 0x0094, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ENET_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD2__SAI7_RX_BCLK = IOMUX_PAD(0x0300, 0x0098, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD2__PDM_CLK = IOMUX_PAD(0x0300, 0x0098, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD2__USDHC3_CLK = IOMUX_PAD(0x0300, 0x0098, 6, 0x05A0, 1, 0),
+
+ IMX8MN_PAD_ENET_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD3__SAI7_MCLK = IOMUX_PAD(0x0304, 0x009C, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD3__SPDIF1_IN = IOMUX_PAD(0x0304, 0x009C, 3, 0x05CC, 5, 0),
+ IMX8MN_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_ENET_RD3__USDHC3_CMD = IOMUX_PAD(0x0304, 0x009C, 6, 0x05DC, 1, 0),
+
+ IMX8MN_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_CLK__ENET1_MDC = IOMUX_PAD(0x0308, 0x00A0, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_CLK__UART1_DCE_TX = IOMUX_PAD(0x0308, 0x00A0, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_CLK__UART1_DTE_RX = IOMUX_PAD(0x0308, 0x00A0, 4, 0x04F4, 4, 0),
+ IMX8MN_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_CMD__ENET1_MDIO = IOMUX_PAD(0x030C, 0x00A4, 1, 0x04C0, 3, 0),
+ IMX8MN_PAD_SD1_CMD__UART1_DCE_RX = IOMUX_PAD(0x030C, 0x00A4, 4, 0x04F4, 5, 0),
+ IMX8MN_PAD_SD1_CMD__UART1_DTE_TX = IOMUX_PAD(0x030C, 0x00A4, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA0__ENET1_RGMII_TD1 = IOMUX_PAD(0x0310, 0x00A8, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA0__UART1_DCE_RTS_B = IOMUX_PAD(0x0310, 0x00A8, 4, 0x04F0, 4, 0),
+ IMX8MN_PAD_SD1_DATA0__UART1_DTE_CTS_B = IOMUX_PAD(0x0310, 0x00A8, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA1__ENET1_RGMII_TD0 = IOMUX_PAD(0x0314, 0x00AC, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA1__UART1_DCE_CTS_B = IOMUX_PAD(0x0314, 0x00AC, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA1__UART1_DTE_RTS_B = IOMUX_PAD(0x0314, 0x00AC, 4, 0x04F0, 5, 0),
+ IMX8MN_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA2__ENET1_RGMII_RD0 = IOMUX_PAD(0x0318, 0x00B0, 1, 0x057C, 1, 0),
+ IMX8MN_PAD_SD1_DATA2__UART2_DCE_TX = IOMUX_PAD(0x0318, 0x00B0, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA2__UART2_DTE_RX = IOMUX_PAD(0x0318, 0x00B0, 4, 0x04FC, 4, 0),
+ IMX8MN_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA3__ENET1_RGMII_RD1 = IOMUX_PAD(0x031C, 0x00B4, 1, 0x0554, 1, 0),
+ IMX8MN_PAD_SD1_DATA3__UART2_DCE_RX = IOMUX_PAD(0x031C, 0x00B4, 4, 0x04FC, 5, 0),
+ IMX8MN_PAD_SD1_DATA3__UART2_DTE_TX = IOMUX_PAD(0x031C, 0x00B4, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0320, 0x00B8, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0320, 0x00B8, 3, 0x055C, 1, 0),
+ IMX8MN_PAD_SD1_DATA4__UART2_DCE_RTS_B = IOMUX_PAD(0x0320, 0x00B8, 4, 0x04F8, 4, 0),
+ IMX8MN_PAD_SD1_DATA4__UART2_DTE_CTS_B = IOMUX_PAD(0x0320, 0x00B8, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0324, 0x00BC, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0324, 0x00BC, 3, 0x056C, 1, 0),
+ IMX8MN_PAD_SD1_DATA5__UART2_DCE_CTS_B = IOMUX_PAD(0x0324, 0x00BC, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA5__UART2_DTE_RTS_B = IOMUX_PAD(0x0324, 0x00BC, 4, 0x04F8, 5, 0),
+ IMX8MN_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x0328, 0x00C0, 1, 0x0574, 1, 0),
+ IMX8MN_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x0328, 0x00C0, 3, 0x05D0, 1, 0),
+ IMX8MN_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0504, 4, 0),
+ IMX8MN_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x032C, 0x00C4, 1, 0x05C8, 1, 0),
+ IMX8MN_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x032C, 0x00C4, 3, 0x0560, 1, 0),
+ IMX8MN_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0504, 5, 0),
+ IMX8MN_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 1, 0),
+ IMX8MN_PAD_SD1_RESET_B__CCMSRCGPCMIX_ENET_REF_CLK_ROOT = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 0, 0),
+ IMX8MN_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0330, 0x00C8, 3, 0x0588, 1, 0),
+ IMX8MN_PAD_SD1_RESET_B__UART3_DCE_RTS_B = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0500, 2, 0),
+ IMX8MN_PAD_SD1_RESET_B__UART3_DTE_CTS_B = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0334, 0x00CC, 3, 0x05BC, 1, 0),
+ IMX8MN_PAD_SD1_STROBE__UART3_DCE_CTS_B = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD1_STROBE__UART3_DTE_RTS_B = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0500, 3, 0),
+ IMX8MN_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK = IOMUX_PAD(0x0338, 0x00D0, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CLK__SAI5_RX_SYNC = IOMUX_PAD(0x033C, 0x00D4, 1, 0x04E4, 1, 0),
+ IMX8MN_PAD_SD2_CLK__ECSPI2_SCLK = IOMUX_PAD(0x033C, 0x00D4, 2, 0x0580, 1, 0),
+ IMX8MN_PAD_SD2_CLK__UART4_DCE_RX = IOMUX_PAD(0x033C, 0x00D4, 3, 0x050C, 4, 0),
+ IMX8MN_PAD_SD2_CLK__UART4_DTE_TX = IOMUX_PAD(0x033C, 0x00D4, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CLK__SAI5_MCLK = IOMUX_PAD(0x033C, 0x00D4, 4, 0x0594, 1, 0),
+ IMX8MN_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CMD__SAI5_RX_BCLK = IOMUX_PAD(0x0340, 0x00D8, 1, 0x04D0, 1, 0),
+ IMX8MN_PAD_SD2_CMD__ECSPI2_MOSI = IOMUX_PAD(0x0340, 0x00D8, 2, 0x0590, 1, 0),
+ IMX8MN_PAD_SD2_CMD__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00D8, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CMD__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00D8, 3, 0x050C, 5, 0),
+ IMX8MN_PAD_SD2_CMD__PDM_CLK = IOMUX_PAD(0x0340, 0x00D8, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA0__SAI5_RX_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 1, 0x04D4, 1, 0),
+ IMX8MN_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0344, 0x00DC, 2, 0x058C, 1, 0),
+ IMX8MN_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0344, 0x00DC, 3, 0x04FC, 6, 0),
+ IMX8MN_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0344, 0x00DC, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA0__PDM_BIT_STREAM0 = IOMUX_PAD(0x0344, 0x00DC, 4, 0x0534, 2, 0),
+ IMX8MN_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA1__SAI5_TX_SYNC = IOMUX_PAD(0x0348, 0x00E0, 1, 0x04EC, 1, 0),
+ IMX8MN_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E0, 2, 0x05D4, 1, 0),
+ IMX8MN_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x0348, 0x00E0, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x0348, 0x00E0, 3, 0x04FC, 7, 0),
+ IMX8MN_PAD_SD2_DATA1__PDM_BIT_STREAM1 = IOMUX_PAD(0x0348, 0x00E0, 4, 0x0538, 4, 0),
+ IMX8MN_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA2__SAI5_TX_BCLK = IOMUX_PAD(0x034C, 0x00E4, 1, 0x04E8, 1, 0),
+ IMX8MN_PAD_SD2_DATA2__ECSPI2_SS0 = IOMUX_PAD(0x034C, 0x00E4, 2, 0x0570, 2, 0),
+ IMX8MN_PAD_SD2_DATA2__SPDIF1_OUT = IOMUX_PAD(0x034C, 0x00E4, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA2__PDM_BIT_STREAM2 = IOMUX_PAD(0x034C, 0x00E4, 4, 0x053C, 4, 0),
+ IMX8MN_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA3__SAI5_TX_DATA0 = IOMUX_PAD(0x0350, 0x00E8, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA3__ECSPI2_MISO = IOMUX_PAD(0x0350, 0x00E8, 2, 0x0578, 1, 0),
+ IMX8MN_PAD_SD2_DATA3__SPDIF1_IN = IOMUX_PAD(0x0350, 0x00E8, 3, 0x05CC, 2, 0),
+ IMX8MN_PAD_SD2_DATA3__PDM_BIT_STREAM3 = IOMUX_PAD(0x0350, 0x00E8, 4, 0x0540, 4, 0),
+ IMX8MN_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SD2_WP__CORESIGHT_EVENTI = IOMUX_PAD(0x0358, 0x00F0, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_ALE__PDM_BIT_STREAM0 = IOMUX_PAD(0x035C, 0x00F4, 3, 0x0534, 3, 0),
+ IMX8MN_PAD_NAND_ALE__UART3_DCE_RX = IOMUX_PAD(0x035C, 0x00F4, 4, 0x0504, 6, 0),
+ IMX8MN_PAD_NAND_ALE__UART3_DTE_TX = IOMUX_PAD(0x035C, 0x00F4, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_ALE__CORESIGHT_TRACE_CLK = IOMUX_PAD(0x035C, 0x00F4, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE0_B__PDM_BIT_STREAM1 = IOMUX_PAD(0x0360, 0x00F8, 3, 0x0538, 5, 0),
+ IMX8MN_PAD_NAND_CE0_B__UART3_DCE_TX = IOMUX_PAD(0x0360, 0x00F8, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE0_B__UART3_DTE_RX = IOMUX_PAD(0x0360, 0x00F8, 4, 0x0504, 7, 0),
+ IMX8MN_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL = IOMUX_PAD(0x0360, 0x00F8, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x059C, 0, 0),
+ IMX8MN_PAD_NAND_CE1_B__PDM_BIT_STREAM0 = IOMUX_PAD(0x0364, 0x00FC, 3, 0x0534, 4, 0),
+ IMX8MN_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0364, 0x00FC, 4, 0x05D4, 2, 0),
+ IMX8MN_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE1_B__CORESIGHT_TRACE0 = IOMUX_PAD(0x0364, 0x00FC, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0550, 0, 0),
+ IMX8MN_PAD_NAND_CE2_B__PDM_BIT_STREAM1 = IOMUX_PAD(0x0368, 0x0100, 3, 0x0538, 6, 0),
+ IMX8MN_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x0368, 0x0100, 4, 0x058C, 2, 0),
+ IMX8MN_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE2_B__CORESIGHT_TRACE1 = IOMUX_PAD(0x0368, 0x0100, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0584, 0, 0),
+ IMX8MN_PAD_NAND_CE3_B__PDM_BIT_STREAM2 = IOMUX_PAD(0x036C, 0x0104, 3, 0x053C, 5, 0),
+ IMX8MN_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x036C, 0x0104, 4, 0x05BC, 2, 0),
+ IMX8MN_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CE3_B__CORESIGHT_TRACE2 = IOMUX_PAD(0x036C, 0x0104, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CLE__USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x054C, 0, 0),
+ IMX8MN_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_CLE__CORESIGHT_TRACE3 = IOMUX_PAD(0x0370, 0x0108, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA00__PDM_BIT_STREAM2 = IOMUX_PAD(0x0374, 0x010C, 3, 0x053C, 6, 0),
+ IMX8MN_PAD_NAND_DATA00__UART4_DCE_RX = IOMUX_PAD(0x0374, 0x010C, 4, 0x050C, 6, 0),
+ IMX8MN_PAD_NAND_DATA00__UART4_DTE_TX = IOMUX_PAD(0x0374, 0x010C, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA00__CORESIGHT_TRACE4 = IOMUX_PAD(0x0374, 0x010C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA01__PDM_BIT_STREAM3 = IOMUX_PAD(0x0378, 0x0110, 3, 0x0540, 5, 0),
+ IMX8MN_PAD_NAND_DATA01__UART4_DCE_TX = IOMUX_PAD(0x0378, 0x0110, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA01__UART4_DTE_RX = IOMUX_PAD(0x0378, 0x0110, 4, 0x050C, 7, 0),
+ IMX8MN_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA01__CORESIGHT_TRACE5 = IOMUX_PAD(0x0378, 0x0110, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0598, 0, 0),
+ IMX8MN_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x037C, 0x0114, 4, 0x058C, 3, 0),
+ IMX8MN_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA02__CORESIGHT_TRACE6 = IOMUX_PAD(0x037C, 0x0114, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA03__USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x05B8, 0, 0),
+ IMX8MN_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA03__CORESIGHT_TRACE7 = IOMUX_PAD(0x0380, 0x0118, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA04__USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x05B4, 0, 0),
+ IMX8MN_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA04__CORESIGHT_TRACE8 = IOMUX_PAD(0x0384, 0x011C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA05__USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x05B0, 0, 0),
+ IMX8MN_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA05__CORESIGHT_TRACE9 = IOMUX_PAD(0x0388, 0x0120, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA06__USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x05E4, 0, 0),
+ IMX8MN_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA06__CORESIGHT_TRACE10 = IOMUX_PAD(0x038C, 0x0124, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA07__USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x05E0, 0, 0),
+ IMX8MN_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DATA07__CORESIGHT_TRACE11 = IOMUX_PAD(0x0390, 0x0128, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DQS__PDM_CLK = IOMUX_PAD(0x0394, 0x012C, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0394, 0x012C, 4, 0x0588, 2, 0),
+ IMX8MN_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0394, 0x012C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_RE_B__USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0558, 0, 0),
+ IMX8MN_PAD_NAND_RE_B__PDM_BIT_STREAM1 = IOMUX_PAD(0x0398, 0x0130, 3, 0x0538, 7, 0),
+ IMX8MN_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_RE_B__CORESIGHT_TRACE13 = IOMUX_PAD(0x0398, 0x0130, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_READY_B__PDM_BIT_STREAM3 = IOMUX_PAD(0x039C, 0x0134, 3, 0x0540, 6, 0),
+ IMX8MN_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x039C, 0x0134, 4, 0x0588, 3, 0),
+ IMX8MN_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x039C, 0x0134, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x05A0, 0, 0),
+ IMX8MN_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x03A0, 0x0138, 4, 0x05BC, 3, 0),
+ IMX8MN_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x03A0, 0x0138, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x05DC, 0, 0),
+ IMX8MN_PAD_NAND_WP_B__I2C4_SDA = IOMUX_PAD(0x03A4, 0x013C, 4, 0x058C, 4, 0),
+ IMX8MN_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x03A4, 0x013C, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+ IMX8MN_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+ IMX8MN_PAD_SAI5_RXC__PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+ IMX8MN_PAD_SAI5_RXD0__PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
+ IMX8MN_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+ IMX8MN_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+ IMX8MN_PAD_SAI5_RXD1__PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
+ IMX8MN_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+ IMX8MN_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+ IMX8MN_PAD_SAI5_RXD2__PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
+ IMX8MN_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+ IMX8MN_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI5_RXD3__PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
+ IMX8MN_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x0594, 0, 0),
+ IMX8MN_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+ IMX8MN_PAD_SAI2_RXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXFS__SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x05AC, 0, 0),
+ IMX8MN_PAD_SAI2_RXFS__UART1_DCE_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXFS__UART1_DTE_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
+ IMX8MN_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXFS__PDM_BIT_STREAM2 = IOMUX_PAD(0x0418, 0x01B0, 6, 0x053C, 7, 0),
+
+ IMX8MN_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+ IMX8MN_PAD_SAI2_RXC__UART1_DCE_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
+ IMX8MN_PAD_SAI2_RXC__UART1_DTE_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXC__PDM_BIT_STREAM1 = IOMUX_PAD(0x041C, 0x01B4, 6, 0x0538, 8, 0),
+
+ IMX8MN_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXD0__SAI2_TX_DATA1 = IOMUX_PAD(0x0420, 0x01B8, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXD0__UART1_DCE_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
+ IMX8MN_PAD_SAI2_RXD0__UART1_DTE_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_RXD0__PDM_BIT_STREAM3 = IOMUX_PAD(0x0420, 0x01B8, 6, 0x0540, 7, 0),
+
+ IMX8MN_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXFS__SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXFS__UART1_DCE_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXFS__UART1_DTE_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
+ IMX8MN_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXFS__PDM_BIT_STREAM2 = IOMUX_PAD(0x0424, 0x01BC, 6, 0x053C, 8, 0),
+
+ IMX8MN_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXC__PDM_BIT_STREAM1 = IOMUX_PAD(0x0428, 0x01C0, 6, 0x0538, 9, 0),
+
+ IMX8MN_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE4 = IOMUX_PAD(0x042C, 0x01C4, 6, 0x0540, 8, 0),
+
+ IMX8MN_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x0594, 2, 0),
+ IMX8MN_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI2_MCLK__SAI3_MCLK = IOMUX_PAD(0x0430, 0x01C8, 6, 0x05C0, 1, 0),
+
+ IMX8MN_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x05F0, 0, 0),
+ IMX8MN_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+ IMX8MN_PAD_SAI3_RXFS__SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXFS__SPDIF1_IN = IOMUX_PAD(0x0434, 0x01CC, 4, 0x05CC, 3, 0),
+ IMX8MN_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXFS__PDM_BIT_STREAM0 = IOMUX_PAD(0x0434, 0x01CC, 6, 0x0534, 5, 0),
+
+ IMX8MN_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXC__GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x05E8, 0, 0),
+ IMX8MN_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+ IMX8MN_PAD_SAI3_RXC__SAI2_RX_DATA1 = IOMUX_PAD(0x0438, 0x01D0, 3, 0x05AC, 2, 0),
+ IMX8MN_PAD_SAI3_RXC__UART2_DCE_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXC__UART2_DTE_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
+ IMX8MN_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXC__PDM_CLK = IOMUX_PAD(0x0438, 0x01D0, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+ IMX8MN_PAD_SAI3_RXD__SAI3_TX_DATA1 = IOMUX_PAD(0x043C, 0x01D4, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXD__UART2_DCE_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
+ IMX8MN_PAD_SAI3_RXD__UART2_DTE_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_RXD__PDM_BIT_STREAM1 = IOMUX_PAD(0x043C, 0x01D4, 6, 0x0538, 10, 0),
+
+ IMX8MN_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXFS__GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x05EC, 0, 0),
+ IMX8MN_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 1, 0),
+ IMX8MN_PAD_SAI3_TXFS__SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXFS__UART2_DCE_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
+ IMX8MN_PAD_SAI3_TXFS__UART2_DTE_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXFS__PDM_BIT_STREAM3 = IOMUX_PAD(0x0440, 0x01D8, 6, 0x0540, 9, 0),
+
+ IMX8MN_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 1, 0),
+ IMX8MN_PAD_SAI3_TXC__SAI2_TX_DATA1 = IOMUX_PAD(0x0444, 0x01DC, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXC__UART2_DCE_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXC__UART2_DTE_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
+ IMX8MN_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXC__PDM_BIT_STREAM2 = IOMUX_PAD(0x0444, 0x01DC, 6, 0x053C, 9, 0),
+
+ IMX8MN_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 1, 0),
+ IMX8MN_PAD_SAI3_TXD__SPDIF1_EXT_CLK = IOMUX_PAD(0x0448, 0x01E0, 4, 0x0568, 2, 0),
+ IMX8MN_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE5 = IOMUX_PAD(0x0448, 0x01E0, 6, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x05C0, 0, 0),
+ IMX8MN_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x0594, 3, 0),
+ IMX8MN_PAD_SAI3_MCLK__SPDIF1_OUT = IOMUX_PAD(0x044C, 0x01E4, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+ IMX8MN_PAD_SAI3_MCLK__SPDIF1_IN = IOMUX_PAD(0x044C, 0x01E4, 6, 0x05CC, 4, 0),
+
+ IMX8MN_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x05CC, 0, 0),
+ IMX8MN_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0568, 0, 0),
+ IMX8MN_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x05D8, 0, 0),
+ IMX8MN_PAD_ECSPI1_SCLK__UART3_DCE_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+ IMX8MN_PAD_ECSPI1_SCLK__UART3_DTE_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x045C, 0x01F4, 2, 0x055C, 2, 0),
+ IMX8MN_PAD_ECSPI1_SCLK__SAI5_RX_SYNC = IOMUX_PAD(0x045C, 0x01F4, 3, 0x04DC, 2, 0),
+ IMX8MN_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x05A8, 0, 0),
+ IMX8MN_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI1_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+ IMX8MN_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0460, 0x01F8, 2, 0x056C, 2, 0),
+ IMX8MN_PAD_ECSPI1_MOSI__SAI5_RX_BCLK = IOMUX_PAD(0x0460, 0x01F8, 3, 0x04D0, 3, 0),
+ IMX8MN_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x05C4, 0, 0),
+ IMX8MN_PAD_ECSPI1_MISO__UART3_DCE_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI1_MISO__UART3_DTE_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+ IMX8MN_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0464, 0x01FC, 2, 0x05D0, 2, 0),
+ IMX8MN_PAD_ECSPI1_MISO__SAI5_RX_DATA0 = IOMUX_PAD(0x0464, 0x01FC, 3, 0x04D4, 3, 0),
+ IMX8MN_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0564, 0, 0),
+ IMX8MN_PAD_ECSPI1_SS0__UART3_DCE_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+ IMX8MN_PAD_ECSPI1_SS0__UART3_DTE_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x0468, 0x0200, 2, 0x0560, 2, 0),
+ IMX8MN_PAD_ECSPI1_SS0__SAI5_RX_DATA1 = IOMUX_PAD(0x0468, 0x0200, 3, 0x04D8, 2, 0),
+ IMX8MN_PAD_ECSPI1_SS0__SAI5_TX_SYNC = IOMUX_PAD(0x0468, 0x0200, 4, 0x04EC, 3, 0),
+ IMX8MN_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0580, 0, 0),
+ IMX8MN_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+ IMX8MN_PAD_ECSPI2_SCLK__UART4_DTE_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x046C, 0x0204, 2, 0x0588, 4, 0),
+ IMX8MN_PAD_ECSPI2_SCLK__SAI5_RX_DATA2 = IOMUX_PAD(0x046C, 0x0204, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI2_SCLK__SAI5_TX_BCLK = IOMUX_PAD(0x046C, 0x0204, 4, 0x04E8, 3, 0),
+ IMX8MN_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0590, 0, 0),
+ IMX8MN_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI2_MOSI__UART4_DTE_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+ IMX8MN_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0470, 0x0208, 2, 0x05BC, 4, 0),
+ IMX8MN_PAD_ECSPI2_MOSI__SAI5_RX_DATA3 = IOMUX_PAD(0x0470, 0x0208, 3, 0x04E0, 2, 0),
+ IMX8MN_PAD_ECSPI2_MOSI__SAI5_TX_DATA0 = IOMUX_PAD(0x0470, 0x0208, 4, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0578, 0, 0),
+ IMX8MN_PAD_ECSPI2_MISO__UART4_DCE_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI2_MISO__UART4_DTE_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+ IMX8MN_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0474, 0x020C, 2, 0x05D4, 3, 0),
+ IMX8MN_PAD_ECSPI2_MISO__SAI5_MCLK = IOMUX_PAD(0x0474, 0x020C, 3, 0x0594, 4, 0),
+ IMX8MN_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0570, 0, 0),
+ IMX8MN_PAD_ECSPI2_SS0__UART4_DCE_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+ IMX8MN_PAD_ECSPI2_SS0__UART4_DTE_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x0478, 0x0210, 2, 0x058C, 5, 0),
+ IMX8MN_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x055C, 0, 0),
+ IMX8MN_PAD_I2C1_SCL__ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C1_SCL__ECSPI1_SCLK = IOMUX_PAD(0x047C, 0x0214, 3, 0x05D8, 1, 0),
+ IMX8MN_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x056C, 0, 0),
+ IMX8MN_PAD_I2C1_SDA__ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+ IMX8MN_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0480, 0x0218, 3, 0x05A8, 1, 0),
+ IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x05D0, 0, 0),
+ IMX8MN_PAD_I2C2_SCL__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C2_SCL__USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0598, 1, 0),
+ IMX8MN_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0484, 0x021C, 3, 0x05C4, 1, 0),
+ IMX8MN_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0560, 0, 0),
+ IMX8MN_PAD_I2C2_SDA__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x05B8, 1, 0),
+ IMX8MN_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x0488, 0x0220, 3, 0x0564, 1, 0),
+ IMX8MN_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0588, 0, 0),
+ IMX8MN_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x048C, 0x0224, 3, 0x0580, 2, 0),
+ IMX8MN_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x05BC, 0, 0),
+ IMX8MN_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0490, 0x0228, 3, 0x0590, 2, 0),
+ IMX8MN_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x05D4, 0, 0),
+ IMX8MN_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0494, 0x022C, 3, 0x0578, 2, 0),
+ IMX8MN_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x058C, 0, 0),
+ IMX8MN_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x0498, 0x0230, 3, 0x0570, 1, 0),
+ IMX8MN_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+ IMX8MN_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
+ IMX8MN_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART2_RXD__UART2_DCE_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+ IMX8MN_PAD_UART2_RXD__UART2_DTE_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART2_RXD__GPT1_COMPARE3 = IOMUX_PAD(0x04A4, 0x023C, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART2_TXD__UART2_DCE_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART2_TXD__UART2_DTE_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
+ IMX8MN_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART2_TXD__GPT1_COMPARE2 = IOMUX_PAD(0x04A8, 0x0240, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART3_RXD__UART3_DCE_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+ IMX8MN_PAD_UART3_RXD__UART3_DTE_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART3_RXD__UART1_DCE_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART3_RXD__UART1_DTE_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+ IMX8MN_PAD_UART3_RXD__USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_UART3_RXD__GPT1_CAPTURE2 = IOMUX_PAD(0x04AC, 0x0244, 3, 0x05EC, 1, 0),
+ IMX8MN_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART3_TXD__UART3_DCE_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART3_TXD__UART3_DTE_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
+ IMX8MN_PAD_UART3_TXD__UART1_DCE_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+ IMX8MN_PAD_UART3_TXD__UART1_DTE_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART3_TXD__USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
+ IMX8MN_PAD_UART3_TXD__GPT1_CLK = IOMUX_PAD(0x04B0, 0x0248, 3, 0x05E8, 1, 0),
+ IMX8MN_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART4_RXD__UART4_DCE_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+ IMX8MN_PAD_UART4_RXD__UART4_DTE_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART4_RXD__UART2_DCE_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART4_RXD__UART2_DTE_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+ IMX8MN_PAD_UART4_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x04B4, 0x024C, 3, 0x0000, 0, 0),
+ IMX8MN_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+ IMX8MN_PAD_UART4_TXD__UART4_DCE_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+ IMX8MN_PAD_UART4_TXD__UART4_DTE_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
+ IMX8MN_PAD_UART4_TXD__UART2_DCE_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+ IMX8MN_PAD_UART4_TXD__UART2_DTE_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
+ IMX8MN_PAD_UART4_TXD__GPT1_CAPTURE1 = IOMUX_PAD(0x04B8, 0x0250, 3, 0x05F0, 1, 0),
+ IMX8MN_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX8MN_PINS_H__ */
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index 720e8f7..3d5586e 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -104,7 +104,7 @@
#define PAD_CTL_ODE (0x1 << 5)
#define PAD_CTL_PUE (0x1 << 6)
#define PAD_CTL_HYS (0x1 << 7)
-#ifdef CONFIG_IMX8MM
+#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
#define PAD_CTL_PE (0x1 << 8)
#else
#define PAD_CTL_LVTTL (0x1 << 8)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 1e627c8..52c83ba 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -53,6 +53,8 @@
#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN))
+
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#ifdef CONFIG_MX6
@@ -104,6 +106,39 @@
#endif /* CONFIG_MX6 */
+#ifdef CONFIG_IMX8M
+struct rom_api {
+ u16 ver;
+ u16 tag;
+ u32 reserved1;
+ u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
+ u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
+};
+
+enum boot_dev_type_e {
+ BT_DEV_TYPE_SD = 1,
+ BT_DEV_TYPE_MMC = 2,
+ BT_DEV_TYPE_NAND = 3,
+ BT_DEV_TYPE_FLEXSPINOR = 4,
+
+ BT_DEV_TYPE_USB = 0xE,
+ BT_DEV_TYPE_MEM_DEV = 0xF,
+
+ BT_DEV_TYPE_INVALID = 0xFF
+};
+
+#define QUERY_ROM_VER 1
+#define QUERY_BT_DEV 2
+#define QUERY_PAGE_SZ 3
+#define QUERY_IVT_OFF 4
+#define QUERY_BT_STAGE 5
+#define QUERY_IMG_OFF 6
+
+#define ROM_API_OKAY 0xF0
+
+extern struct rom_api *g_rom_api;
+#endif
+
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_speed_grade_hz(void);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3f93fe5..751c0b5 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -109,3 +109,7 @@
NXP does NOT recommend to perform this calibration at each boot. One
shall perform it on a new PCB and then use those values to program
the ddrmc_cr_setting on relevant board file.
+
+config SPL_IMX_ROMAPI_LOADADDR
+ hex "Default load address to load image through ROM API"
+ depends on IMX8MN
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 6e87dc5..e14713c 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -226,3 +226,5 @@
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
+
+obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d39f607..51c7c05 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -92,6 +92,8 @@
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_IMX8MN:
+ return "8MNano";/* Quad-core version of the imx8mn */
case MXC_CPU_IMX8MM:
return "8MMQ"; /* Quad-core version of the imx8mm */
case MXC_CPU_IMX8MML:
@@ -375,7 +377,7 @@
}
#endif
-#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
enum boot_device get_boot_device(void)
{
struct bootrom_sw_info **p =
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index f520075..eb4a73b 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -12,6 +12,10 @@
bool
select IMX8M
+config IMX8MN
+ bool
+ select IMX8M
+
config SYS_SOC
default "imx8m"
@@ -30,9 +34,16 @@
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_IMX8MN_EVK
+ bool "imx8mn DDR4 EVK board"
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_DDR4
+
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
+source "board/freescale/imx8mn_evk/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index 92184f3..db4ba30 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -5,4 +5,4 @@
obj-y += lowlevel_init.o
obj-y += clock_slice.o soc.o
obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
-obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
+obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN) += clock_imx8mm.o
diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 780f643..09c5615 100644
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -475,7 +475,7 @@
{DRAM_PLL1_CLK}
},
};
-#elif defined(CONFIG_IMX8MM)
+#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
static struct clk_root_map root_array[] = {
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
@@ -487,11 +487,13 @@
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
+#ifdef CONFIG_IMX8MM
{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
+#endif
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
diff --git a/arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg
new file mode 100644
index 0000000..1405c65
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+FIT
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER spl/u-boot-spl-ddr.bin 0x912000
+SECOND_LOADER u-boot.itb 0x40200000 0x60000
+
+DDR_FW ddr4_imem_1d.bin
+DDR_FW ddr4_dmem_1d.bin
+DDR_FW ddr4_imem_2d.bin
+DDR_FW ddr4_dmem_2d.bin
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a924af4..9a203e4 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -56,7 +56,7 @@
/* Enable TZASC and lock setting */
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
- if (IS_ENABLED(CONFIG_IMX8MM))
+ if (is_imx8mm() || is_imx8mn())
setbits_le32(&gpr->gpr[10], BIT(1));
/*
* set Region 0 attribute to allow secure and non-secure
@@ -197,7 +197,9 @@
reg &= 0xff;
/* i.MX8MM */
- if (major_low == 0x41) {
+ if (major_low == 0x42) {
+ return (MXC_CPU_IMX8MN << 12) | reg;
+ } else if (major_low == 0x41) {
type = get_cpu_variant_type(MXC_CPU_IMX8MM);
} else {
if (reg == CHIP_REV_1_0) {
@@ -241,12 +243,14 @@
struct udevice *dev;
int ret;
- ret = uclass_get_device_by_name(UCLASS_CLK,
- "clock-controller@30380000",
- &dev);
- if (ret < 0) {
- printf("Failed to find clock node. Check device tree\n");
- return ret;
+ if (CONFIG_IS_ENABLED(CLK)) {
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ return ret;
+ }
}
return 0;
@@ -281,6 +285,54 @@
return 0;
}
+#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+struct rom_api *g_rom_api = (struct rom_api *)0x980;
+
+enum boot_device get_boot_device(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+ enum boot_device boot_dev = SD1_BOOT;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return -1;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ switch (boot_type) {
+ case BT_DEV_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BT_DEV_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BT_DEV_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BT_DEV_TYPE_FLEXSPINOR:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BT_DEV_TYPE_USB:
+ boot_dev = USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+#endif
+
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 5cc74b6..dde1635 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -135,7 +135,7 @@
enum boot_device boot_device_spl = get_boot_device();
- if (IS_ENABLED(CONFIG_IMX8MM))
+ if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN))
return spl_board_boot_device(boot_device_spl);
switch (boot_device_spl) {
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
new file mode 100644
index 0000000..5dc0f71
--- /dev/null
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <image.h>
+#include <linux/libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int is_boot_from_stream_device(u32 boot)
+{
+ u32 interface;
+
+ interface = boot >> 16;
+ if (interface >= BT_DEV_TYPE_USB)
+ return 1;
+
+ if (interface == BT_DEV_TYPE_MMC && (boot & 1))
+ return 1;
+
+ return 0;
+}
+
+static ulong spl_romapi_read_seekable(struct spl_load_info *load,
+ ulong sector, ulong count,
+ void *buf)
+{
+ u32 pagesize = *(u32 *)load->priv;
+ volatile gd_t *pgd = gd;
+ ulong byte = count * pagesize;
+ int ret;
+ u32 offset;
+
+ offset = sector * pagesize;
+
+ debug("ROM API load from 0x%x, size 0x%x\n", offset, (u32)byte);
+
+ ret = g_rom_api->download_image(buf, offset, byte,
+ ((uintptr_t)buf) ^ offset ^ byte);
+ gd = pgd;
+
+ if (ret == ROM_API_OKAY)
+ return count;
+
+ printf("ROM API Failure when load 0x%x\n", offset);
+
+ return 0;
+}
+
+static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev,
+ u32 rom_bt_dev)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 offset;
+ u32 pagesize, size;
+ struct image_header *header;
+ u32 image_offset;
+
+ ret = g_rom_api->query_boot_infor(QUERY_IVT_OFF, &offset,
+ ((uintptr_t)&offset) ^ QUERY_IVT_OFF);
+ ret |= g_rom_api->query_boot_infor(QUERY_PAGE_SZ, &pagesize,
+ ((uintptr_t)&pagesize) ^ QUERY_PAGE_SZ);
+ ret |= g_rom_api->query_boot_infor(QUERY_IMG_OFF, &image_offset,
+ ((uintptr_t)&image_offset) ^ QUERY_IMG_OFF);
+
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: Failure query boot infor pagesize/offset\n");
+ return -1;
+ }
+
+ header = (struct image_header *)(CONFIG_SPL_IMX_ROMAPI_LOADADDR);
+
+ printf("image offset 0x%x, pagesize 0x%x, ivt offset 0x%x\n",
+ image_offset, pagesize, offset);
+
+ if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_FLEXSPINOR)
+ offset = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512;
+ else
+ offset = image_offset +
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
+
+ size = ALIGN(sizeof(struct image_header), pagesize);
+ ret = g_rom_api->download_image((u8 *)header, offset, size,
+ ((uintptr_t)header) ^ offset ^ size);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ printf("ROMAPI: download failure offset 0x%x size 0x%x\n",
+ offset, size);
+ return -1;
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ memset(&load, 0, sizeof(load));
+ load.bl_len = pagesize;
+ load.read = spl_romapi_read_seekable;
+ load.priv = &pagesize;
+ return spl_load_simple_fit(spl_image, &load,
+ offset / pagesize, header);
+ } else {
+ /* TODO */
+ puts("Can't support legacy image\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ memcpy(buf, (void *)(sector), count);
+
+ if (load->priv) {
+ ulong *p = (ulong *)load->priv;
+ ulong total = sector + count;
+
+ if (total > *p)
+ *p = total;
+ }
+
+ return count;
+}
+
+static ulong get_fit_image_size(void *fit)
+{
+ struct spl_image_info spl_image;
+ struct spl_load_info spl_load_info;
+ ulong last = (ulong)fit;
+
+ memset(&spl_load_info, 0, sizeof(spl_load_info));
+ spl_load_info.bl_len = 1;
+ spl_load_info.read = spl_ram_load_read;
+ spl_load_info.priv = &last;
+
+ spl_load_simple_fit(&spl_image, &spl_load_info,
+ (uintptr_t)fit, fit);
+
+ return last - (ulong)fit;
+}
+
+u8 *search_fit_header(u8 *p, int size)
+{
+ int i;
+
+ for (i = 0; i < size; i += 4)
+ if (genimg_get_format(p + i) == IMAGE_FORMAT_FIT)
+ return p + i;
+
+ return NULL;
+}
+
+static int spl_romapi_load_image_stream(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ struct spl_load_info load;
+ volatile gd_t *pgd = gd;
+ u32 pagesize, pg;
+ int ret;
+ int i = 0;
+ u8 *p = (u8 *)CONFIG_SPL_IMX_ROMAPI_LOADADDR;
+ u8 *pfit = NULL;
+ int imagesize;
+ int total;
+
+ ret = g_rom_api->query_boot_infor(QUERY_PAGE_SZ, &pagesize,
+ ((uintptr_t)&pagesize) ^ QUERY_PAGE_SZ);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY)
+ puts("failure at query_boot_info\n");
+
+ pg = pagesize;
+ if (pg < 1024)
+ pg = 1024;
+
+ for (i = 0; i < 640; i++) {
+ ret = g_rom_api->download_image(p, 0, pg,
+ ((uintptr_t)p) ^ pg);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ puts("Steam(USB) download failure\n");
+ return -1;
+ }
+
+ pfit = search_fit_header(p, pg);
+ p += pg;
+
+ if (pfit)
+ break;
+ }
+
+ if (!pfit) {
+ puts("Can't found uboot FIT image in 640K range \n");
+ return -1;
+ }
+
+ if (p - pfit < sizeof(struct fdt_header)) {
+ ret = g_rom_api->download_image(p, 0, pg, ((uintptr_t)p) ^ pg);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ puts("Steam(USB) download failure\n");
+ return -1;
+ }
+
+ p += pg;
+ }
+
+ imagesize = fit_get_size(pfit);
+ printf("Find FIT header 0x&%p, size %d\n", pfit, imagesize);
+
+ if (p - pfit < imagesize) {
+ imagesize -= p - pfit;
+ /*need pagesize hear after ROM fix USB problme*/
+ imagesize += pg - 1;
+ imagesize /= pg;
+ imagesize *= pg;
+
+ printf("Need continue download %d\n", imagesize);
+
+ ret = g_rom_api->download_image(p, 0, imagesize,
+ ((uintptr_t)p) ^ imagesize);
+ gd = pgd;
+
+ p += imagesize;
+
+ if (ret != ROM_API_OKAY) {
+ printf("Failure download %d\n", imagesize);
+ return -1;
+ }
+ }
+
+ total = get_fit_image_size(pfit);
+ total += 3;
+ total &= ~0x3;
+
+ imagesize = total - (p - pfit);
+
+ imagesize += pagesize - 1;
+ imagesize /= pagesize;
+ imagesize *= pagesize;
+
+ printf("Download %d, total fit %d\n", imagesize, total);
+
+ ret = g_rom_api->download_image(p, 0, imagesize,
+ ((uintptr_t)p) ^ imagesize);
+ if (ret != ROM_API_OKAY)
+ printf("ROM download failure %d\n", imagesize);
+
+ memset(&load, 0, sizeof(load));
+ load.bl_len = 1;
+ load.read = spl_ram_load_read;
+
+ return spl_load_simple_fit(spl_image, &load, (ulong)pfit, pfit);
+}
+
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return -1;
+ }
+
+ if (is_boot_from_stream_device(boot))
+ return spl_romapi_load_image_stream(spl_image, bootdev);
+
+ return spl_romapi_load_image_seekable(spl_image, bootdev, boot);
+}
diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
index e474233..a0af550 100644
--- a/board/freescale/imx8mm_evk/imx8mm_evk.c
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -4,6 +4,11 @@
*/
#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -14,8 +19,40 @@
return 0;
}
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
int board_init(void)
{
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
return 0;
}
diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig
new file mode 100644
index 0000000..38ac846
--- /dev/null
+++ b/board/freescale/imx8mn_evk/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8MN_EVK
+
+config SYS_BOARD
+ default "imx8mn_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx8mn_evk"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8mn_evk/MAINTAINERS b/board/freescale/imx8mn_evk/MAINTAINERS
new file mode 100644
index 0000000..3b0653d
--- /dev/null
+++ b/board/freescale/imx8mn_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MM EVK BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/imx8mn_evk/
+F: include/configs/imx8mn_evk.h
+F: configs/imx8mn_ddr4_evk_defconfig
diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile
new file mode 100644
index 0000000..9511a70
--- /dev/null
+++ b/board/freescale/imx8mn_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mn_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c
new file mode 100644
index 0000000..cfd193a
--- /dev/null
+++ b/board/freescale/imx8mn_evk/ddr4_timing.c
@@ -0,0 +1,1214 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x3d400000, 0x81040010},
+ {0x3d400030, 0x00000020},
+ {0x3d400034, 0x00221306},
+ {0x3d400050, 0x00210070},
+ {0x3d400054, 0x00010008},
+ {0x3d400060, 0x00000000},
+ {0x3d400064, 0x0092014a},
+ {0x3d4000c0, 0x00000000},
+ {0x3d4000c4, 0x00001000},
+ {0x3d4000d0, 0xc0030126},
+ {0x3d4000d4, 0x00770000},
+ {0x3d4000dc, 0x08340105},
+ {0x3d4000e0, 0x00180200},
+ {0x3d4000e4, 0x00110000},
+ {0x3d4000e8, 0x02000740},
+ {0x3d4000ec, 0x00000850},
+ {0x3d4000f4, 0x00000ec7},
+ {0x3d400100, 0x11122914},
+ {0x3d400104, 0x0004051c},
+ {0x3d400108, 0x0608050d},
+ {0x3d40010c, 0x0000400c},
+ {0x3d400110, 0x08030409},
+ {0x3d400114, 0x06060403},
+ {0x3d40011c, 0x00000606},
+ {0x3d400120, 0x07070d0c},
+ {0x3d400124, 0x0002040a},
+ {0x3d40012c, 0x1809010e},
+ {0x3d400130, 0x00000008},
+ {0x3d40013c, 0x00000000},
+ {0x3d400180, 0x01000040},
+ {0x3d400184, 0x0000493e},
+ {0x3d400190, 0x038b8207},
+ {0x3d400194, 0x02020303},
+ {0x3d400198, 0x07f04011},
+ {0x3d40019c, 0x000000b0},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0x0048005a},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x00000001},
+ {0x3d4001b4, 0x00000b07},
+ {0x3d4001b8, 0x00000004},
+ {0x3d4001c0, 0x00000001},
+ {0x3d4001c4, 0x00000000},
+ {0x3d400240, 0x06000610},
+ {0x3d400244, 0x00001323},
+ {0x3d400200, 0x00003f1f},
+ {0x3d400204, 0x003f0909},
+ {0x3d400208, 0x01010100},
+ {0x3d40020c, 0x01010101},
+ {0x3d400210, 0x00001f1f},
+ {0x3d400214, 0x07070707},
+ {0x3d400218, 0x07070707},
+ {0x3d40021c, 0x00000f07},
+ {0x3d400220, 0x00003f01},
+ {0x3d402050, 0x00210070},
+ {0x3d402064, 0x00180037},
+ {0x3d4020dc, 0x00000105},
+ {0x3d4020e0, 0x00000000},
+ {0x3d4020e8, 0x02000740},
+ {0x3d4020ec, 0x00000050},
+ {0x3d402100, 0x08030604},
+ {0x3d402104, 0x00020205},
+ {0x3d402108, 0x05050309},
+ {0x3d40210c, 0x0000400c},
+ {0x3d402110, 0x02030202},
+ {0x3d402114, 0x03030202},
+ {0x3d402118, 0x0a070008},
+ {0x3d40211c, 0x00000d09},
+ {0x3d402120, 0x08084b09},
+ {0x3d402124, 0x00020308},
+ {0x3d402128, 0x000f0d06},
+ {0x3d40212c, 0x12060111},
+ {0x3d402130, 0x00000008},
+ {0x3d40213c, 0x00000000},
+ {0x3d402180, 0x01000040},
+ {0x3d402190, 0x03848204},
+ {0x3d402194, 0x02020303},
+ {0x3d4021b4, 0x00000404},
+ {0x3d4021b8, 0x00000004},
+ {0x3d402240, 0x07000600},
+ {0x3d403050, 0x00210070},
+ {0x3d403064, 0x0006000d},
+ {0x3d4030dc, 0x00000105},
+ {0x3d4030e0, 0x00000000},
+ {0x3d4030e8, 0x02000740},
+ {0x3d4030ec, 0x00000050},
+ {0x3d403100, 0x07010101},
+ {0x3d403104, 0x00020202},
+ {0x3d403108, 0x05050309},
+ {0x3d40310c, 0x0000400c},
+ {0x3d403110, 0x01030201},
+ {0x3d403114, 0x03030202},
+ {0x3d40311c, 0x00000303},
+ {0x3d403120, 0x02020d02},
+ {0x3d403124, 0x00020208},
+ {0x3d403128, 0x000f0d06},
+ {0x3d40312c, 0x0e02010e},
+ {0x3d403130, 0x00000008},
+ {0x3d40313c, 0x00000000},
+ {0x3d403180, 0x01000040},
+ {0x3d403190, 0x03848204},
+ {0x3d403194, 0x02020303},
+ {0x3d4031b4, 0x00000404},
+ {0x3d4031b8, 0x00000004},
+ {0x3d403240, 0x07000600},
+
+ /* performance setting */
+ { 0x3d400250, 0x00001f05 },
+ { 0x3d400254, 0x1f },
+ { 0x3d400264, 0x900003ff },
+ { 0x3d40026c, 0x200003ff },
+ { 0x3d400494, 0x01000e00 },
+ { 0x3d400498, 0x03ff0000 },
+ { 0x3d40049c, 0x01000e00 },
+ { 0x3d4004a0, 0x03ff0000 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x0001005f, 0x000002fd},
+ {0x0001015f, 0x000002fd},
+ {0x0001105f, 0x000002fd},
+ {0x0001115f, 0x000002fd},
+ {0x0011005f, 0x000002fd},
+ {0x0011015f, 0x000002fd},
+ {0x0011105f, 0x000002fd},
+ {0x0011115f, 0x000002fd},
+ {0x0021005f, 0x000002fd},
+ {0x0021015f, 0x000002fd},
+ {0x0021105f, 0x000002fd},
+ {0x0021115f, 0x000002fd},
+ {0x00000055, 0x00000355},
+ {0x00001055, 0x00000355},
+ {0x00002055, 0x00000355},
+ {0x00003055, 0x00000355},
+ {0x00004055, 0x00000055},
+ {0x00005055, 0x00000055},
+ {0x00006055, 0x00000355},
+ {0x00007055, 0x00000355},
+ {0x00008055, 0x00000355},
+ {0x00009055, 0x00000355},
+ {0x000200c5, 0x0000000a},
+ {0x001200c5, 0x00000007},
+ {0x002200c5, 0x00000007},
+ {0x0002002e, 0x00000002},
+ {0x0012002e, 0x00000002},
+ {0x0022002e, 0x00000002},
+ {0x00020024, 0x00000008},
+ {0x0002003a, 0x00000002},
+ {0x0002007d, 0x00000212},
+ {0x0002007c, 0x00000061},
+ {0x00120024, 0x00000008},
+ {0x0002003a, 0x00000002},
+ {0x0012007d, 0x00000212},
+ {0x0012007c, 0x00000061},
+ {0x00220024, 0x00000008},
+ {0x0002003a, 0x00000002},
+ {0x0022007d, 0x00000212},
+ {0x0022007c, 0x00000061},
+ {0x00020056, 0x00000006},
+ {0x00120056, 0x0000000a},
+ {0x00220056, 0x0000000a},
+ {0x0001004d, 0x0000001a},
+ {0x0001014d, 0x0000001a},
+ {0x0001104d, 0x0000001a},
+ {0x0001114d, 0x0000001a},
+ {0x0011004d, 0x0000001a},
+ {0x0011014d, 0x0000001a},
+ {0x0011104d, 0x0000001a},
+ {0x0011114d, 0x0000001a},
+ {0x0021004d, 0x0000001a},
+ {0x0021014d, 0x0000001a},
+ {0x0021104d, 0x0000001a},
+ {0x0021114d, 0x0000001a},
+ {0x00010049, 0x00000e38},
+ {0x00010149, 0x00000e38},
+ {0x00011049, 0x00000e38},
+ {0x00011149, 0x00000e38},
+ {0x00110049, 0x00000e38},
+ {0x00110149, 0x00000e38},
+ {0x00111049, 0x00000e38},
+ {0x00111149, 0x00000e38},
+ {0x00210049, 0x00000e38},
+ {0x00210149, 0x00000e38},
+ {0x00211049, 0x00000e38},
+ {0x00211149, 0x00000e38},
+ {0x00000043, 0x00000063},
+ {0x00001043, 0x00000063},
+ {0x00002043, 0x00000063},
+ {0x00003043, 0x00000063},
+ {0x00004043, 0x00000063},
+ {0x00005043, 0x00000063},
+ {0x00006043, 0x00000063},
+ {0x00007043, 0x00000063},
+ {0x00008043, 0x00000063},
+ {0x00009043, 0x00000063},
+ {0x00020018, 0x00000001},
+ {0x00020075, 0x00000002},
+ {0x00020050, 0x00000000},
+ {0x00020008, 0x00000258},
+ {0x00120008, 0x00000064},
+ {0x00220008, 0x00000019},
+ {0x00020088, 0x00000009},
+ {0x000200b2, 0x00000268},
+ {0x00010043, 0x000005b1},
+ {0x00010143, 0x000005b1},
+ {0x00011043, 0x000005b1},
+ {0x00011143, 0x000005b1},
+ {0x001200b2, 0x00000268},
+ {0x00110043, 0x000005b1},
+ {0x00110143, 0x000005b1},
+ {0x00111043, 0x000005b1},
+ {0x00111143, 0x000005b1},
+ {0x002200b2, 0x00000268},
+ {0x00210043, 0x000005b1},
+ {0x00210143, 0x000005b1},
+ {0x00211043, 0x000005b1},
+ {0x00211143, 0x000005b1},
+ {0x0002005b, 0x00007529},
+ {0x0002005c, 0x00000000},
+ {0x000200fa, 0x00000001},
+ {0x001200fa, 0x00000001},
+ {0x002200fa, 0x00000001},
+ {0x00020019, 0x00000005},
+ {0x00120019, 0x00000005},
+ {0x00220019, 0x00000005},
+ {0x000200f0, 0x00005665},
+ {0x000200f1, 0x00005555},
+ {0x000200f2, 0x00005555},
+ {0x000200f3, 0x00005555},
+ {0x000200f4, 0x00005555},
+ {0x000200f5, 0x00005555},
+ {0x000200f6, 0x00005555},
+ {0x000200f7, 0x0000f000},
+ {0x0001004a, 0x00000500},
+ {0x0001104a, 0x00000500},
+ {0x00020025, 0x00000000},
+ {0x0002002d, 0x00000000},
+ {0x0012002d, 0x00000000},
+ {0x0022002d, 0x00000000},
+ {0x0002002c, 0x00000000},
+ {0x000200c7, 0x00000021},
+ {0x000200ca, 0x00000024},
+ {0x000200cc, 0x000001f7},
+ {0x001200c7, 0x00000021},
+ {0x001200ca, 0x00000024},
+ {0x001200cc, 0x000001f7},
+ {0x002200c7, 0x00000021},
+ {0x002200ca, 0x00000024},
+ {0x002200cc, 0x000001f7},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x010082, 0x0},
+ {0x110082, 0x0},
+ {0x210082, 0x0},
+ {0x010182, 0x0},
+ {0x110182, 0x0},
+ {0x210182, 0x0},
+ {0x010083, 0x0},
+ {0x110083, 0x0},
+ {0x210083, 0x0},
+ {0x010183, 0x0},
+ {0x110183, 0x0},
+ {0x210183, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x011082, 0x0},
+ {0x111082, 0x0},
+ {0x211082, 0x0},
+ {0x011182, 0x0},
+ {0x111182, 0x0},
+ {0x211182, 0x0},
+ {0x011083, 0x0},
+ {0x111083, 0x0},
+ {0x211083, 0x0},
+ {0x011183, 0x0},
+ {0x111183, 0x0},
+ {0x211183, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0100d2, 0x0},
+ {0x1100d2, 0x0},
+ {0x2100d2, 0x0},
+ {0x0101d2, 0x0},
+ {0x1101d2, 0x0},
+ {0x2101d2, 0x0},
+ {0x0100d3, 0x0},
+ {0x1100d3, 0x0},
+ {0x2100d3, 0x0},
+ {0x0101d3, 0x0},
+ {0x1101d3, 0x0},
+ {0x2101d3, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x0110d2, 0x0},
+ {0x1110d2, 0x0},
+ {0x2110d2, 0x0},
+ {0x0111d2, 0x0},
+ {0x1111d2, 0x0},
+ {0x2111d2, 0x0},
+ {0x0110d3, 0x0},
+ {0x1110d3, 0x0},
+ {0x2110d3, 0x0},
+ {0x0111d3, 0x0},
+ {0x1111d3, 0x0},
+ {0x2111d3, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x01006a, 0x0},
+ {0x01016a, 0x0},
+ {0x01026a, 0x0},
+ {0x01036a, 0x0},
+ {0x01046a, 0x0},
+ {0x01056a, 0x0},
+ {0x01066a, 0x0},
+ {0x01076a, 0x0},
+ {0x01086a, 0x0},
+ {0x01006b, 0x0},
+ {0x01016b, 0x0},
+ {0x01026b, 0x0},
+ {0x01036b, 0x0},
+ {0x01046b, 0x0},
+ {0x01056b, 0x0},
+ {0x01066b, 0x0},
+ {0x01076b, 0x0},
+ {0x01086b, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01106a, 0x0},
+ {0x01116a, 0x0},
+ {0x01126a, 0x0},
+ {0x01136a, 0x0},
+ {0x01146a, 0x0},
+ {0x01156a, 0x0},
+ {0x01166a, 0x0},
+ {0x01176a, 0x0},
+ {0x01186a, 0x0},
+ {0x01106b, 0x0},
+ {0x01116b, 0x0},
+ {0x01126b, 0x0},
+ {0x01136b, 0x0},
+ {0x01146b, 0x0},
+ {0x01156b, 0x0},
+ {0x01166b, 0x0},
+ {0x01176b, 0x0},
+ {0x01186b, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01008e, 0x0},
+ {0x11008e, 0x0},
+ {0x21008e, 0x0},
+ {0x01018e, 0x0},
+ {0x11018e, 0x0},
+ {0x21018e, 0x0},
+ {0x01008f, 0x0},
+ {0x11008f, 0x0},
+ {0x21008f, 0x0},
+ {0x01018f, 0x0},
+ {0x11018f, 0x0},
+ {0x21018f, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x01108e, 0x0},
+ {0x11108e, 0x0},
+ {0x21108e, 0x0},
+ {0x01118e, 0x0},
+ {0x11118e, 0x0},
+ {0x21118e, 0x0},
+ {0x01108f, 0x0},
+ {0x11108f, 0x0},
+ {0x21108f, 0x0},
+ {0x01118f, 0x0},
+ {0x11118f, 0x0},
+ {0x21118f, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0100c2, 0x0},
+ {0x1100c2, 0x0},
+ {0x2100c2, 0x0},
+ {0x0101c2, 0x0},
+ {0x1101c2, 0x0},
+ {0x2101c2, 0x0},
+ {0x0102c2, 0x0},
+ {0x1102c2, 0x0},
+ {0x2102c2, 0x0},
+ {0x0103c2, 0x0},
+ {0x1103c2, 0x0},
+ {0x2103c2, 0x0},
+ {0x0104c2, 0x0},
+ {0x1104c2, 0x0},
+ {0x2104c2, 0x0},
+ {0x0105c2, 0x0},
+ {0x1105c2, 0x0},
+ {0x2105c2, 0x0},
+ {0x0106c2, 0x0},
+ {0x1106c2, 0x0},
+ {0x2106c2, 0x0},
+ {0x0107c2, 0x0},
+ {0x1107c2, 0x0},
+ {0x2107c2, 0x0},
+ {0x0108c2, 0x0},
+ {0x1108c2, 0x0},
+ {0x2108c2, 0x0},
+ {0x0100c3, 0x0},
+ {0x1100c3, 0x0},
+ {0x2100c3, 0x0},
+ {0x0101c3, 0x0},
+ {0x1101c3, 0x0},
+ {0x2101c3, 0x0},
+ {0x0102c3, 0x0},
+ {0x1102c3, 0x0},
+ {0x2102c3, 0x0},
+ {0x0103c3, 0x0},
+ {0x1103c3, 0x0},
+ {0x2103c3, 0x0},
+ {0x0104c3, 0x0},
+ {0x1104c3, 0x0},
+ {0x2104c3, 0x0},
+ {0x0105c3, 0x0},
+ {0x1105c3, 0x0},
+ {0x2105c3, 0x0},
+ {0x0106c3, 0x0},
+ {0x1106c3, 0x0},
+ {0x2106c3, 0x0},
+ {0x0107c3, 0x0},
+ {0x1107c3, 0x0},
+ {0x2107c3, 0x0},
+ {0x0108c3, 0x0},
+ {0x1108c3, 0x0},
+ {0x2108c3, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x0110c2, 0x0},
+ {0x1110c2, 0x0},
+ {0x2110c2, 0x0},
+ {0x0111c2, 0x0},
+ {0x1111c2, 0x0},
+ {0x2111c2, 0x0},
+ {0x0112c2, 0x0},
+ {0x1112c2, 0x0},
+ {0x2112c2, 0x0},
+ {0x0113c2, 0x0},
+ {0x1113c2, 0x0},
+ {0x2113c2, 0x0},
+ {0x0114c2, 0x0},
+ {0x1114c2, 0x0},
+ {0x2114c2, 0x0},
+ {0x0115c2, 0x0},
+ {0x1115c2, 0x0},
+ {0x2115c2, 0x0},
+ {0x0116c2, 0x0},
+ {0x1116c2, 0x0},
+ {0x2116c2, 0x0},
+ {0x0117c2, 0x0},
+ {0x1117c2, 0x0},
+ {0x2117c2, 0x0},
+ {0x0118c2, 0x0},
+ {0x1118c2, 0x0},
+ {0x2118c2, 0x0},
+ {0x0110c3, 0x0},
+ {0x1110c3, 0x0},
+ {0x2110c3, 0x0},
+ {0x0111c3, 0x0},
+ {0x1111c3, 0x0},
+ {0x2111c3, 0x0},
+ {0x0112c3, 0x0},
+ {0x1112c3, 0x0},
+ {0x2112c3, 0x0},
+ {0x0113c3, 0x0},
+ {0x1113c3, 0x0},
+ {0x2113c3, 0x0},
+ {0x0114c3, 0x0},
+ {0x1114c3, 0x0},
+ {0x2114c3, 0x0},
+ {0x0115c3, 0x0},
+ {0x1115c3, 0x0},
+ {0x2115c3, 0x0},
+ {0x0116c3, 0x0},
+ {0x1116c3, 0x0},
+ {0x2116c3, 0x0},
+ {0x0117c3, 0x0},
+ {0x1117c3, 0x0},
+ {0x2117c3, 0x0},
+ {0x0118c3, 0x0},
+ {0x1118c3, 0x0},
+ {0x2118c3, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00020060, 0x00000002},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000000},
+ {0x00054003, 0x00000960},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x0000025e},
+ {0x00054007, 0x00001000},
+ {0x00054008, 0x00000101},
+ {0x00054009, 0x00000000},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x0000031f},
+ {0x0005400c, 0x000000c8},
+ {0x0005400d, 0x00000100},
+ {0x0005400e, 0x00000000},
+ {0x0005400f, 0x00000000},
+ {0x00054010, 0x00000000},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000001},
+ {0x0005402f, 0x00000834},
+ {0x00054030, 0x00000105},
+ {0x00054031, 0x00000018},
+ {0x00054032, 0x00000200},
+ {0x00054033, 0x00000200},
+ {0x00054034, 0x00000740},
+ {0x00054035, 0x00000850},
+ {0x00054036, 0x00000103},
+ {0x00054037, 0x00000000},
+ {0x00054038, 0x00000000},
+ {0x00054039, 0x00000000},
+ {0x0005403a, 0x00000000},
+ {0x0005403b, 0x00000000},
+ {0x0005403c, 0x00000000},
+ {0x0005403d, 0x00000000},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00001221},
+ {0x000541fc, 0x00000100},
+ {0x000d0000, 0x00000001},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000101},
+ {0x00054003, 0x00000190},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x0000025e},
+ {0x00054007, 0x00001000},
+ {0x00054008, 0x00000101},
+ {0x00054009, 0x00000000},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x0000021f},
+ {0x0005400c, 0x000000c8},
+ {0x0005400d, 0x00000100},
+ {0x0005400e, 0x00000000},
+ {0x0005400f, 0x00000000},
+ {0x00054010, 0x00000000},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000001},
+ {0x0005402f, 0x00000000},
+ {0x00054030, 0x00000105},
+ {0x00054031, 0x00000000},
+ {0x00054032, 0x00000000},
+ {0x00054033, 0x00000200},
+ {0x00054034, 0x00000740},
+ {0x00054035, 0x00000050},
+ {0x00054036, 0x00000103},
+ {0x00054037, 0x00000000},
+ {0x00054038, 0x00000000},
+ {0x00054039, 0x00000000},
+ {0x0005403a, 0x00000000},
+ {0x0005403b, 0x00000000},
+ {0x0005403c, 0x00000000},
+ {0x0005403d, 0x00000000},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00001221},
+ {0x000541fc, 0x00000100},
+ {0x000d0000, 0x00000001},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000102},
+ {0x00054003, 0x00000064},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x0000025e},
+ {0x00054007, 0x00001000},
+ {0x00054008, 0x00000101},
+ {0x00054009, 0x00000000},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x0000021f},
+ {0x0005400c, 0x000000c8},
+ {0x0005400d, 0x00000100},
+ {0x0005400e, 0x00000000},
+ {0x0005400f, 0x00000000},
+ {0x00054010, 0x00000000},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000001},
+ {0x0005402f, 0x00000000},
+ {0x00054030, 0x00000105},
+ {0x00054031, 0x00000000},
+ {0x00054032, 0x00000000},
+ {0x00054033, 0x00000200},
+ {0x00054034, 0x00000740},
+ {0x00054035, 0x00000050},
+ {0x00054036, 0x00000103},
+ {0x00054037, 0x00000000},
+ {0x00054038, 0x00000000},
+ {0x00054039, 0x00000000},
+ {0x0005403a, 0x00000000},
+ {0x0005403b, 0x00000000},
+ {0x0005403c, 0x00000000},
+ {0x0005403d, 0x00000000},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00001221},
+ {0x000541fc, 0x00000100},
+ {0x000d0000, 0x00000001},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000000},
+ {0x00054003, 0x00000960},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x0000025e},
+ {0x00054007, 0x00001000},
+ {0x00054008, 0x00000101},
+ {0x00054009, 0x00000000},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x00000061},
+ {0x0005400c, 0x000000c8},
+ {0x0005400d, 0x00000100},
+ {0x0005400e, 0x00001f7f},
+ {0x0005400f, 0x00000000},
+ {0x00054010, 0x00000000},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000001},
+ {0x0005402f, 0x00000834},
+ {0x00054030, 0x00000105},
+ {0x00054031, 0x00000018},
+ {0x00054032, 0x00000200},
+ {0x00054033, 0x00000200},
+ {0x00054034, 0x00000740},
+ {0x00054035, 0x00000850},
+ {0x00054036, 0x00000103},
+ {0x00054037, 0x00000000},
+ {0x00054038, 0x00000000},
+ {0x00054039, 0x00000000},
+ {0x0005403a, 0x00000000},
+ {0x0005403b, 0x00000000},
+ {0x0005403c, 0x00000000},
+ {0x0005403d, 0x00000000},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00001221},
+ {0x000541fc, 0x00000100},
+ {0x000d0000, 0x00000001},
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x2},
+ {0x90033, 0x10},
+ {0x90034, 0x139},
+ {0x90035, 0xb},
+ {0x90036, 0x7c0},
+ {0x90037, 0x139},
+ {0x90038, 0x44},
+ {0x90039, 0x633},
+ {0x9003a, 0x159},
+ {0x9003b, 0x14f},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x47},
+ {0x9003f, 0x633},
+ {0x90040, 0x149},
+ {0x90041, 0x4f},
+ {0x90042, 0x633},
+ {0x90043, 0x179},
+ {0x90044, 0x8},
+ {0x90045, 0xe0},
+ {0x90046, 0x109},
+ {0x90047, 0x0},
+ {0x90048, 0x7c8},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x1},
+ {0x9004c, 0x8},
+ {0x9004d, 0x0},
+ {0x9004e, 0x45a},
+ {0x9004f, 0x9},
+ {0x90050, 0x0},
+ {0x90051, 0x448},
+ {0x90052, 0x109},
+ {0x90053, 0x40},
+ {0x90054, 0x633},
+ {0x90055, 0x179},
+ {0x90056, 0x1},
+ {0x90057, 0x618},
+ {0x90058, 0x109},
+ {0x90059, 0x40c0},
+ {0x9005a, 0x633},
+ {0x9005b, 0x149},
+ {0x9005c, 0x8},
+ {0x9005d, 0x4},
+ {0x9005e, 0x48},
+ {0x9005f, 0x4040},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x0},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x40},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x10},
+ {0x90069, 0x4},
+ {0x9006a, 0x18},
+ {0x9006b, 0x0},
+ {0x9006c, 0x4},
+ {0x9006d, 0x78},
+ {0x9006e, 0x549},
+ {0x9006f, 0x633},
+ {0x90070, 0x159},
+ {0x90071, 0xd49},
+ {0x90072, 0x633},
+ {0x90073, 0x159},
+ {0x90074, 0x94a},
+ {0x90075, 0x633},
+ {0x90076, 0x159},
+ {0x90077, 0x441},
+ {0x90078, 0x633},
+ {0x90079, 0x149},
+ {0x9007a, 0x42},
+ {0x9007b, 0x633},
+ {0x9007c, 0x149},
+ {0x9007d, 0x1},
+ {0x9007e, 0x633},
+ {0x9007f, 0x149},
+ {0x90080, 0x0},
+ {0x90081, 0xe0},
+ {0x90082, 0x109},
+ {0x90083, 0xa},
+ {0x90084, 0x10},
+ {0x90085, 0x109},
+ {0x90086, 0x9},
+ {0x90087, 0x3c0},
+ {0x90088, 0x149},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x159},
+ {0x9008c, 0x18},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x0},
+ {0x90090, 0x3c0},
+ {0x90091, 0x109},
+ {0x90092, 0x18},
+ {0x90093, 0x4},
+ {0x90094, 0x48},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x58},
+ {0x90098, 0xb},
+ {0x90099, 0x10},
+ {0x9009a, 0x109},
+ {0x9009b, 0x1},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x5},
+ {0x9009f, 0x7c0},
+ {0x900a0, 0x109},
+ {0x900a1, 0x0},
+ {0x900a2, 0x8140},
+ {0x900a3, 0x10c},
+ {0x900a4, 0x10},
+ {0x900a5, 0x8138},
+ {0x900a6, 0x10c},
+ {0x900a7, 0x8},
+ {0x900a8, 0x7c8},
+ {0x900a9, 0x101},
+ {0x900aa, 0x8},
+ {0x900ab, 0x448},
+ {0x900ac, 0x109},
+ {0x900ad, 0xf},
+ {0x900ae, 0x7c0},
+ {0x900af, 0x109},
+ {0x900b0, 0x47},
+ {0x900b1, 0x630},
+ {0x900b2, 0x109},
+ {0x900b3, 0x8},
+ {0x900b4, 0x618},
+ {0x900b5, 0x109},
+ {0x900b6, 0x8},
+ {0x900b7, 0xe0},
+ {0x900b8, 0x109},
+ {0x900b9, 0x0},
+ {0x900ba, 0x7c8},
+ {0x900bb, 0x109},
+ {0x900bc, 0x8},
+ {0x900bd, 0x8140},
+ {0x900be, 0x10c},
+ {0x900bf, 0x0},
+ {0x900c0, 0x1},
+ {0x900c1, 0x8},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x8},
+ {0x900c5, 0x8},
+ {0x900c6, 0x7c8},
+ {0x900c7, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x90026, 0x2b},
+ {0x2000b, 0x4b},
+ {0x2000c, 0x96},
+ {0x2000d, 0x5dc},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x16},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x3},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0xffff},
+ {0x90013, 0x6152},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 400, 100,},
+};
+
diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c
new file mode 100644
index 0000000..b22a2a6
--- /dev/null
+++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "DDR4 EVK");
+ env_set("board_rev", "iMX8MN");
+#endif
+ return 0;
+}
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
new file mode 100644
index 0000000..cbde9f6
--- /dev/null
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ puts("Normal Boot\n");
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0)
+ printf("Failed to find clock node. Check device tree\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(1);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ puts("resetting ...\n");
+
+ reset_cpu(WDOG1_BASE_ADDR);
+
+ return 0;
+}
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 95ce9f3..cb4006e 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -18,7 +18,6 @@
void spl_board_init(void)
{
struct udevice *dev;
- int offset;
uclass_find_first_device(UCLASS_MISC, &dev);
@@ -27,21 +26,6 @@
continue;
}
- offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
- while (offset != -FDT_ERR_NOTFOUND) {
- lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
- NULL, true);
- offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
- "nxp,imx8-pd");
- }
-
- uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
-
- for (; dev; uclass_find_next_device(&dev)) {
- if (device_probe(dev))
- continue;
- }
-
arch_cpu_init();
board_early_init_f();
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 4cbc62f..9bf5c45 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -35,6 +35,9 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
@@ -62,7 +65,11 @@
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
new file mode 100644
index 0000000..75dad70
--- /dev/null
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_SPL_CLK_IMX8MN=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 8978a5c..6e7d9e6 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -6,7 +6,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
CONFIG_TARGET_IMX8QM_MEK=y
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index aae69cf..0ba8bc9 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -36,3 +36,19 @@
select CLK_CCF
help
This enables support clock driver for i.MX8MM platforms.
+
+config SPL_CLK_IMX8MN
+ bool "SPL clock support for i.MX8MN"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MN
+
+config CLK_IMX8MN
+ bool "Clock support for i.MX8MN"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MX8MN platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 5ad7967..222c5a4 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,3 +12,5 @@
endif
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
+ clk-composite-8m.o
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index f4913e7..091b092 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -80,6 +80,17 @@
static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
"sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+#ifndef CONFIG_SPL_BUILD
+static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
+ "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
+ "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+#endif
+
static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
@@ -164,11 +175,30 @@
return __imx8mm_clk_enable(clk, 1);
}
+static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
static struct clk_ops imx8mm_clk_ops = {
.set_rate = imx8mm_clk_set_rate,
.get_rate = imx8mm_clk_get_rate,
.enable = imx8mm_clk_enable,
.disable = imx8mm_clk_disable,
+ .set_parent = imx8mm_clk_set_parent,
};
static int imx8mm_clk_probe(struct udevice *dev)
@@ -363,6 +393,22 @@
clk_dm(IMX8MM_CLK_USDHC3_ROOT,
imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+ /* clks not needed in SPL stage */
+#ifndef CONFIG_SPL_BUILD
+ clk_dm(IMX8MM_CLK_ENET_REF,
+ imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
+ base + 0xa980));
+ clk_dm(IMX8MM_CLK_ENET_TIMER,
+ imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
+ base + 0xaa00));
+ clk_dm(IMX8MM_CLK_ENET_PHY_REF,
+ imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
+ base + 0xaa80));
+ clk_dm(IMX8MM_CLK_ENET1_ROOT,
+ imx_clk_gate4("enet1_root_clk", "enet_axi",
+ base + 0x40a0, 0));
+#endif
+
#ifdef CONFIG_SPL_BUILD
struct clk *clkp, *clkp1;
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
new file mode 100644
index 0000000..4048cc6
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imx8mn-clock.h>
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
+ PLL_1416X_RATE(1800000000U, 225, 3, 0),
+ PLL_1416X_RATE(1600000000U, 200, 3, 0),
+ PLL_1416X_RATE(1200000000U, 300, 3, 1),
+ PLL_1416X_RATE(1000000000U, 250, 3, 1),
+ PLL_1416X_RATE(800000000U, 200, 3, 1),
+ PLL_1416X_RATE(750000000U, 250, 2, 2),
+ PLL_1416X_RATE(700000000U, 350, 3, 2),
+ PLL_1416X_RATE(600000000U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
+ PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_drampll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
+static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
+static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+
+static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
+ "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
+ "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
+ "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
+ "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
+
+static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
+ "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
+
+static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
+
+static ulong imx8mn_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imx8mn_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imx8mn_clk_disable(struct clk *clk)
+{
+ return __imx8mn_clk_enable(clk, 0);
+}
+
+static int imx8mn_clk_enable(struct clk *clk)
+{
+ return __imx8mn_clk_enable(clk, 1);
+}
+
+static struct clk_ops imx8mn_clk_ops = {
+ .set_rate = imx8mn_clk_set_rate,
+ .get_rate = imx8mn_clk_get_rate,
+ .enable = imx8mn_clk_enable,
+ .disable = imx8mn_clk_disable,
+};
+
+static int imx8mn_clk_probe(struct udevice *dev)
+{
+ void __iomem *base;
+
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
+ imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MN_ARM_PLL_REF_SEL,
+ imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
+ imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
+ imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
+ imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+
+ clk_dm(IMX8MN_DRAM_PLL,
+ imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
+ base + 0x50, &imx8mn_dram_pll));
+ clk_dm(IMX8MN_ARM_PLL,
+ imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
+ base + 0x84, &imx8mn_arm_pll));
+ clk_dm(IMX8MN_SYS_PLL1,
+ imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
+ base + 0x94, &imx8mn_sys_pll));
+ clk_dm(IMX8MN_SYS_PLL2,
+ imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
+ base + 0x104, &imx8mn_sys_pll));
+ clk_dm(IMX8MN_SYS_PLL3,
+ imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
+ base + 0x114, &imx8mn_sys_pll));
+
+ /* PLL bypass out */
+ clk_dm(IMX8MN_DRAM_PLL_BYPASS,
+ imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+ dram_pll_bypass_sels,
+ ARRAY_SIZE(dram_pll_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MN_ARM_PLL_BYPASS,
+ imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+ arm_pll_bypass_sels,
+ ARRAY_SIZE(arm_pll_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MN_SYS_PLL1_BYPASS,
+ imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+ sys_pll1_bypass_sels,
+ ARRAY_SIZE(sys_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MN_SYS_PLL2_BYPASS,
+ imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+ sys_pll2_bypass_sels,
+ ARRAY_SIZE(sys_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MN_SYS_PLL3_BYPASS,
+ imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+ sys_pll3_bypass_sels,
+ ARRAY_SIZE(sys_pll3_bypass_sels),
+ CLK_SET_RATE_PARENT));
+
+ /* PLL out gate */
+ clk_dm(IMX8MN_DRAM_PLL_OUT,
+ imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+ base + 0x50, 13));
+ clk_dm(IMX8MN_ARM_PLL_OUT,
+ imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+ base + 0x84, 11));
+ clk_dm(IMX8MN_SYS_PLL1_OUT,
+ imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+ base + 0x94, 11));
+ clk_dm(IMX8MN_SYS_PLL2_OUT,
+ imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+ base + 0x104, 11));
+ clk_dm(IMX8MN_SYS_PLL3_OUT,
+ imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+ base + 0x114, 11));
+
+ /* SYS PLL fixed output */
+ clk_dm(IMX8MN_SYS_PLL1_40M,
+ imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+ clk_dm(IMX8MN_SYS_PLL1_80M,
+ imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+ clk_dm(IMX8MN_SYS_PLL1_100M,
+ imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+ clk_dm(IMX8MN_SYS_PLL1_133M,
+ imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+ clk_dm(IMX8MN_SYS_PLL1_160M,
+ imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+ clk_dm(IMX8MN_SYS_PLL1_200M,
+ imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+ clk_dm(IMX8MN_SYS_PLL1_266M,
+ imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+ clk_dm(IMX8MN_SYS_PLL1_400M,
+ imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+ clk_dm(IMX8MN_SYS_PLL1_800M,
+ imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+
+ clk_dm(IMX8MN_SYS_PLL2_50M,
+ imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+ clk_dm(IMX8MN_SYS_PLL2_100M,
+ imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+ clk_dm(IMX8MN_SYS_PLL2_125M,
+ imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+ clk_dm(IMX8MN_SYS_PLL2_166M,
+ imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+ clk_dm(IMX8MN_SYS_PLL2_200M,
+ imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+ clk_dm(IMX8MN_SYS_PLL2_250M,
+ imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+ clk_dm(IMX8MN_SYS_PLL2_333M,
+ imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+ clk_dm(IMX8MN_SYS_PLL2_500M,
+ imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+ clk_dm(IMX8MN_SYS_PLL2_1000M,
+ imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+
+ base = dev_read_addr_ptr(dev);
+ if (base == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(IMX8MN_CLK_A53_SRC,
+ imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+ imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
+ clk_dm(IMX8MN_CLK_A53_CG,
+ imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+ clk_dm(IMX8MN_CLK_A53_DIV,
+ imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+ base + 0x8000, 0, 3));
+
+ clk_dm(IMX8MN_CLK_AHB,
+ imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
+ base + 0x9000));
+ clk_dm(IMX8MN_CLK_IPG_ROOT,
+ imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+
+ clk_dm(IMX8MN_CLK_ENET_AXI,
+ imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
+ base + 0x8880));
+ clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
+ imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8mn_nand_usdhc_sels,
+ base + 0x8900));
+
+ /* IP */
+ clk_dm(IMX8MN_CLK_USDHC1,
+ imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
+ base + 0xac00));
+ clk_dm(IMX8MN_CLK_USDHC2,
+ imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
+ base + 0xac80));
+ clk_dm(IMX8MN_CLK_I2C1,
+ imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
+ clk_dm(IMX8MN_CLK_I2C2,
+ imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
+ clk_dm(IMX8MN_CLK_I2C3,
+ imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
+ clk_dm(IMX8MN_CLK_I2C4,
+ imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MN_CLK_WDOG,
+ imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
+ clk_dm(IMX8MN_CLK_USDHC3,
+ imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
+ base + 0xbc80));
+
+ clk_dm(IMX8MN_CLK_I2C1_ROOT,
+ imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+ clk_dm(IMX8MN_CLK_I2C2_ROOT,
+ imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+ clk_dm(IMX8MN_CLK_I2C3_ROOT,
+ imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+ clk_dm(IMX8MN_CLK_I2C4_ROOT,
+ imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ clk_dm(IMX8MN_CLK_OCOTP_ROOT,
+ imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MN_CLK_USDHC1_ROOT,
+ imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+ clk_dm(IMX8MN_CLK_USDHC2_ROOT,
+ imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+ clk_dm(IMX8MN_CLK_WDOG1_ROOT,
+ imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+ clk_dm(IMX8MN_CLK_WDOG2_ROOT,
+ imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+ clk_dm(IMX8MN_CLK_WDOG3_ROOT,
+ imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+ clk_dm(IMX8MN_CLK_USDHC3_ROOT,
+ imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+
+#ifdef CONFIG_SPL_BUILD
+ struct clk *clkp, *clkp1;
+
+ clk_get_by_id(IMX8MN_CLK_WDOG1_ROOT, &clkp);
+ clk_enable(clkp);
+ clk_get_by_id(IMX8MN_CLK_WDOG2_ROOT, &clkp);
+ clk_enable(clkp);
+ clk_get_by_id(IMX8MN_CLK_WDOG3_ROOT, &clkp);
+ clk_enable(clkp);
+
+ /* Configure SYS_PLL3 to 600MHz */
+ clk_get_by_id(IMX8MN_SYS_PLL3, &clkp);
+ clk_set_rate(clkp, 600000000UL);
+ clk_enable(clkp);
+
+ /* Configure ARM to sys_pll2_500m */
+ clk_get_by_id(IMX8MN_CLK_A53_SRC, &clkp);
+ clk_get_by_id(IMX8MN_SYS_PLL2_OUT, &clkp1);
+ clk_enable(clkp1);
+ clk_get_by_id(IMX8MN_SYS_PLL2_500M, &clkp1);
+ clk_set_parent(clkp, clkp1);
+
+ /* Configure ARM PLL to 1.2GHz */
+ clk_get_by_id(IMX8MN_ARM_PLL, &clkp1);
+ clk_set_rate(clkp1, 1200000000UL);
+ clk_get_by_id(IMX8MN_ARM_PLL_OUT, &clkp1);
+ clk_enable(clkp1);
+ clk_set_parent(clkp, clkp1);
+
+ /* Configure DIV to 1.2GHz */
+ clk_get_by_id(IMX8MN_CLK_A53_DIV, &clkp1);
+ clk_set_rate(clkp1, 1200000000UL);
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id imx8mn_clk_ids[] = {
+ { .compatible = "fsl,imx8mn-ccm" },
+ { },
+};
+
+U_BOOT_DRIVER(imx8mn_clk) = {
+ .name = "clk_imx8mn",
+ .id = UCLASS_CLK,
+ .of_match = imx8mn_clk_ids,
+ .ops = &imx8mn_clk_ops,
+ .probe = imx8mn_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index 9ec0045..a7654a7 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -26,8 +26,6 @@
struct imx8_scu {
struct mu_type *base;
- struct udevice *clk;
- struct udevice *pinclk;
};
#define MU_CR_GIE_MASK 0xF0000000u
@@ -202,9 +200,6 @@
gd->arch.scu_dev = dev;
- device_probe(plat->clk);
- device_probe(plat->pinclk);
-
return 0;
}
@@ -215,44 +210,17 @@
static int imx8_scu_bind(struct udevice *dev)
{
- struct imx8_scu *plat = dev_get_platdata(dev);
int ret;
struct udevice *child;
- int node;
- char *clk_compatible, *iomuxc_compatible;
-
- if (IS_ENABLED(CONFIG_IMX8QXP)) {
- clk_compatible = "fsl,imx8qxp-clk";
- iomuxc_compatible = "fsl,imx8qxp-iomuxc";
- } else if (IS_ENABLED(CONFIG_IMX8QM)) {
- clk_compatible = "fsl,imx8qm-clk";
- iomuxc_compatible = "fsl,imx8qm-iomuxc";
- } else {
- return -EINVAL;
- }
+ ofnode node;
debug("%s(dev=%p)\n", __func__, dev);
-
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, clk_compatible);
- if (node < 0)
- panic("No clk node found\n");
-
- ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child, true);
- if (ret)
- return ret;
-
- plat->clk = child;
-
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- iomuxc_compatible);
- if (node < 0)
- panic("No iomuxc node found\n");
-
- ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child, true);
- if (ret)
- return ret;
-
- plat->pinclk = child;
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ ret = lists_bind_fdt(dev, node, &child, true);
+ if (ret)
+ return ret;
+ debug("bind child dev %s\n", child->name);
+ }
return 0;
}
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index eb3d7ed..4182897 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -236,7 +236,7 @@
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX28 || MX5 || MX6 || MX7 || IMX8 || VF610
+ depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || VF610
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 080dbcf..131d199 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -123,30 +123,38 @@
return val;
}
+#ifndef imx_get_fecclk
+u32 __weak imx_get_fecclk(void)
+{
+ return 0;
+}
+#endif
+
static int fec_get_clk_rate(void *udev, int idx)
{
-#if IS_ENABLED(CONFIG_IMX8)
struct fec_priv *fec;
struct udevice *dev;
int ret;
- dev = udev;
- if (!dev) {
- ret = uclass_get_device(UCLASS_ETH, idx, &dev);
- if (ret < 0) {
- debug("Can't get FEC udev: %d\n", ret);
- return ret;
+ if (IS_ENABLED(CONFIG_IMX8) ||
+ CONFIG_IS_ENABLED(CLK_CCF)) {
+ dev = udev;
+ if (!dev) {
+ ret = uclass_get_device(UCLASS_ETH, idx, &dev);
+ if (ret < 0) {
+ debug("Can't get FEC udev: %d\n", ret);
+ return ret;
+ }
}
+
+ fec = dev_get_priv(dev);
+ if (fec)
+ return fec->clk_rate;
+
+ return -EINVAL;
+ } else {
+ return imx_get_fecclk();
}
-
- fec = dev_get_priv(dev);
- if (fec)
- return fec->clk_rate;
-
- return -EINVAL;
-#else
- return imx_get_fecclk();
-#endif
}
static void fec_mii_setspeed(struct ethernet_regs *eth)
@@ -1336,6 +1344,47 @@
}
priv->clk_rate = clk_get_rate(&priv->ipg_clk);
+ } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+ if (ret < 0) {
+ debug("Can't get FEC ipg clk: %d\n", ret);
+ return ret;
+ }
+ ret = clk_enable(&priv->ipg_clk);
+ if(ret)
+ return ret;
+
+ ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
+ if (ret < 0) {
+ debug("Can't get FEC ahb clk: %d\n", ret);
+ return ret;
+ }
+ ret = clk_enable(&priv->ahb_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
+ if (!ret) {
+ ret = clk_enable(&priv->clk_enet_out);
+ if (ret)
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
+ if (!ret) {
+ ret = clk_enable(&priv->clk_ref);
+ if (ret)
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
+ if (!ret) {
+ ret = clk_enable(&priv->clk_ptp);
+ if (ret)
+ return ret;
+ }
+
+ priv->clk_rate = clk_get_rate(&priv->ipg_clk);
}
ret = fec_alloc_descs(priv);
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index e5f2dd7..723b06a 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -264,6 +264,10 @@
u32 interface;
#endif
struct clk ipg_clk;
+ struct clk ahb_clk;
+ struct clk clk_enet_out;
+ struct clk clk_ref;
+ struct clk clk_ptp;
u32 clk_rate;
};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
index 8bb03b7..b384431 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8m.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -21,6 +21,7 @@
static const struct udevice_id imx8m_pinctrl_match[] = {
{ .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
{ .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+ { .compatible = "fsl,imx8mn-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
{ /* sentinel */ }
};
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index d0dce14..45bf9f6 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -5,7 +5,7 @@
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
-obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o
+obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o
obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c
new file mode 100644
index 0000000..d51dbaa
--- /dev/null
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power-domain-uclass.h>
+#include <asm/io.h>
+#include <asm/arch/power-domain.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+#include <asm/arch/sci/sci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct imx8_power_domain_priv {
+ bool state_on;
+};
+
+static int imx8_power_domain_request(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ return 0;
+}
+
+static int imx8_power_domain_free(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ return 0;
+}
+
+static int imx8_power_domain_on(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_priv *ppriv;
+ sc_err_t ret;
+ int err;
+
+ struct power_domain parent_domain;
+ struct udevice *parent = dev_get_parent(dev);
+
+ /* Need to power on parent node first */
+ if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
+ parent_domain.dev = parent;
+ err = imx8_power_domain_on(&parent_domain);
+ if (err)
+ return err;
+ }
+
+ pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev);
+ ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev);
+
+ debug("%s(power_domain=%s) resource_id %d\n", __func__, dev->name,
+ pdata->resource_id);
+
+ /* Already powered on */
+ if (ppriv->state_on)
+ return 0;
+
+ if (pdata->resource_id != SC_R_LAST) {
+ ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
+ SC_PM_PW_MODE_ON);
+ if (ret) {
+ printf("Error: %s Power up failed! (error = %d)\n",
+ dev->name, ret);
+ return -EIO;
+ }
+ }
+
+ ppriv->state_on = true;
+ debug("%s is powered on\n", dev->name);
+
+ return 0;
+}
+
+static int imx8_power_domain_off_node(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct udevice *child;
+ struct imx8_power_domain_priv *ppriv;
+ struct imx8_power_domain_priv *child_ppriv;
+ struct imx8_power_domain_platdata *pdata;
+ sc_err_t ret;
+
+ ppriv = dev_get_priv(dev);
+ pdata = dev_get_platdata(dev);
+
+ debug("%s, %s, state_on %d\n", __func__, dev->name, ppriv->state_on);
+
+ /* Already powered off */
+ if (!ppriv->state_on)
+ return 0;
+
+ /* Check if all subnodes are off */
+ for (device_find_first_child(dev, &child);
+ child;
+ device_find_next_child(&child)) {
+ if (device_active(child)) {
+ child_ppriv =
+ (struct imx8_power_domain_priv *)dev_get_priv(child);
+ if (child_ppriv->state_on)
+ return -EPERM;
+ }
+ }
+
+ if (pdata->resource_id != SC_R_LAST) {
+ if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) {
+ printf("%s not owned by curr partition\n", dev->name);
+ return 0;
+ }
+ ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
+ SC_PM_PW_MODE_OFF);
+ if (ret) {
+ printf("Error: %s Power off failed! (error = %d)\n",
+ dev->name, ret);
+ return -EIO;
+ }
+ }
+
+ ppriv->state_on = false;
+ debug("%s is powered off\n", dev->name);
+
+ return 0;
+}
+
+static int imx8_power_domain_off_parentnodes(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct udevice *parent = dev_get_parent(dev);
+ struct udevice *child;
+ struct imx8_power_domain_priv *ppriv;
+ struct imx8_power_domain_priv *child_ppriv;
+ struct imx8_power_domain_platdata *pdata;
+ sc_err_t ret;
+ struct power_domain parent_pd;
+
+ if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
+ pdata =
+ (struct imx8_power_domain_platdata *)dev_get_platdata(parent);
+ ppriv = (struct imx8_power_domain_priv *)dev_get_priv(parent);
+
+ debug("%s, %s, state_on %d\n", __func__, parent->name,
+ ppriv->state_on);
+
+ /* Already powered off */
+ if (!ppriv->state_on)
+ return 0;
+
+ /*
+ * Check if all sibling nodes are off. If yes,
+ * power off parent
+ */
+ for (device_find_first_child(parent, &child); child;
+ device_find_next_child(&child)) {
+ if (device_active(child)) {
+ child_ppriv = (struct imx8_power_domain_priv *)
+ dev_get_priv(child);
+ /* Find a power on sibling */
+ if (child_ppriv->state_on) {
+ debug("sibling %s, state_on %d\n",
+ child->name,
+ child_ppriv->state_on);
+ return 0;
+ }
+ }
+ }
+
+ /* power off parent */
+ if (pdata->resource_id != SC_R_LAST) {
+ ret = sc_pm_set_resource_power_mode(-1,
+ pdata->resource_id,
+ SC_PM_PW_MODE_OFF);
+ if (ret) {
+ printf("%s Power off failed! (error = %d)\n",
+ parent->name, ret);
+ return -EIO;
+ }
+ }
+
+ ppriv->state_on = false;
+ debug("%s is powered off\n", parent->name);
+
+ parent_pd.dev = parent;
+ imx8_power_domain_off_parentnodes(&parent_pd);
+ }
+
+ return 0;
+}
+
+static int imx8_power_domain_off(struct power_domain *power_domain)
+{
+ int ret;
+
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ /* Turn off the node */
+ ret = imx8_power_domain_off_node(power_domain);
+ if (ret) {
+ debug("Can't power off the node of dev %s, ret = %d\n",
+ power_domain->dev->name, ret);
+ return ret;
+ }
+
+ /* Turn off parent nodes, if sibling nodes are all off */
+ ret = imx8_power_domain_off_parentnodes(power_domain);
+ if (ret) {
+ printf("Failed to power off parent nodes of dev %s, ret = %d\n",
+ power_domain->dev->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int imx8_power_domain_of_xlate(struct power_domain *power_domain,
+ struct ofnode_phandle_args *args)
+{
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ /* Do nothing to the xlate, since we don't have args used */
+
+ return 0;
+}
+
+static int imx8_power_domain_bind(struct udevice *dev)
+{
+ int offset;
+ const char *name;
+ int ret = 0;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ offset = dev_of_offset(dev);
+ for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0;
+ offset = fdt_next_subnode(gd->fdt_blob, offset)) {
+ /* Bind the subnode to this driver */
+ name = fdt_get_name(gd->fdt_blob, offset, NULL);
+
+ ret = device_bind_with_driver_data(dev, dev->driver, name,
+ dev->driver_data,
+ offset_to_ofnode(offset),
+ NULL);
+
+ if (ret == -ENODEV)
+ printf("Driver '%s' refuses to bind\n",
+ dev->driver->name);
+
+ if (ret)
+ printf("Error binding driver '%s': %d\n",
+ dev->driver->name, ret);
+ }
+
+ return 0;
+}
+
+static int imx8_power_domain_probe(struct udevice *dev)
+{
+ struct imx8_power_domain_priv *ppriv;
+
+ debug("%s(dev=%s)\n", __func__, dev->name);
+
+ ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev);
+
+ /* Set default to power off */
+ if (ppriv)
+ ppriv->state_on = false;
+
+ return 0;
+}
+
+static int imx8_power_domain_ofdata_to_platdata(struct udevice *dev)
+{
+ int reg;
+ struct imx8_power_domain_platdata *pdata = dev_get_platdata(dev);
+
+ reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
+ if (reg == -1) {
+ debug("%s: Invalid resource id %d\n", __func__, reg);
+ return -EINVAL;
+ }
+ pdata->resource_id = (sc_rsrc_t)reg;
+
+ debug("%s resource_id %d\n", __func__, pdata->resource_id);
+
+ return 0;
+}
+
+static const struct udevice_id imx8_power_domain_ids[] = {
+ { .compatible = "nxp,imx8-pd" },
+ { }
+};
+
+struct power_domain_ops imx8_power_domain_ops = {
+ .request = imx8_power_domain_request,
+ .free = imx8_power_domain_free,
+ .on = imx8_power_domain_on,
+ .off = imx8_power_domain_off,
+ .of_xlate = imx8_power_domain_of_xlate,
+};
+
+U_BOOT_DRIVER(imx8_power_domain) = {
+ .name = "imx8_power_domain",
+ .id = UCLASS_POWER_DOMAIN,
+ .of_match = imx8_power_domain_ids,
+ .bind = imx8_power_domain_bind,
+ .probe = imx8_power_domain_probe,
+ .ofdata_to_platdata = imx8_power_domain_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct imx8_power_domain_platdata),
+ .priv_auto_alloc_size = sizeof(struct imx8_power_domain_priv),
+ .ops = &imx8_power_domain_ops,
+};
diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c
index d51dbaa..aa76836 100644
--- a/drivers/power/domain/imx8-power-domain.c
+++ b/drivers/power/domain/imx8-power-domain.c
@@ -1,23 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2017 NXP
+ * Copyright 2019 NXP
*/
+#define DEBUG
#include <common.h>
#include <dm.h>
#include <power-domain-uclass.h>
-#include <asm/io.h>
#include <asm/arch/power-domain.h>
-#include <dm/device-internal.h>
-#include <dm/device.h>
#include <asm/arch/sci/sci.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-struct imx8_power_domain_priv {
- bool state_on;
-};
-
static int imx8_power_domain_request(struct power_domain *power_domain)
{
debug("%s(power_domain=%p)\n", __func__, power_domain);
@@ -34,158 +26,16 @@
static int imx8_power_domain_on(struct power_domain *power_domain)
{
- struct udevice *dev = power_domain->dev;
- struct imx8_power_domain_platdata *pdata;
- struct imx8_power_domain_priv *ppriv;
- sc_err_t ret;
- int err;
+ u32 resource_id = power_domain->id;
+ int ret;
- struct power_domain parent_domain;
- struct udevice *parent = dev_get_parent(dev);
+ debug("%s: resource_id %u\n", __func__, resource_id);
- /* Need to power on parent node first */
- if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
- parent_domain.dev = parent;
- err = imx8_power_domain_on(&parent_domain);
- if (err)
- return err;
- }
-
- pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev);
- ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev);
-
- debug("%s(power_domain=%s) resource_id %d\n", __func__, dev->name,
- pdata->resource_id);
-
- /* Already powered on */
- if (ppriv->state_on)
- return 0;
-
- if (pdata->resource_id != SC_R_LAST) {
- ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
- SC_PM_PW_MODE_ON);
- if (ret) {
- printf("Error: %s Power up failed! (error = %d)\n",
- dev->name, ret);
- return -EIO;
- }
- }
-
- ppriv->state_on = true;
- debug("%s is powered on\n", dev->name);
-
- return 0;
-}
-
-static int imx8_power_domain_off_node(struct power_domain *power_domain)
-{
- struct udevice *dev = power_domain->dev;
- struct udevice *child;
- struct imx8_power_domain_priv *ppriv;
- struct imx8_power_domain_priv *child_ppriv;
- struct imx8_power_domain_platdata *pdata;
- sc_err_t ret;
-
- ppriv = dev_get_priv(dev);
- pdata = dev_get_platdata(dev);
-
- debug("%s, %s, state_on %d\n", __func__, dev->name, ppriv->state_on);
-
- /* Already powered off */
- if (!ppriv->state_on)
- return 0;
-
- /* Check if all subnodes are off */
- for (device_find_first_child(dev, &child);
- child;
- device_find_next_child(&child)) {
- if (device_active(child)) {
- child_ppriv =
- (struct imx8_power_domain_priv *)dev_get_priv(child);
- if (child_ppriv->state_on)
- return -EPERM;
- }
- }
-
- if (pdata->resource_id != SC_R_LAST) {
- if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) {
- printf("%s not owned by curr partition\n", dev->name);
- return 0;
- }
- ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
- SC_PM_PW_MODE_OFF);
- if (ret) {
- printf("Error: %s Power off failed! (error = %d)\n",
- dev->name, ret);
- return -EIO;
- }
- }
-
- ppriv->state_on = false;
- debug("%s is powered off\n", dev->name);
-
- return 0;
-}
-
-static int imx8_power_domain_off_parentnodes(struct power_domain *power_domain)
-{
- struct udevice *dev = power_domain->dev;
- struct udevice *parent = dev_get_parent(dev);
- struct udevice *child;
- struct imx8_power_domain_priv *ppriv;
- struct imx8_power_domain_priv *child_ppriv;
- struct imx8_power_domain_platdata *pdata;
- sc_err_t ret;
- struct power_domain parent_pd;
-
- if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
- pdata =
- (struct imx8_power_domain_platdata *)dev_get_platdata(parent);
- ppriv = (struct imx8_power_domain_priv *)dev_get_priv(parent);
-
- debug("%s, %s, state_on %d\n", __func__, parent->name,
- ppriv->state_on);
-
- /* Already powered off */
- if (!ppriv->state_on)
- return 0;
-
- /*
- * Check if all sibling nodes are off. If yes,
- * power off parent
- */
- for (device_find_first_child(parent, &child); child;
- device_find_next_child(&child)) {
- if (device_active(child)) {
- child_ppriv = (struct imx8_power_domain_priv *)
- dev_get_priv(child);
- /* Find a power on sibling */
- if (child_ppriv->state_on) {
- debug("sibling %s, state_on %d\n",
- child->name,
- child_ppriv->state_on);
- return 0;
- }
- }
- }
-
- /* power off parent */
- if (pdata->resource_id != SC_R_LAST) {
- ret = sc_pm_set_resource_power_mode(-1,
- pdata->resource_id,
- SC_PM_PW_MODE_OFF);
- if (ret) {
- printf("%s Power off failed! (error = %d)\n",
- parent->name, ret);
- return -EIO;
- }
- }
-
- ppriv->state_on = false;
- debug("%s is powered off\n", parent->name);
-
- parent_pd.dev = parent;
- imx8_power_domain_off_parentnodes(&parent_pd);
+ ret = sc_pm_set_resource_power_mode(-1, resource_id, SC_PM_PW_MODE_ON);
+ if (ret) {
+ printf("Error: %u Power up failed! (error = %d)\n",
+ resource_id, ret);
+ return ret;
}
return 0;
@@ -193,123 +43,45 @@
static int imx8_power_domain_off(struct power_domain *power_domain)
{
+ u32 resource_id = power_domain->id;
int ret;
- debug("%s(power_domain=%p)\n", __func__, power_domain);
+ debug("%s: resource_id %u\n", __func__, resource_id);
- /* Turn off the node */
- ret = imx8_power_domain_off_node(power_domain);
+ ret = sc_pm_set_resource_power_mode(-1, resource_id, SC_PM_PW_MODE_OFF);
if (ret) {
- debug("Can't power off the node of dev %s, ret = %d\n",
- power_domain->dev->name, ret);
+ printf("Error: %u Power off failed! (error = %d)\n",
+ resource_id, ret);
return ret;
}
- /* Turn off parent nodes, if sibling nodes are all off */
- ret = imx8_power_domain_off_parentnodes(power_domain);
- if (ret) {
- printf("Failed to power off parent nodes of dev %s, ret = %d\n",
- power_domain->dev->name, ret);
- return ret;
- }
-
- return 0;
-}
-
-static int imx8_power_domain_of_xlate(struct power_domain *power_domain,
- struct ofnode_phandle_args *args)
-{
- debug("%s(power_domain=%p)\n", __func__, power_domain);
-
- /* Do nothing to the xlate, since we don't have args used */
-
- return 0;
-}
-
-static int imx8_power_domain_bind(struct udevice *dev)
-{
- int offset;
- const char *name;
- int ret = 0;
-
- debug("%s(dev=%p)\n", __func__, dev);
-
- offset = dev_of_offset(dev);
- for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0;
- offset = fdt_next_subnode(gd->fdt_blob, offset)) {
- /* Bind the subnode to this driver */
- name = fdt_get_name(gd->fdt_blob, offset, NULL);
-
- ret = device_bind_with_driver_data(dev, dev->driver, name,
- dev->driver_data,
- offset_to_ofnode(offset),
- NULL);
-
- if (ret == -ENODEV)
- printf("Driver '%s' refuses to bind\n",
- dev->driver->name);
-
- if (ret)
- printf("Error binding driver '%s': %d\n",
- dev->driver->name, ret);
- }
-
return 0;
}
static int imx8_power_domain_probe(struct udevice *dev)
{
- struct imx8_power_domain_priv *ppriv;
-
debug("%s(dev=%s)\n", __func__, dev->name);
- ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev);
-
- /* Set default to power off */
- if (ppriv)
- ppriv->state_on = false;
-
- return 0;
-}
-
-static int imx8_power_domain_ofdata_to_platdata(struct udevice *dev)
-{
- int reg;
- struct imx8_power_domain_platdata *pdata = dev_get_platdata(dev);
-
- reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
- if (reg == -1) {
- debug("%s: Invalid resource id %d\n", __func__, reg);
- return -EINVAL;
- }
- pdata->resource_id = (sc_rsrc_t)reg;
-
- debug("%s resource_id %d\n", __func__, pdata->resource_id);
-
return 0;
}
static const struct udevice_id imx8_power_domain_ids[] = {
- { .compatible = "nxp,imx8-pd" },
+ { .compatible = "fsl,imx8qxp-scu-pd" },
+ { .compatible = "fsl,scu-pd" },
{ }
};
-struct power_domain_ops imx8_power_domain_ops = {
+struct power_domain_ops imx8_power_domain_ops_v2 = {
.request = imx8_power_domain_request,
.free = imx8_power_domain_free,
.on = imx8_power_domain_on,
.off = imx8_power_domain_off,
- .of_xlate = imx8_power_domain_of_xlate,
};
-U_BOOT_DRIVER(imx8_power_domain) = {
- .name = "imx8_power_domain",
+U_BOOT_DRIVER(imx8_power_domain_v2) = {
+ .name = "imx8_power_domain_v2",
.id = UCLASS_POWER_DOMAIN,
.of_match = imx8_power_domain_ids,
- .bind = imx8_power_domain_bind,
.probe = imx8_power_domain_probe,
- .ofdata_to_platdata = imx8_power_domain_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct imx8_power_domain_platdata),
- .priv_auto_alloc_size = sizeof(struct imx8_power_domain_priv),
- .ops = &imx8_power_domain_ops,
+ .ops = &imx8_power_domain_ops_v2,
};
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index a9d99ec..e0c5f5a 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -150,4 +150,12 @@
#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE 0x30BE0000
+
#endif
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
new file mode 100644
index 0000000..8d4a88b
--- /dev/null
+++ b/include/configs/imx8mn_evk.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8MN_EVK_H
+#define __IMX8MN_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE SZ_8K
+#endif
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x95fff0
+#define CONFIG_SPL_BSS_START_ADDR 0x00950000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x00940000
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image.itb\0" \
+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fit=try\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "fi;"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
+#endif
+#define CONFIG_ENV_SIZE SZ_4K
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#endif
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
new file mode 100644
index 0000000..5255b1c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
+#define __DT_BINDINGS_CLOCK_IMX8MN_H
+
+#define IMX8MN_CLK_DUMMY 0
+#define IMX8MN_CLK_32K 1
+#define IMX8MN_CLK_24M 2
+#define IMX8MN_OSC_HDMI_CLK 3
+#define IMX8MN_CLK_EXT1 4
+#define IMX8MN_CLK_EXT2 5
+#define IMX8MN_CLK_EXT3 6
+#define IMX8MN_CLK_EXT4 7
+#define IMX8MN_AUDIO_PLL1_REF_SEL 8
+#define IMX8MN_AUDIO_PLL2_REF_SEL 9
+#define IMX8MN_VIDEO_PLL1_REF_SEL 10
+#define IMX8MN_DRAM_PLL_REF_SEL 11
+#define IMX8MN_GPU_PLL_REF_SEL 12
+#define IMX8MN_VPU_PLL_REF_SEL 13
+#define IMX8MN_ARM_PLL_REF_SEL 14
+#define IMX8MN_SYS_PLL1_REF_SEL 15
+#define IMX8MN_SYS_PLL2_REF_SEL 16
+#define IMX8MN_SYS_PLL3_REF_SEL 17
+#define IMX8MN_AUDIO_PLL1 18
+#define IMX8MN_AUDIO_PLL2 19
+#define IMX8MN_VIDEO_PLL1 20
+#define IMX8MN_DRAM_PLL 21
+#define IMX8MN_GPU_PLL 22
+#define IMX8MN_VPU_PLL 23
+#define IMX8MN_ARM_PLL 24
+#define IMX8MN_SYS_PLL1 25
+#define IMX8MN_SYS_PLL2 26
+#define IMX8MN_SYS_PLL3 27
+#define IMX8MN_AUDIO_PLL1_BYPASS 28
+#define IMX8MN_AUDIO_PLL2_BYPASS 29
+#define IMX8MN_VIDEO_PLL1_BYPASS 30
+#define IMX8MN_DRAM_PLL_BYPASS 31
+#define IMX8MN_GPU_PLL_BYPASS 32
+#define IMX8MN_VPU_PLL_BYPASS 33
+#define IMX8MN_ARM_PLL_BYPASS 34
+#define IMX8MN_SYS_PLL1_BYPASS 35
+#define IMX8MN_SYS_PLL2_BYPASS 36
+#define IMX8MN_SYS_PLL3_BYPASS 37
+#define IMX8MN_AUDIO_PLL1_OUT 38
+#define IMX8MN_AUDIO_PLL2_OUT 39
+#define IMX8MN_VIDEO_PLL1_OUT 40
+#define IMX8MN_DRAM_PLL_OUT 41
+#define IMX8MN_GPU_PLL_OUT 42
+#define IMX8MN_VPU_PLL_OUT 43
+#define IMX8MN_ARM_PLL_OUT 44
+#define IMX8MN_SYS_PLL1_OUT 45
+#define IMX8MN_SYS_PLL2_OUT 46
+#define IMX8MN_SYS_PLL3_OUT 47
+#define IMX8MN_SYS_PLL1_40M 48
+#define IMX8MN_SYS_PLL1_80M 49
+#define IMX8MN_SYS_PLL1_100M 50
+#define IMX8MN_SYS_PLL1_133M 51
+#define IMX8MN_SYS_PLL1_160M 52
+#define IMX8MN_SYS_PLL1_200M 53
+#define IMX8MN_SYS_PLL1_266M 54
+#define IMX8MN_SYS_PLL1_400M 55
+#define IMX8MN_SYS_PLL1_800M 56
+#define IMX8MN_SYS_PLL2_50M 57
+#define IMX8MN_SYS_PLL2_100M 58
+#define IMX8MN_SYS_PLL2_125M 59
+#define IMX8MN_SYS_PLL2_166M 60
+#define IMX8MN_SYS_PLL2_200M 61
+#define IMX8MN_SYS_PLL2_250M 62
+#define IMX8MN_SYS_PLL2_333M 63
+#define IMX8MN_SYS_PLL2_500M 64
+#define IMX8MN_SYS_PLL2_1000M 65
+
+/* CORE CLOCK ROOT */
+#define IMX8MN_CLK_A53_SRC 66
+#define IMX8MN_CLK_GPU_CORE_SRC 67
+#define IMX8MN_CLK_GPU_SHADER_SRC 68
+#define IMX8MN_CLK_A53_CG 69
+#define IMX8MN_CLK_GPU_CORE_CG 70
+#define IMX8MN_CLK_GPU_SHADER_CG 71
+#define IMX8MN_CLK_A53_DIV 72
+#define IMX8MN_CLK_GPU_CORE_DIV 73
+#define IMX8MN_CLK_GPU_SHADER_DIV 74
+
+/* BUS CLOCK ROOT */
+#define IMX8MN_CLK_MAIN_AXI 75
+#define IMX8MN_CLK_ENET_AXI 76
+#define IMX8MN_CLK_NAND_USDHC_BUS 77
+#define IMX8MN_CLK_DISP_AXI 78
+#define IMX8MN_CLK_DISP_APB 79
+#define IMX8MN_CLK_USB_BUS 80
+#define IMX8MN_CLK_GPU_AXI 81
+#define IMX8MN_CLK_GPU_AHB 82
+#define IMX8MN_CLK_NOC 83
+#define IMX8MN_CLK_AHB 84
+#define IMX8MN_CLK_AUDIO_AHB 85
+
+/* IPG CLOCK ROOT */
+#define IMX8MN_CLK_IPG_ROOT 86
+#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
+
+/* IP */
+#define IMX8MN_CLK_DRAM_CORE 88
+#define IMX8MN_CLK_DRAM_ALT 89
+#define IMX8MN_CLK_DRAM_APB 90
+#define IMX8MN_CLK_DRAM_ALT_ROOT 91
+#define IMX8MN_CLK_DISP_PIXEL 92
+#define IMX8MN_CLK_SAI2 93
+#define IMX8MN_CLK_SAI3 94
+#define IMX8MN_CLK_SAI5 95
+#define IMX8MN_CLK_SAI6 96
+#define IMX8MN_CLK_SPDIF1 97
+#define IMX8MN_CLK_ENET_REF 98
+#define IMX8MN_CLK_ENET_TIMER 99
+#define IMX8MN_CLK_ENET_PHY_REF 100
+#define IMX8MN_CLK_NAND 101
+#define IMX8MN_CLK_QSPI 102
+#define IMX8MN_CLK_USDHC1 103
+#define IMX8MN_CLK_USDHC2 104
+#define IMX8MN_CLK_I2C1 105
+#define IMX8MN_CLK_I2C2 106
+#define IMX8MN_CLK_I2C3 107
+#define IMX8MN_CLK_I2C4 118
+#define IMX8MN_CLK_UART1 119
+#define IMX8MN_CLK_UART2 110
+#define IMX8MN_CLK_UART3 111
+#define IMX8MN_CLK_UART4 112
+#define IMX8MN_CLK_USB_CORE_REF 113
+#define IMX8MN_CLK_USB_PHY_REF 114
+#define IMX8MN_CLK_ECSPI1 115
+#define IMX8MN_CLK_ECSPI2 116
+#define IMX8MN_CLK_PWM1 117
+#define IMX8MN_CLK_PWM2 118
+#define IMX8MN_CLK_PWM3 119
+#define IMX8MN_CLK_PWM4 120
+#define IMX8MN_CLK_WDOG 121
+#define IMX8MN_CLK_WRCLK 122
+#define IMX8MN_CLK_CLKO1 123
+#define IMX8MN_CLK_CLKO2 124
+#define IMX8MN_CLK_DSI_CORE 125
+#define IMX8MN_CLK_DSI_PHY_REF 126
+#define IMX8MN_CLK_DSI_DBI 127
+#define IMX8MN_CLK_USDHC3 128
+#define IMX8MN_CLK_CAMERA_PIXEL 129
+#define IMX8MN_CLK_CSI1_PHY_REF 130
+#define IMX8MN_CLK_CSI2_PHY_REF 131
+#define IMX8MN_CLK_CSI2_ESC 132
+#define IMX8MN_CLK_ECSPI3 133
+#define IMX8MN_CLK_PDM 134
+#define IMX8MN_CLK_SAI7 135
+
+#define IMX8MN_CLK_ECSPI1_ROOT 136
+#define IMX8MN_CLK_ECSPI2_ROOT 137
+#define IMX8MN_CLK_ECSPI3_ROOT 138
+#define IMX8MN_CLK_ENET1_ROOT 139
+#define IMX8MN_CLK_GPIO1_ROOT 140
+#define IMX8MN_CLK_GPIO2_ROOT 141
+#define IMX8MN_CLK_GPIO3_ROOT 142
+#define IMX8MN_CLK_GPIO4_ROOT 143
+#define IMX8MN_CLK_GPIO5_ROOT 144
+#define IMX8MN_CLK_I2C1_ROOT 145
+#define IMX8MN_CLK_I2C2_ROOT 146
+#define IMX8MN_CLK_I2C3_ROOT 147
+#define IMX8MN_CLK_I2C4_ROOT 148
+#define IMX8MN_CLK_MU_ROOT 149
+#define IMX8MN_CLK_OCOTP_ROOT 150
+#define IMX8MN_CLK_PWM1_ROOT 151
+#define IMX8MN_CLK_PWM2_ROOT 152
+#define IMX8MN_CLK_PWM3_ROOT 153
+#define IMX8MN_CLK_PWM4_ROOT 154
+#define IMX8MN_CLK_QSPI_ROOT 155
+#define IMX8MN_CLK_NAND_ROOT 156
+#define IMX8MN_CLK_SAI2_ROOT 157
+#define IMX8MN_CLK_SAI2_IPG 158
+#define IMX8MN_CLK_SAI3_ROOT 159
+#define IMX8MN_CLK_SAI3_IPG 160
+#define IMX8MN_CLK_SAI5_ROOT 161
+#define IMX8MN_CLK_SAI5_IPG 162
+#define IMX8MN_CLK_SAI6_ROOT 163
+#define IMX8MN_CLK_SAI6_IPG 164
+#define IMX8MN_CLK_SAI7_ROOT 165
+#define IMX8MN_CLK_SAI7_IPG 166
+#define IMX8MN_CLK_SDMA1_ROOT 167
+#define IMX8MN_CLK_SDMA2_ROOT 168
+#define IMX8MN_CLK_UART1_ROOT 169
+#define IMX8MN_CLK_UART2_ROOT 170
+#define IMX8MN_CLK_UART3_ROOT 171
+#define IMX8MN_CLK_UART4_ROOT 172
+#define IMX8MN_CLK_USB1_CTRL_ROOT 173
+#define IMX8MN_CLK_USDHC1_ROOT 174
+#define IMX8MN_CLK_USDHC2_ROOT 175
+#define IMX8MN_CLK_WDOG1_ROOT 176
+#define IMX8MN_CLK_WDOG2_ROOT 177
+#define IMX8MN_CLK_WDOG3_ROOT 178
+#define IMX8MN_CLK_GPU_BUS_ROOT 179
+#define IMX8MN_CLK_ASRC_ROOT 180
+#define IMX8MN_CLK_GPU3D_ROOT 181
+#define IMX8MN_CLK_PDM_ROOT 182
+#define IMX8MN_CLK_PDM_IPG 183
+#define IMX8MN_CLK_DISP_AXI_ROOT 184
+#define IMX8MN_CLK_DISP_APB_ROOT 185
+#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
+#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
+#define IMX8MN_CLK_USDHC3_ROOT 188
+#define IMX8MN_CLK_SDMA3_ROOT 189
+#define IMX8MN_CLK_TMU_ROOT 190
+#define IMX8MN_CLK_ARM 191
+#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
+#define IMX8MN_CLK_GPU_CORE_ROOT 193
+
+#define IMX8MN_CLK_END 194
+
+#endif
diff --git a/include/imximage.h b/include/imximage.h
index 544babb..ace5cf8 100644
--- a/include/imximage.h
+++ b/include/imximage.h
@@ -79,6 +79,7 @@
CMD_LOADER,
CMD_SECOND_LOADER,
CMD_DDR_FW,
+ CMD_ROM_VERSION,
};
enum imximage_fld_types {
diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh
index 08a6a48..603ba6e 100755
--- a/tools/imx8m_image.sh
+++ b/tools/imx8m_image.sh
@@ -39,6 +39,16 @@
cat spl/u-boot-spl-pad.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin
rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin spl/u-boot-spl-pad.bin
fi
+ if [ -f $srctree/ddr4_imem_1d.bin ]; then
+ objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/ddr4_imem_1d.bin ddr4_imem_1d_pad.bin
+ objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $srctree/ddr4_dmem_1d.bin ddr4_dmem_1d_pad.bin
+ objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/ddr4_imem_2d.bin ddr4_imem_2d_pad.bin
+ cat ddr4_imem_1d_pad.bin ddr4_dmem_1d_pad.bin > ddr4_1d_fw.bin
+ cat ddr4_imem_2d_pad.bin $srctree/ddr4_dmem_2d.bin > ddr4_2d_fw.bin
+ dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync
+ cat spl/u-boot-spl-pad.bin ddr4_1d_fw.bin ddr4_2d_fw.bin > spl/u-boot-spl-ddr.bin
+ rm -f ddr4_1d_fw.bin ddr4_2d_fw.bin ddr4_imem_1d_pad.bin ddr4_dmem_1d_pad.bin ddr4_imem_2d_pad.bin spl/u-boot-spl-pad.bin
+ fi
fi
exit 0
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 6c02337..2b0d946 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -21,6 +21,11 @@
static uint32_t ivt_offset;
static uint32_t using_fit;
+#define ROM_V1 1
+#define ROM_V2 2
+
+static uint32_t rom_version = ROM_V1;
+
#define CSF_SIZE 0x2000
#define HDMI_IVT_ID 0
#define IMAGE_IVT_ID 1
@@ -71,6 +76,7 @@
{CMD_LOADER, "LOADER", "loader image", },
{CMD_SECOND_LOADER, "SECOND_LOADER", "2nd loader image", },
{CMD_DDR_FW, "DDR_FW", "ddr firmware", },
+ {CMD_ROM_VERSION, "ROM_VERSION", "rom version", },
{-1, "", "", },
};
@@ -90,6 +96,9 @@
token);
if (!strncmp(token, "sd", 2))
rom_image_offset = 0x8000;
+
+ if (rom_version == ROM_V2)
+ ivt_offset = 0;
break;
case CMD_LOADER:
ap_img = token;
@@ -103,6 +112,15 @@
case CMD_DDR_FW:
/* Do nothing */
break;
+ case CMD_ROM_VERSION:
+ if (!strncmp(token, "v2", 2)) {
+ rom_version = ROM_V2;
+ ivt_offset = 0;
+ } else if (!strncmp(token, "v1", 2)) {
+ rom_version = ROM_V1;
+ }
+ break;
+
}
}
@@ -491,8 +509,10 @@
* Record the second bootloader relative offset in
* image's IVT reserved1
*/
- imx_header[IMAGE_IVT_ID].fhdr.reserved1 =
- sld_header_off - header_image_off;
+ if (rom_version == ROM_V1) {
+ imx_header[IMAGE_IVT_ID].fhdr.reserved1 =
+ sld_header_off - header_image_off;
+ }
sld_fd = open(sld_img, O_RDONLY | O_BINARY);
if (sld_fd < 0) {
fprintf(stderr, "%s: Can't open: %s\n",