| commit | 6071bcaec1cbbdd2679f9abdd36dfe16114bc315 | [log] [tgz] |
|---|---|---|
| author | Rajeshwari Shinde <rajeshwari.s@samsung.com> | Tue Jul 03 20:02:57 2012 +0000 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sat Sep 01 14:58:23 2012 +0200 |
| tree | 142468c8d25f58f06e357b947298461c28a04dfa | |
| parent | 87f2e079dbbe517003bd2c3910ae2512ab27a6f5 [diff] |
EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>