| commit | 610083e547d19e87b567849b299187d66b643fb9 | [log] [tgz] |
|---|---|---|
| author | Ye Li <ye.li@nxp.com> | Sat Aug 07 16:00:48 2021 +0800 |
| committer | Stefano Babic <sbabic@denx.de> | Mon Aug 09 14:46:51 2021 +0200 |
| tree | 728844aae35918a91503e3395fad1e168bcc6533 | |
| parent | 981f040a9a56ea4085308d4a6cf83561e02ed95f [diff] |
arm: imx8ulp: Enable full L2 cache in SPL SRAM2 is half L2 cache and default to SRAM after system boot. To enable the full l2 cache (512KB), it needs to reset A35 to make the change happen. So re-implement the jump entry function in SPL: 1. configure the core0 reset vector to entry (ATF) 2. enable the L2 full cache 3. reset A35 So when core0 up, it runs into ATF. And we have 512KB L2 cache working. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>