commit 621e579b812dd1a2e6777f7cbf6e55e736505823
author Mike Frysinger <vapier@gentoo.org> Mon Oct 06 03:44:33 2008 -0400
committer Mike Frysinger <vapier@gentoo.org> Thu Oct 23 05:03:50 2008 -0400
tree ac09bc75052ee9f3577ad002edfb91643b51ecd5
parent 06121c4e2d183887dcd7a4ca2dcd395b213ea15b

Blackfin: fix SWRST register definition

The SWRST register is a 16bit, not 32bit, register.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

include/asm-blackfin/mach-bf561/BF561_cdef.h

diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h
index 23e64ca..d8883f3 100644
--- a/include/asm-blackfin/mach-bf561/BF561_cdef.h
+++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h
@@ -241,9 +241,9 @@
 #define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1)
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pSICA_SWRST                    ((uint32_t volatile *)SICA_SWRST)
-#define bfin_read_SICA_SWRST()         bfin_read32(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val)     bfin_write32(SICA_SWRST, val)
+#define pSICA_SWRST                    ((uint16_t volatile *)SICA_SWRST)
+#define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
+#define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
 #define pSICA_SYSCR                    ((uint32_t volatile *)SICA_SYSCR)
 #define bfin_read_SICA_SYSCR()         bfin_read32(SICA_SYSCR)
 #define bfin_write_SICA_SYSCR(val)     bfin_write32(SICA_SYSCR, val)
@@ -292,9 +292,9 @@
 #define pSICA_IAR7                     ((uint32_t volatile *)SICA_IAR7)
 #define bfin_read_SICA_IAR7()          bfin_read32(SICA_IAR7)
 #define bfin_write_SICA_IAR7(val)      bfin_write32(SICA_IAR7, val)
-#define pSICB_SWRST                    ((uint32_t volatile *)SICB_SWRST)
-#define bfin_read_SICB_SWRST()         bfin_read32(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val)     bfin_write32(SICB_SWRST, val)
+#define pSICB_SWRST                    ((uint16_t volatile *)SICB_SWRST)
+#define bfin_read_SICB_SWRST()         bfin_read16(SICB_SWRST)
+#define bfin_write_SICB_SWRST(val)     bfin_write16(SICB_SWRST, val)
 #define pSICB_SYSCR                    ((uint32_t volatile *)SICB_SYSCR)
 #define bfin_read_SICB_SYSCR()         bfin_read32(SICB_SYSCR)
 #define bfin_write_SICB_SYSCR(val)     bfin_write32(SICB_SYSCR, val)