| commit | 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54 | [log] [tgz] |
|---|---|---|
| author | Bin Meng <bmeng.cn@gmail.com> | Tue Jun 15 13:45:57 2021 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Thu Jun 17 09:39:46 2021 +0800 |
| tree | 086819c8f5cbcab23e7932ab7d9aa747d3aed8e1 | |
| parent | 279de759bd2ceb1dad6ff30c7d27c8ff9c5706a3 [diff] |
riscv: andes_plic: Fix riscv_get_ipi() mask
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>