| commit | 3f6f0cd8fd809287838153d355311f1499040758 | [log] [tgz] |
|---|---|---|
| author | Suneel Garapati <sgarapati@marvell.com> | Sat Oct 19 17:48:25 2019 -0700 |
| committer | Stefan Roese <sr@denx.de> | Tue Aug 25 08:01:16 2020 +0200 |
| tree | 4d4dd7e78d49b8bd1d32132f651893fb6e138302 | |
| parent | 04cd0a0fa03968405918fa6f6b695821767fb068 [diff] |
ata: ahci: Add BAR index quirk for Cavium PCI SATA device For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0 instead of BAR5. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>