commit 651a70e8d58281fdc034864ad5a8c905e5541c89
author Patrice Chotard <patrice.chotard@st.com> Thu Feb 08 17:20:47 2018 +0100
committer Tom Rini <trini@konsulko.com> Tue Mar 13 21:45:37 2018 -0400
tree e232ca28e0a82338535efbce219c0b77b560bd9c
parent 526aa92960cfea5d6799b5a6aae89e4e646acc67

clk: clk_stm32f: No more need of 48Mhz from PLL_SAI

Initially, 48Mhz for SDIO clock was generated from SAI pll for
STM32F469 and STM32F746 SoCs, but this solution was not suitable
for STM32F429 SoCs.

A generic solution is to used the PLL_Q output as 48Mhz clock
for all STM32F SOCs family.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

drivers/clk/clk_stm32f.c

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 7d89906..e8f6b47 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -128,7 +128,6 @@
 	struct stm32_rcc_regs *regs = priv->base;
 	struct stm32_pwr_regs *pwr = priv->pwr_regs;
 	struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
-	u32 pllsaicfgr = 0;
 
 	/* Reset RCC configuration */
 	setbits_le32(&regs->cr, RCC_CR_HSION);
@@ -160,20 +159,10 @@
 	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
 			sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
 
-	/* Configure the SAI PLL to get a 48 MHz source */
-	pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
-		     RCC_PLLSAICFGR_PLLSAIP_4;
-	pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
-	writel(pllsaicfgr, &regs->pllsaicfgr);
-
-	/* Enable the main PLL */
-	setbits_le32(&regs->cr, RCC_CR_PLLON);
-	while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
-		;
-
+	/* configure SDMMC clock */
 	if (priv->info.v2) { /*stm32f7 case */
-		/* select PLLSAI as 48MHz clock source */
-		setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
+		/* select PLLQ as 48MHz clock source */
+		clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
 
 		/* select 48MHz as SDMMC1 clock source */
 		clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
@@ -181,16 +170,16 @@
 		/* select 48MHz as SDMMC2 clock source */
 		clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
 	} else  { /* stm32f4 case */
-		/* select PLLSAI as 48MHz clock source */
-		setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
+		/* select PLLQ as 48MHz clock source */
+		clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
 
 		/* select 48MHz as SDMMC1 clock source */
 		clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
 	}
 
-	/* Enable the SAI PLL */
-	setbits_le32(&regs->cr, RCC_CR_PLLSAION);
-	while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
+	/* Enable the main PLL */
+	setbits_le32(&regs->cr, RCC_CR_PLLON);
+	while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 		;
 
 	setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
@@ -218,8 +207,6 @@
 	while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 			RCC_CFGR_SWS_PLL)
 		;
-	/* gate the SAI clock, needed for MMC 1&2 clocks */
-	setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);
 
 #ifdef CONFIG_ETH_DESIGNWARE
 	/* gate the SYSCFG clock, needed to set RMII ethernet interface */