commit 6596270ecb5d74d5f997da0daa728e06d1f47029
author Michal Simek <michal.simek@xilinx.com> Fri Oct 04 15:52:43 2019 +0200
committer Michal Simek <michal.simek@xilinx.com> Thu Oct 24 13:37:01 2019 +0200
tree 21d5b8265b2fa0e02297c0ee8edae46b9362a3cc
parent 866225f394a9b3174d9ea39d2d19ac0d2c07a516

arm64: versal: Rename versal_pm_request to xilinx_pm_request

Use generic name instead of Versal specific because this should be also
used on ZynqMP.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers/fpga/versalpl.c

diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index 8337b83..4bcc213 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -39,7 +39,7 @@
 	buf_lo = lower_32_bits(bin_buf);
 	buf_hi = upper_32_bits(bin_buf);
 
-	ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+	ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
 				buf_hi, 0, ret_payload);
 	if (ret)
 		puts("PL FPGA LOAD fail\n");