Merge git://git.denx.de/u-boot-socfpga
diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
new file mode 100644
index 0000000..2fd8e7a
--- /dev/null
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -0,0 +1,19 @@
+Altera SOCFPGA Arria10 FPGA Manager
+
+Required properties:
+- compatible : should contain "altr,socfpga-a10-fpga-mgr"
+- reg : base address and size for memory mapped io.
+ - The first index is for FPGA manager register access.
+ - The second index is for writing FPGA configuration data.
+- resets : Phandle and reset specifier for the device's reset.
+- clocks : Clocks used by the device.
+
+Example:
+
+ fpga_mgr: fpga-mgr@ffd03000 {
+ compatible = "altr,socfpga-a10-fpga-mgr";
+ reg = <0xffd03000 0x100
+ 0xffcfe400 0x20>;
+ clocks = <&l4_mp_clk>;
+ resets = <&rst FPGAMGR_RESET>;
+ };
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 28fa16b..6e14ebd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -55,18 +55,20 @@
uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
asm volatile(
+ " cmp %2, #0\n"
+ " beq 2f\n"
"1: ldmia %0!, {r0-r7}\n"
" stmia %1!, {r0-r7}\n"
" sub %1, #32\n"
" subs %2, #1\n"
" bne 1b\n"
- " cmp %3, #0\n"
- " beq 3f\n"
- "2: ldr %2, [%0], #4\n"
+ "2: cmp %3, #0\n"
+ " beq 4f\n"
+ "3: ldr %2, [%0], #4\n"
" str %2, [%1]\n"
" subs %3, #1\n"
- " bne 2b\n"
- "3: nop\n"
+ " bne 3b\n"
+ "4: nop\n"
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1ba02be..0fb3e07 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -159,6 +159,8 @@
COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */
+ COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */
+ COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 45f3fe7..c4582ea 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -71,6 +71,8 @@
COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
+ COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
+ COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)