global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 5a15365..9e76a4a 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -18,7 +18,7 @@
#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE
#endif
/*
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index aca7793..c882bd3 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -95,7 +95,7 @@
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
-#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index d96406f..17bd53d 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_HZ_CLOCK
+#ifndef CFG_SYS_HZ_CLOCK
static inline u32 read_cntfrq(void)
{
u32 frq;
@@ -29,8 +29,8 @@
gd->arch.tbl = 0;
gd->arch.tbu = 0;
-#ifdef CONFIG_SYS_HZ_CLOCK
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#ifdef CFG_SYS_HZ_CLOCK
+ gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = read_cntfrq();
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d09c21d..25e4b49 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -313,9 +313,9 @@
int arch_cpu_init(void)
{
- void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
- (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 0e7d5fa..599b7e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -183,7 +183,7 @@
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
- CONFIG_SYS_IFC_ADDR);
+ CFG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 954fa5f..dbb0766 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -42,7 +42,7 @@
static void __secure ls1_fsm_setup(void)
{
- void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -118,7 +118,7 @@
static void __secure ls1_start_fsm(void)
{
- void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
index 67764cc..f7cc457 100644
--- a/arch/arm/cpu/armv7/stv0991/timer.c
+++ b/arch/arm/cpu/armv7/stv0991/timer.c
@@ -18,7 +18,7 @@
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@@ -67,7 +67,7 @@
{
ulong tmo;
ulong start = get_timer_masked();
- ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+ ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c
index 556eaf8..c30af4f 100644
--- a/arch/arm/cpu/armv7m/systick-timer.c
+++ b/arch/arm/cpu/armv7m/systick-timer.c
@@ -18,7 +18,7 @@
* The number of reference clock ticks that correspond to 10ms is normally
* defined in the SysTick Calibration register's TENMS field. However, on some
* devices this is wrong, so this driver allows the clock rate to be defined
- * using CONFIG_SYS_HZ_CLOCK.
+ * using CFG_SYS_HZ_CLOCK.
*/
#include <common.h>
@@ -76,10 +76,10 @@
/*
* If the TENMS field is inexact or wrong, specify the clock rate using
- * CONFIG_SYS_HZ_CLOCK.
+ * CFG_SYS_HZ_CLOCK.
*/
-#if defined(CONFIG_SYS_HZ_CLOCK)
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#if defined(CFG_SYS_HZ_CLOCK)
+ gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bbaa91f..99413ef 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -114,7 +114,7 @@
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
@@ -130,9 +130,9 @@
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#ifdef CONFIG_FSL_IFC
- /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
@@ -391,7 +391,7 @@
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
{}, /* space holder for secure mem */
#endif
{},
@@ -445,7 +445,7 @@
if (el == 3)
gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
- gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
+ gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
@@ -568,7 +568,7 @@
}
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
if (el == 3) {
/*
@@ -580,7 +580,7 @@
gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
final_map[index].virt = gd->arch.secure_ram & ~0x3;
final_map[index].phys = final_map[index].virt;
- final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
+ final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
tlb_addr_save = gd->arch.tlb_addr;
@@ -1323,10 +1323,10 @@
ea_size = gd->ram_size;
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
/* Check if we have enough space for secure memory */
- if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
- ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
+ ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
else
printf("Error: No enough space for secure memory.\n");
#endif
@@ -1433,7 +1433,7 @@
* gd->arch.secure_ram should be done to avoid running it repeatedly.
*/
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
debug("No need to run again, skip %s\n", __func__);
@@ -1442,11 +1442,11 @@
#endif
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
+ CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@@ -1458,17 +1458,17 @@
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->bd->bi_dram[0].size >
- CONFIG_SYS_MEM_RESERVE_SECURE) {
+ CFG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -=
- CONFIG_SYS_MEM_RESERVE_SECURE;
+ CFG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
- gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
}
-#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
+#endif /* CFG_SYS_MEM_RESERVE_SECURE */
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */
@@ -1520,7 +1520,7 @@
}
#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
debug("%s is called. gd->ram_size is reduced to %lu\n",
__func__, (ulong)gd->ram_size);
#endif
@@ -1580,7 +1580,7 @@
} else {
mmu_change_region_attr(
CFG_SYS_SDRAM_BASE,
- CONFIG_SYS_DDR_BLOCK1_SIZE,
+ CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
@@ -1589,10 +1589,10 @@
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
#endif
- if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
+ if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
CONFIG_SYS_DDR_BLOCK2_SIZE) {
mmu_change_region_attr(
- CONFIG_SYS_DDR_BLOCK2_BASE,
+ CFG_SYS_DDR_BLOCK2_BASE,
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1601,7 +1601,7 @@
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK3_BASE,
gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE -
+ CFG_SYS_DDR_BLOCK1_SIZE -
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1611,9 +1611,9 @@
#endif
{
mmu_change_region_attr(
- CONFIG_SYS_DDR_BLOCK2_BASE,
+ CFG_SYS_DDR_BLOCK2_BASE,
gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE,
+ CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 9119d60..6f3fe7c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -116,10 +116,10 @@
Environment Variables
=====================
mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
- the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+ the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value
- CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+ CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
from the location where it is stored(NOR, NAND, SD, SATA, USB)during
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 4880a31..e3c3fc6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -10,7 +10,7 @@
#include <fsl_sec.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index e47d3af..333d7e2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -9,7 +9,7 @@
#include <asm/arch-fsl-layerscape/fsl_portals.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 89a6262..359cbc0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -531,7 +531,7 @@
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
- out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
@@ -643,8 +643,8 @@
out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
| SCFG_RD_QOS1_PFE2_QOS));
- ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
- out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+ ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+ out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 | (unsigned int)DISABLE_PFE_ECC);
}
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 3a4b665..61fced4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -116,7 +116,7 @@
#endif
dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA
-#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifndef CFG_SYS_MEM_RESERVE_SECURE
#error Need secure RAM for PPA
#endif
/*
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 540436b..c0e8726 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -198,7 +198,7 @@
goto out;
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
/*
* The SEC Firmware must be stored in secure memory.
* Append SEC Firmware to secure mmu table.
@@ -211,7 +211,7 @@
sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
gd->arch.tlb_size;
#else
-#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
+#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
#endif
/* Align SEC Firmware base address to 4K */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 0669222..c9c72e3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -20,13 +20,13 @@
* Reserve secure memory
* To be aligned with MMU block size
*/
-#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
+#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
-#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CFG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
@@ -37,8 +37,8 @@
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@@ -96,7 +96,7 @@
#elif defined(CONFIG_ARCH_LS1088A)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CFG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
@@ -122,8 +122,8 @@
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@@ -141,15 +141,15 @@
#endif
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
-#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CFG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@@ -192,8 +192,8 @@
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SEC */
@@ -212,8 +212,8 @@
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 7
#define CFG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@@ -251,15 +251,15 @@
#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SMMU Defintions */
#define SMMU_BASE 0x09000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 9cddb41..d5f63f4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -75,7 +75,7 @@
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
- CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+ CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(compat, streamid) \
SET_SCFG_ICID(compat, streamid, sata_icid,\
@@ -142,7 +142,7 @@
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
- CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+ CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(sata_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 64dc7c8..9794db0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -11,11 +11,11 @@
#include <linux/bitops.h>
#endif
-#define CONFIG_SYS_DCSRBAR 0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CFG_SYS_DCSRBAR 0x20000000
+#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
@@ -30,37 +30,37 @@
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
-#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
+#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
-#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
- CONFIG_SYS_BMAN_MEM_BASE)
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0x508000000
+#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
+ CFG_SYS_BMAN_MEM_BASE)
+#define CFG_SYS_BMAN_MEM_SIZE 0x08000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0x500000000
+#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_SIZE 0x08000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
@@ -134,20 +134,20 @@
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define TP_INIT_PER_CLUSTER 4
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR 0x01000000
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0x01000000
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
- CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index cd11240..ca5e333 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -33,7 +33,7 @@
#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
+#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
@@ -67,8 +67,8 @@
#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
-#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
@@ -105,7 +105,7 @@
#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
/* SFP */
-#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
@@ -173,7 +173,7 @@
#endif
/* Security Monitor */
-#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 6de431f..3ad78cb 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -23,7 +23,7 @@
#define CFG_SYS_NS16550_CLK 13000000
#endif
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
/* NAND */
@@ -49,7 +49,7 @@
/* USB OHCI */
#if defined(CONFIG_USB_OHCI_LPC32XX)
-#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
+#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE
#endif
#endif /* _LPC32XX_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 62026bda..6413a30 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -11,36 +11,36 @@
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
-#define CONFIG_SYS_DCSRBAR 0x20000000
+#define CFG_SYS_DCSRBAR 0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
-#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
+#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000)
+#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
-#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
-#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
-#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
-#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
-#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
+#define CFG_SYS_TSEC1_OFFSET 0x01d10000
+#define CFG_SYS_MDIO1_OFFSET 0x01d24000
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index b0acf67..a0c3da7 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -42,24 +42,24 @@
#define DCFG_DCSR_PORCR1 0
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
#endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
- CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fb5ded8..acd8c69 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -12,14 +12,14 @@
{ .compat = name, \
.id = { idA }, .num_ids = 1, \
.reg_offset = off + CONFIG_SYS_IMMR, \
- .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
{ .compat = name, \
.id = { idA, idB }, .num_ids = 2, \
.reg_offset = off + CONFIG_SYS_IMMR, \
- .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
/*
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index d5c0ed8..a0ab3a0 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -899,9 +899,9 @@
* Generic timer support
*/
#ifdef CONFIG_MX31_CLK32
-#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32
+#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32
#else
-#define CONFIG_SYS_TIMER_RATE 32768
+#define CFG_SYS_TIMER_RATE 32768
#endif
#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
index 5b12d90..eb1ddca 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
@@ -36,6 +36,6 @@
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
+#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index 3525f22..241b449 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -18,6 +18,6 @@
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
-#define CONFIG_SYS_TCLK 24000000
+#define CFG_SYS_TCLK 24000000
#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index cd6112d..9e746e3 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -54,7 +54,7 @@
unsigned long tlb_emerg;
#endif
#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
#define MEM_RESERVE_SECURE_SECURED 0x1
#define MEM_RESERVE_SECURE_MAINTAINED 0x2
#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 826e09e..5e6eaad 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -29,7 +29,7 @@
struct bd_info *bd = gd->bd;
bdinfo_print_num_l("arch_number", bd->bi_arch_number);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
bdinfo_print_num_ll("Secure ram",
gd->arch.secure_ram &
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index bbaaaa4..d05314e 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c
@@ -11,7 +11,7 @@
#include <config.h>
#include <common.h>
-struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
static void pl310_cache_sync(void)
{
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index a2bf2e5..1a589c7 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -152,7 +152,7 @@
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
/*
* Record allocated tlb_addr in case gd->tlb_addr to be overwritten
* with location within secure ram.
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index a54c84b..7cf7d16 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -83,8 +83,8 @@
*/
_start:
-#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
- .word CONFIG_SYS_DV_NOR_BOOT_CFG
+#ifdef CFG_SYS_DV_NOR_BOOT_CFG
+ .word CFG_SYS_DV_NOR_BOOT_CFG
#endif
ARM_VECTORS
#endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c
index c744027..09ac66d 100644
--- a/arch/arm/mach-at91/arm920t/clock.c
+++ b/arch/arm/mach-at91/arm920t/clock.c
@@ -26,7 +26,7 @@
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
@@ -107,7 +107,7 @@
{
unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@@ -120,7 +120,7 @@
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;
diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c
index 44c079c..9bf03fd 100644
--- a/arch/arm/mach-at91/arm920t/cpu.c
+++ b/arch/arm/mach-at91/arm920t/cpu.c
@@ -16,11 +16,11 @@
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
}
diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S
index 3b91a0c..6b7d3cb 100644
--- a/arch/arm/mach-at91/arm920t/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S
@@ -94,11 +94,11 @@
.word AT91_ASM_MC_SMC_CSR0
.word CONFIG_SYS_SMC_CSR0_VAL
.word AT91_ASM_PMC_PLLAR
- .word CONFIG_SYS_PLLAR_VAL
+ .word CFG_SYS_PLLAR_VAL
.word AT91_ASM_PMC_PLLBR
.word CONFIG_SYS_PLLBR_VAL
.word AT91_ASM_PMC_MCKR
- .word CONFIG_SYS_MCKR_VAL
+ .word CFG_SYS_MCKR_VAL
SMRDATAE:
/* here there's a delay */
SMRDATA1:
@@ -107,17 +107,17 @@
.word AT91_ASM_PIOC_BSR
.word CONFIG_SYS_PIOC_BSR_VAL
.word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL
+ .word CFG_SYS_PIOC_PDR_VAL
.word AT91_ASM_MC_EBI_CSA
.word CONFIG_SYS_EBI_CSA_VAL
.word AT91_ASM_MC_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
+ .word CFG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL
+ .word CFG_SYS_SDRC_MR_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
+ .word CFG_SYS_SDRC_MR_VAL1
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
@@ -135,15 +135,15 @@
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
+ .word CFG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRAM1
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL
+ .word CFG_SYS_SDRC_TR_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
+ .word CFG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
SMRDATA1E:
diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c
index c400e87..8ef5764 100644
--- a/arch/arm/mach-at91/arm920t/timer.c
+++ b/arch/arm/mach-at91/arm920t/timer.c
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
int timer_init(void)
{
@@ -92,7 +92,7 @@
u32 endtime;
signed long diff;
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+ tmo = CFG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= 1000;
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index c68e0c0..013daf4 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
@@ -26,7 +26,7 @@
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
@@ -115,7 +115,7 @@
{
unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@@ -128,7 +128,7 @@
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;
diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c
index 761edb6..5e84b0a 100644
--- a/arch/arm/mach-at91/arm926ejs/cpu.c
+++ b/arch/arm/mach-at91/arm926ejs/cpu.c
@@ -15,13 +15,13 @@
#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
}
void arch_preboot_os(void)
diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
index ecfe589..e159a74 100644
--- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
@@ -21,8 +21,8 @@
#ifdef CONFIG_ATMEL_LEGACY
#include <asm/arch/at91sam9_matrix.h>
#endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
+#ifndef CFG_SYS_MATRIX_EBICSA_VAL
+#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL
#endif
.globl lowlevel_init
@@ -67,7 +67,7 @@
ldr r1, =(AT91_ASM_PMC_MOR)
ldr r2, =(AT91_ASM_PMC_SR)
/* Main oscillator Enable register PMC_MOR: */
- ldr r0, =CONFIG_SYS_MOR_VAL
+ ldr r0, =CFG_SYS_MOR_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
@@ -85,7 +85,7 @@
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_ASM_PMC_PLLAR)
- ldr r0, =CONFIG_SYS_PLLAR_VAL
+ ldr r0, =CFG_SYS_PLLAR_VAL
str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */
@@ -105,7 +105,7 @@
ldr r1, =(AT91_ASM_PMC_MCKR)
/* -Master Clock Controller register PMC_MCKR */
- ldr r0, =CONFIG_SYS_MCKR1_VAL
+ ldr r0, =CFG_SYS_MCKR1_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
@@ -116,7 +116,7 @@
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop
- ldr r0, =CONFIG_SYS_MCKR2_VAL
+ ldr r0, =CFG_SYS_MCKR2_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
@@ -158,53 +158,53 @@
SMRDATA:
.word AT91_ASM_WDT_MR
- .word CONFIG_SYS_WDTC_WDMR_VAL
+ .word CFG_SYS_WDTC_WDMR_VAL
/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
.word AT91_ASM_PIOD_PDR
- .word CONFIG_SYS_PIOD_PDR_VAL1
+ .word CFG_SYS_PIOD_PDR_VAL1
.word AT91_ASM_PIOD_PUDR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
+ .word CFG_SYS_PIOD_PPUDR_VAL
.word AT91_ASM_PIOD_ASR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
+ .word CFG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
|| defined(CONFIG_AT91SAM9G20)
.word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL1
+ .word CFG_SYS_PIOC_PDR_VAL1
.word AT91_ASM_PIOC_PUDR
- .word CONFIG_SYS_PIOC_PPUDR_VAL
+ .word CFG_SYS_PIOC_PPUDR_VAL
#endif
.word AT91_ASM_MATRIX_CSA0
- .word CONFIG_SYS_MATRIX_EBICSA_VAL
+ .word CFG_SYS_MATRIX_EBICSA_VAL
/* flash */
.word AT91_ASM_SMC_MODE0
- .word CONFIG_SYS_SMC0_MODE0_VAL
+ .word CFG_SYS_SMC0_MODE0_VAL
.word AT91_ASM_SMC_CYCLE0
- .word CONFIG_SYS_SMC0_CYCLE0_VAL
+ .word CFG_SYS_SMC0_CYCLE0_VAL
.word AT91_ASM_SMC_PULSE0
- .word CONFIG_SYS_SMC0_PULSE0_VAL
+ .word CFG_SYS_SMC0_PULSE0_VAL
.word AT91_ASM_SMC_SETUP0
- .word CONFIG_SYS_SMC0_SETUP0_VAL
+ .word CFG_SYS_SMC0_SETUP0_VAL
SMRDATA1:
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
+ .word CFG_SYS_SDRC_MR_VAL1
.word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL1
+ .word CFG_SYS_SDRC_TR_VAL1
.word AT91_ASM_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
+ .word CFG_SYS_SDRC_CR_VAL
.word AT91_ASM_SDRAMC_MDR
- .word CONFIG_SYS_SDRC_MDR_VAL
+ .word CFG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
+ .word CFG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
+ .word CFG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL2
.word CFG_SYS_SDRAM_BASE
@@ -222,20 +222,20 @@
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL4
+ .word CFG_SYS_SDRC_MR_VAL4
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL5
+ .word CFG_SYS_SDRC_MR_VAL5
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL2
+ .word CFG_SYS_SDRC_TR_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
- .word CONFIG_SYS_RSTC_RMR_VAL
+ .word CFG_SYS_RSTC_RMR_VAL
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
.word AT91_ASM_MATRIX_MCFG
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index aa6bb6b..6bfa02d 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -28,7 +28,7 @@
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
@@ -58,7 +58,7 @@
{
unsigned freq, mckr;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@@ -71,7 +71,7 @@
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;
@@ -271,7 +271,7 @@
clk_source = regval & AT91_PMC_PCR_GCKCSS;
switch (clk_source) {
case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
- freq = CONFIG_SYS_AT91_SLOW_CLOCK;
+ freq = CFG_SYS_AT91_SLOW_CLOCK;
break;
case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
freq = gd->arch.main_clk_rate_hz;
diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c
index 9b37534..616621a 100644
--- a/arch/arm/mach-at91/armv7/cpu.c
+++ b/arch/arm/mach-at91/armv7/cpu.c
@@ -18,8 +18,8 @@
#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
@@ -27,7 +27,7 @@
#if defined(CONFIG_CLK_CCF)
return 0;
#else
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
#endif
}
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 2daeb4f..103db26 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -128,7 +128,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index d5de8d5..2b252f1 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -112,7 +112,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index c9fff93..0aa1862 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -127,7 +127,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 5880325..22116f3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -132,7 +132,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 8f9155c..b2c074e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -112,7 +112,7 @@
#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index e3c494c..0efb4a9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -162,7 +162,7 @@
#endif
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/*
* Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h
index c08d19c..47c7c72 100644
--- a/arch/arm/mach-at91/include/mach/sam9x60.h
+++ b/arch/arm/mach-at91/include/mach/sam9x60.h
@@ -140,7 +140,7 @@
#define ATMEL_CPU_NAME get_cpu_name()
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c
+#define CFG_SYS_TIMER_COUNTER 0xfffffe4c
/*
* Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index 5ff20e9..567cdd3 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -238,7 +238,7 @@
#define cpu_is_sama5d2 _cpu_is_sama5d2
/* PIT Timer(PIT_PIIR) */
-#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
+#define CFG_SYS_TIMER_COUNTER 0xf804803c
#ifndef __ASSEMBLY__
unsigned int get_chip_id(void);
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 83f18a8..9efcf5f 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -185,7 +185,7 @@
#define CPU_HAS_PCR
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/*
* PMECC table in ROM
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index e2edb6a..9c80286 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -217,7 +217,7 @@
(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
+#define CFG_SYS_TIMER_COUNTER 0xfc06863c
/*
* No PMECC Galois table in ROM
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index ea19ec3..dfba9f7 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -101,17 +101,17 @@
at91_pllicpr_init(0x00);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
- at91_plla_init(CONFIG_SYS_AT91_PLLA);
+ at91_plla_init(CFG_SYS_AT91_PLLA);
/* PCK = PLLA = 2 * MCK */
- at91_mck_init(CONFIG_SYS_MCKR);
+ at91_mck_init(CFG_SYS_MCKR);
/* Switch MCK on PLLA output */
- at91_mck_init(CONFIG_SYS_MCKR_CSS);
+ at91_mck_init(CFG_SYS_MCKR_CSS);
-#if defined(CONFIG_SYS_AT91_PLLB)
+#if defined(CFG_SYS_AT91_PLLB)
/* Configure PLLB */
- at91_pllb_init(CONFIG_SYS_AT91_PLLB);
+ at91_pllb_init(CFG_SYS_AT91_PLLB);
#endif
/* Enable External Reset */
@@ -120,7 +120,7 @@
/* Initialize matrix */
matrix_init();
- gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
+ gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK;
/*
* init timer long enough for using in spl.
*/
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 217ed12..a30c4f6 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -124,7 +124,7 @@
/* PMC configuration */
at91_pmc_init();
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
matrix_init();
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index 0f68f9f..dae6026 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -42,7 +42,7 @@
int pll_out;
unsigned int pll_base;
- pll_out = CONFIG_SYS_OSCIN_FREQ;
+ pll_out = CFG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID)
goto out;
diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c
index 2319ac6..08c8f59 100644
--- a/arch/arm/mach-davinci/da850_lowlevel.c
+++ b/arch/arm/mach-davinci/da850_lowlevel.c
@@ -185,9 +185,9 @@
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
}
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
- writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+ writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
- if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+ if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
/* DDR2 */
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_DDR_PDENA_BIT) |
@@ -211,19 +211,19 @@
* At the same time, set the TIMUNLOCK bit to allow changing
* the timing registers
*/
- tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+ tmp = CFG_SYS_DA850_DDR2_SDBCR;
tmp &= ~DV_DDR_BOOTUNLOCK;
tmp |= DV_DDR_TIMUNLOCK;
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */
- if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+ if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
/* MOBILE DDR only*/
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+ writel(CFG_SYS_DA850_DDR2_SDBCR2,
&dv_ddr2_regs_ctrl->sdbcr2);
}
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+ writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+ writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
/* clear the TIMUNLOCK bit and write the value of the CL field */
tmp &= ~DV_DDR_TIMUNLOCK;
@@ -233,7 +233,7 @@
* LPMODEN and MCLKSTOPEN must be set!
* Without this bits set, PSC don;t switch states !!
*/
- writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+ writel(CFG_SYS_DA850_DDR2_SDRCR |
(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
&dv_ddr2_regs_ctrl->sdrcr);
@@ -246,7 +246,7 @@
/* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
- writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+ writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0;
}
@@ -265,7 +265,7 @@
writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
dv_maskbits(&davinci_syscfg_regs->suspsrc,
- CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+ CFG_SYS_DA850_SYSCFG_SUSPSRC);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
@@ -273,8 +273,8 @@
#if defined(CONFIG_SYS_DA850_PLL_INIT)
/* PLL setup */
- da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
- da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+ da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM);
+ da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM);
#endif
/* setup CSn config */
#if defined(CONFIG_SYS_DA850_CS2CFG)
diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c
index 43e0574..83c190b 100644
--- a/arch/arm/mach-davinci/timer.c
+++ b/arch/arm/mach-davinci/timer.c
@@ -32,7 +32,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct davinci_timer * const timer =
- (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
+ (struct davinci_timer *)CFG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL 0xffffffff
@@ -47,7 +47,7 @@
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
writel(2 << 22, &timer->tcr);
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+ gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV;
gd->arch.timer_reset_value = 0;
return(0);
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index f518539..553dac7 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -141,7 +141,7 @@
{
int upto, todo;
int i, timeout = 100;
- struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
+ struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE;
set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* set the spi1 GPIO */
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 0e76786..06ee608 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -248,13 +248,13 @@
int end;
/* Calculate the image set end,
- * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
- * we use CONFIG_SYS_UBOOT_BASE
+ * if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
+ * we use CFG_SYS_UBOOT_BASE
* Otherwise, use the calculated address
*/
end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
- if (end <= CONFIG_SYS_UBOOT_BASE)
- end = CONFIG_SYS_UBOOT_BASE;
+ if (end <= CFG_SYS_UBOOT_BASE)
+ end = CFG_SYS_UBOOT_BASE;
else
end = ROUND(end, SZ_1K);
diff --git a/arch/arm/mach-imx/mx5/lowlevel_init.S b/arch/arm/mach-imx/mx5/lowlevel_init.S
index b42cc3e..6ec38dc 100644
--- a/arch/arm/mach-imx/mx5/lowlevel_init.S
+++ b/arch/arm/mach-imx/mx5/lowlevel_init.S
@@ -205,7 +205,7 @@
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
@@ -215,7 +215,7 @@
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3_BASE_ADDR, 216
@@ -240,10 +240,10 @@
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ ldr r1, =CFG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
@@ -378,7 +378,7 @@
mov r10, lr
mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_SYS_MAIN_PWR_ON)
+#if defined(CFG_SYS_MAIN_PWR_ON)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #1 << 23
diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk
index 9cc1f9e..7bc8af8 100644
--- a/arch/arm/mach-k3/config_secure.mk
+++ b/arch/arm/mach-k3/config_secure.mk
@@ -30,7 +30,7 @@
$(call if_changed,mkfitimage)
MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index 4734e4c..dc97bac 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
@@ -23,7 +23,7 @@
if (argc < 2)
return CMD_RET_USAGE;
- freq = CONFIG_SYS_HZ_CLOCK;
+ freq = CFG_SYS_HZ_CLOCK;
addr = hextoul(argv[1], NULL);
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 98a8f05..424c32a 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -263,7 +263,7 @@
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
-#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
+#define KS2_MSMC_DST_SEG_BASE (CFG_SYS_LPAE_SDRAM_BASE >> \
KS2_MSMC_SEG_SIZE_SHIFT)
/* Device speed */
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 5186f6e..a2781e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -52,8 +52,8 @@
/* Use common timer */
#ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
-#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
+#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK
#endif
#endif /* _KW_CONFIG_H */
diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
index c44eacf..d3a3a83 100644
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
@@ -15,6 +15,6 @@
#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_KW88F6192_H */
diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
index f86cd0b..7f8e156 100644
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
@@ -15,7 +15,7 @@
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock definition */
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \
166666667 : 200000000)
#endif /* _ASM_ARCH_KW88F6281_H */
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 1f8cdf8..67ad5e5 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -659,7 +659,7 @@
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
/* The L2 cache is already disabled at this point */
@@ -691,7 +691,7 @@
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 3b96188..e6383d4 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -54,7 +54,7 @@
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
-#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
+#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
@@ -146,7 +146,7 @@
#define BOOT_FROM_UART 0x30
#define BOOT_FROM_SPI 0x38
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
200000000 : 166000000)
#elif defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
@@ -169,7 +169,7 @@
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
200000000 : 250000000)
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
@@ -188,7 +188,7 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+#define CFG_SYS_TCLK 200000000 /* 200MHz */
#elif defined(CONFIG_ARMADA_XP)
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
@@ -209,7 +209,7 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+#define CFG_SYS_TCLK 250000000 /* 250MHz */
#endif
#endif /* _MVEBU_SOC_H */
diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S
index 60c2072..6c9783a 100644
--- a/arch/arm/mach-mvebu/lowlevel.S
+++ b/arch/arm/mach-mvebu/lowlevel.S
@@ -35,10 +35,10 @@
* Disable L2 cache
*
* NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
- * but CONFIG_SYS_PL310_BASE is already calculated from base
+ * but CFG_SYS_PL310_BASE is already calculated from base
* address SOC_REGS_PHY_BASE.
*/
- ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
+ ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
ldr r0, [r1, #L2X0_CTRL_OFF]
bic r0, #L2X0_CTRL_EN
str r0, [r1, #L2X0_CTRL_OFF]
diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
index cba2e34..ed4b1ca 100644
--- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
+++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
@@ -11,7 +11,7 @@
void set_pl310_ctrl(u32 enable)
{
- struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
writel(enable, &pl310->pl310_ctrl);
}
diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
index f76262b..24ddcdb 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -102,7 +102,7 @@
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c
index 803dc7f..1919748 100644
--- a/arch/arm/mach-omap2/mem-common.c
+++ b/arch/arm/mach-omap2/mem-common.c
@@ -124,11 +124,11 @@
#if defined(CONFIG_NOR)
case MTD_DEV_TYPE_NOR:
gpmc_regs = gpmc_regs_nor;
- base = CONFIG_SYS_FLASH_BASE;
- size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
- ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
- ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
- ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
+ base = CFG_SYS_FLASH_BASE;
+ size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
+ ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+ ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
+ ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
GPMC_SIZE_16M)));
break;
#endif
@@ -142,7 +142,7 @@
#if defined(CONFIG_CMD_ONENAND)
case MTD_DEV_TYPE_ONENAND:
gpmc_regs = gpmc_regs_onenand;
- base = CONFIG_SYS_ONENAND_BASE;
+ base = CFG_SYS_ONENAND_BASE;
size = GPMC_SIZE_128M;
break;
#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 00d91c1..71fdf5b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE;
static ulong get_timer_masked(void);
/*
diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h
index 0e9fe0d..ee0aa94 100644
--- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h
+++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h
@@ -18,6 +18,6 @@
#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE
/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_88F5182_H */
diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c
index d7ea2e3..b373e59 100644
--- a/arch/arm/mach-orion5x/timer.c
+++ b/arch/arm/mach-orion5x/timer.c
@@ -74,7 +74,7 @@
static inline ulong read_timer(void)
{
return readl(CNTMR_VAL_REG(UBOOT_CNTR))
- / (CONFIG_SYS_TCLK / 1000);
+ / (CFG_SYS_TCLK / 1000);
}
DECLARE_GLOBAL_DATA_PTR;
@@ -92,7 +92,7 @@
} else {
/* we have an overflow ... */
timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+ (TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now;
}
lastdec = now;
@@ -115,7 +115,7 @@
ulong delayticks;
current = uboot_cntr_val();
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+ delayticks = (usec * (CFG_SYS_TCLK / 1000000));
if (current < delayticks) {
delayticks -= current;
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h
index 28669e3..485ea7e 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h
@@ -24,7 +24,7 @@
#define MSTP11_BITS 0x00000000
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 4
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h
index 37d134c..2006ad58 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h
@@ -14,7 +14,7 @@
*/
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h
index 06db64a..cc1b00d 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7792.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h
@@ -24,6 +24,6 @@
#define MSTP11_BITS 0x00000008
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 1
#endif /* __ASM_ARCH_R8A7792_H */
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h
index 85f59d9..02f4286 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7793.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h
@@ -15,7 +15,7 @@
*/
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h
index 2bd6e46..a2a949d 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7794.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h
@@ -24,7 +24,7 @@
#define MSTP11_BITS 0x000001C0
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define R8A7794_CUT_ES2 2
#define IS_R8A7794_ES2() \
diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c
index ba06535..293c23b 100644
--- a/arch/arm/mach-rmobile/timer.c
+++ b/arch/arm/mach-rmobile/timer.c
@@ -40,8 +40,8 @@
{
u64 timer = get_cpu_global_timer();
- timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
- do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
+ timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1));
+ do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK));
return timer;
}
@@ -65,7 +65,7 @@
u64 wait;
start = get_cpu_global_timer();
- wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+ wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2);
do {
current = get_cpu_global_timer();
} while ((current - start) < wait);
@@ -83,5 +83,5 @@
ulong get_tbclk(void)
{
- return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+ return (ulong)(CFG_SYS_CPU_CLK >> 2);
}
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 9c19157..5b5a81a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -34,7 +34,7 @@
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
#endif
struct bsel bsel_str[] = {
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 7ce888d..93c9e8b 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -60,7 +60,7 @@
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
@@ -256,7 +256,7 @@
/* If we're still in OCRAM, don't set the XN bit on it */
if (!(gd->flags & GD_FLG_RELOC)) {
set_section_dcache(
- CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+ CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
DCACHE_WRITETHROUGH);
}
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 4edf4f9..e7500c1 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 2c567ed..9edbbf4 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -41,7 +41,7 @@
DECLARE_GLOBAL_DATA_PTR;
#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
-#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+#define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \
SOCFPGA_PHYS_OCRAM_SIZE - \
BOOTROM_SHARED_MEM_SIZE)
#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index a58f1cf..d9e8c84 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c
@@ -10,7 +10,7 @@
#define TIMER_LOAD_VAL 0xFFFFFFFF
-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE;
/*
* Timer initialization
diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c
index f9fd4fe..05a9134 100644
--- a/arch/arm/mach-u8500/cache.c
+++ b/arch/arm/mach-u8500/cache.c
@@ -22,7 +22,7 @@
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_disable(void)
{
- struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
/*
* Linux expects the L2 cache to be turned off by the bootloader.
diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c
index a40bdf1..58247c2 100644
--- a/arch/arm/mach-uniphier/arm32/timer.c
+++ b/arch/arm/mach-uniphier/arm32/timer.c
@@ -10,7 +10,7 @@
#include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
-#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1)
static void *get_global_timer_base(void)
{
diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c
index 739cb29..b471412 100644
--- a/arch/arm/mach-versatile/timer.c
+++ b/arch/arm/mach-versatile/timer.c
@@ -36,9 +36,9 @@
ulong tmr_ctrl_val;
/* 1st disable the Timer */
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+ tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~TIMER_ENABLE;
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+ *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/*
* The Timer Control Register has one Undefined/Shouldn't Use Bit
@@ -52,11 +52,11 @@
* Tmr Siz : 16 Bit Counter
* Tmr in Wrapping Mode
*/
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+ tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+ *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
return 0;
}