global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 17c76bc..d60f494 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -17,8 +17,8 @@
#endif
#endif
-#ifndef CONFIG_SYS_BAUDRATE_TABLE
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#ifndef CFG_SYS_BAUDRATE_TABLE
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
#endif /* __CONFIG_FALLBACKS_H */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 6dfa3dd..246437a 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -13,7 +13,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
@@ -41,11 +41,11 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
-#define CONFIG_SYS_PLL_ODR 0x36
-#define CONFIG_SYS_PLL_FDR 0x7D
+#define CFG_SYS_CLK 166666666 /* CPU Core Clock */
+#define CFG_SYS_PLL_ODR 0x36
+#define CFG_SYS_PLL_FDR 0x7D
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
@@ -53,9 +53,9 @@
* You should know what you are doing if you make changes here.
*/
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
@@ -75,14 +75,14 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/*
* Configuration for environment
@@ -95,15 +95,15 @@
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -117,8 +117,8 @@
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x007F0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x007F0001
+#define CFG_SYS_CS0_CTRL 0x00001FA0
#endif /* _M5208EVBE_H */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index e28662c..128ef50 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -18,14 +18,14 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
-#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
-#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
+#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
+#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
#ifdef CONFIG_MCFFEC
@@ -50,10 +50,10 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 75000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
+#define CFG_SYS_CLK 75000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*
* Low Level Configuration Settings
@@ -63,9 +63,9 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x21
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x21
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -81,16 +81,16 @@
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -104,15 +104,15 @@
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -130,13 +130,13 @@
* CS7 - Available
*/
#ifdef CONFIG_NORFLASH_PS32BIT
-# define CONFIG_SYS_CS0_BASE 0xFFC00000
-# define CONFIG_SYS_CS0_MASK 0x003f0001
-# define CONFIG_SYS_CS0_CTRL 0x00001D00
+# define CFG_SYS_CS0_BASE 0xFFC00000
+# define CFG_SYS_CS0_MASK 0x003f0001
+# define CFG_SYS_CS0_CTRL 0x00001D00
#else
-# define CONFIG_SYS_CS0_BASE 0xFFE00000
-# define CONFIG_SYS_CS0_MASK 0x001f0001
-# define CONFIG_SYS_CS0_CTRL 0x00001D80
+# define CFG_SYS_CS0_BASE 0xFFE00000
+# define CFG_SYS_CS0_MASK 0x001f0001
+# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
#endif /* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index f1da278..0e38eeb 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -18,7 +18,7 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
@@ -26,9 +26,9 @@
* Clock configuration: enable only one of the following options
*/
-#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
-#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
-#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
+#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
+#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
/*
* Low Level Configuration Settings
@@ -36,14 +36,14 @@
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
-#define CONFIG_SYS_MBAR2 0x80000000
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR2 0x80000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
@@ -56,7 +56,7 @@
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -67,33 +67,33 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/*-----------------------------------------------------------------------
@@ -101,25 +101,25 @@
*/
/* CS0 - AMD Flash, address 0xffc00000 */
-#define CONFIG_SYS_CS0_BASE 0xffe00000
-#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
+#define CFG_SYS_CS0_BASE 0xffe00000
+#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
+#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
-#define CONFIG_SYS_CS1_BASE 0xe0000000
-#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
-#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define CFG_SYS_CS1_BASE 0xe0000000
+#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
+#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
-#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
-#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
+#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* M5249 */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index bd3c57d..7e37c6d 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -8,7 +8,7 @@
#include <linux/stringify.h>
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
@@ -20,7 +20,7 @@
env/embedded.o(.text*);
#ifdef CONFIG_DRIVER_DM9000
-# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
+# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
@@ -45,18 +45,18 @@
#define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
-#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
-#define CONFIG_SYS_I2C_PINMUX_SET (0)
+#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C))
+#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
+#define CFG_SYS_I2C_PINMUX_SET (0)
-#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
-#define CONFIG_SYS_FAST_CLK
-#ifdef CONFIG_SYS_FAST_CLK
-# define CONFIG_SYS_PLLCR 0x1243E054
-# define CONFIG_SYS_CLK 140000000
+#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
+# define CFG_SYS_PLLCR 0x1243E054
+# define CFG_SYS_CLK 140000000
#else
-# define CONFIG_SYS_PLLCR 0x135a4140
-# define CONFIG_SYS_CLK 70000000
+# define CFG_SYS_PLLCR 0x135a4140
+# define CFG_SYS_CLK 70000000
#endif
/*
@@ -65,14 +65,14 @@
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
-#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*
* Start addresses for the final memory configuration
@@ -87,10 +87,10 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#define FLASH_SST6401B 0x200
#define SST_ID_xF6401B 0x236D236D
@@ -101,45 +101,45 @@
* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
* 0x30 is block erase in SST
*/
-# define CONFIG_SYS_FLASH_SIZE 0x800000
+# define CFG_SYS_FLASH_SIZE 0x800000
#else
-# define CONFIG_SYS_SST_SECT 2048
-# define CONFIG_SYS_SST_SECTSZ 0x1000
+# define CFG_SYS_SST_SECT 2048
+# define CFG_SYS_SST_SECTSZ 0x1000
#endif
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
-#define CONFIG_SYS_CS0_BASE 0xFF800000
-#define CONFIG_SYS_CS0_MASK 0x007F0021
-#define CONFIG_SYS_CS0_CTRL 0x00001D80
+#define CFG_SYS_CS0_BASE 0xFF800000
+#define CFG_SYS_CS0_MASK 0x007F0021
+#define CFG_SYS_CS0_CTRL 0x00001D80
-#define CONFIG_SYS_CS1_BASE 0xE0000000
-#define CONFIG_SYS_CS1_MASK 0x00000001
-#define CONFIG_SYS_CS1_CTRL 0x00003DD8
+#define CFG_SYS_CS1_BASE 0xE0000000
+#define CFG_SYS_CS1_MASK 0x00000001
+#define CFG_SYS_CS1_CTRL 0x00003DD8
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
-#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
-#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
+#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253DEMO_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 7c3bc03..847b4c2 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -17,7 +17,7 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
@@ -51,22 +51,22 @@
"save\0" \
""
-#define CONFIG_SYS_CLK 66000000
+#define CFG_SYS_CLK 66000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
-#define CONFIG_SYS_SCR 0x0003
-#define CONFIG_SYS_SPR 0xffff
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_SCR 0x0003
+#define CFG_SYS_SPR 0xffff
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -75,35 +75,35 @@
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE 0xffe00000
+#define CFG_SYS_FLASH_BASE 0xffe00000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -111,11 +111,11 @@
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_PACNT 0x00000000
-#define CONFIG_SYS_PADDR 0x0000
-#define CONFIG_SYS_PADAT 0x0000
-#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
-#define CONFIG_SYS_PBDDR 0x0000
-#define CONFIG_SYS_PBDAT 0x0000
-#define CONFIG_SYS_PDCNT 0x00000000
+#define CFG_SYS_PACNT 0x00000000
+#define CFG_SYS_PADDR 0x0000
+#define CFG_SYS_PADAT 0x0000
+#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
+#define CFG_SYS_PBDDR 0x0000
+#define CFG_SYS_PBDAT 0x0000
+#define CFG_SYS_PDCNT 0x00000000
#endif /* _M5272C3_H */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 4eb4abe..ff9f853 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -21,7 +21,7 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -34,9 +34,9 @@
/* Available command configuration */
/* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
-#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
-#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
+#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
+#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0)
+#define CFG_SYS_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC
# define CONFIG_OVERWRITE_ETHADDR_ONCE
@@ -54,7 +54,7 @@
"save\0" \
""
-#define CONFIG_SYS_CLK 150000000
+#define CFG_SYS_CLK 150000000
/*
* Low Level Configuration Settings
@@ -62,13 +62,13 @@
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -77,34 +77,34 @@
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CONFIG_SYS_FLASH_SIZE 0x200000
+#define CFG_SYS_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -112,12 +112,12 @@
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
-#define CONFIG_SYS_CS0_BASE 0xffe00000
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-#define CONFIG_SYS_CS0_MASK 0x001F0001
+#define CFG_SYS_CS0_BASE 0xffe00000
+#define CFG_SYS_CS0_CTRL 0x00001980
+#define CFG_SYS_CS0_MASK 0x001F0001
-#define CONFIG_SYS_CS1_BASE 0x30000000
-#define CONFIG_SYS_CS1_CTRL 0x00001900
-#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CFG_SYS_CS1_BASE 0x30000000
+#define CFG_SYS_CS1_CTRL 0x00001900
+#define CFG_SYS_CS1_MASK 0x00070001
#endif /* _M5275EVB_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index eda3944..bde9e77 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -17,7 +17,7 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
@@ -49,25 +49,25 @@
"save\0" \
""
-#define CONFIG_SYS_CLK 64000000
+#define CFG_SYS_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
+#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -76,65 +76,65 @@
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
+#define CFG_SYS_INT_FLASH_BASE 0xf0000000
+#define CFG_SYS_INT_FLASH_ENABLE 0x21
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
-#define CONFIG_SYS_CS0_BASE 0xFFE00000
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-#define CONFIG_SYS_CS0_MASK 0x001F0001
+#define CFG_SYS_CS0_BASE 0xFFE00000
+#define CFG_SYS_CS0_CTRL 0x00001980
+#define CFG_SYS_CS0_MASK 0x001F0001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
-#define CONFIG_SYS_PADDR 0x0000000
-#define CONFIG_SYS_PADAT 0x0000000
+#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_SYS_PADDR 0x0000000
+#define CFG_SYS_PADAT 0x0000000
-#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
-#define CONFIG_SYS_PBDDR 0x0000000
-#define CONFIG_SYS_PBDAT 0x0000000
+#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_SYS_PBDDR 0x0000000
+#define CFG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
-#define CONFIG_SYS_PEHLPAR 0xC0
-#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
-#define CONFIG_SYS_DDRUA 0x05
-#define CONFIG_SYS_PJPAR 0xFF
+#define CFG_SYS_PEHLPAR 0xC0
+#define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
+#define CFG_SYS_DDRUA 0x05
+#define CFG_SYS_PJPAR 0xFF
#endif /* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 159993a..0e9ba4c 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -18,17 +18,17 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
#ifdef CONFIG_MCFFEC
-# define CONFIG_SYS_TX_ETH_BUFFER 8
-# define CONFIG_SYS_FEC_BUF_USE_SRAM
+# define CFG_SYS_TX_ETH_BUFFER 8
+# define CFG_SYS_FEC_BUF_USE_SRAM
#endif
-#define CONFIG_SYS_RTC_CNT (0x8000)
-#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
+#define CFG_SYS_RTC_CNT (0x8000)
+#define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
/* I2C */
@@ -54,10 +54,10 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
@@ -67,9 +67,9 @@
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
@@ -89,17 +89,17 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_SPANSION_S29WS_N 1
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
#endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -113,15 +113,15 @@
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
@@ -135,12 +135,12 @@
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x00FF0001
+#define CFG_SYS_CS0_CTRL 0x00001FA0
-#define CONFIG_SYS_CS1_BASE 0xC0000000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x00001FA0
+#define CFG_SYS_CS1_BASE 0xC0000000
+#define CFG_SYS_CS1_MASK 0x00070001
+#define CFG_SYS_CS1_CTRL 0x00001FA0
#endif /* _M53017EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index d7ece63..8f83810 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -18,7 +18,7 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
@@ -46,12 +46,12 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
-#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
+#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
@@ -61,9 +61,9 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -83,22 +83,22 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
#ifdef CONFIG_CMD_NAND
-# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -112,15 +112,15 @@
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
@@ -134,18 +134,18 @@
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x007f0001
-#define CONFIG_SYS_CS0_CTRL 0x00001fa0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x007f0001
+#define CFG_SYS_CS0_CTRL 0x00001fa0
-#define CONFIG_SYS_CS1_BASE 0x10000000
-#define CONFIG_SYS_CS1_MASK 0x001f0001
-#define CONFIG_SYS_CS1_CTRL 0x002A3780
+#define CFG_SYS_CS1_BASE 0x10000000
+#define CFG_SYS_CS1_MASK 0x001f0001
+#define CFG_SYS_CS1_CTRL 0x002A3780
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK (16 << 20)
-#define CONFIG_SYS_CS2_CTRL 0x00001f60
+#define CFG_SYS_CS2_BASE 0x20000000
+#define CFG_SYS_CS2_MASK (16 << 20)
+#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
#endif /* _M5329EVB_H */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index b2fc692..43c642e 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -20,7 +20,7 @@
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
@@ -48,12 +48,12 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
-#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
+#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
@@ -63,9 +63,9 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -85,20 +85,20 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -112,15 +112,15 @@
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
@@ -134,16 +134,16 @@
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x007f0001
-#define CONFIG_SYS_CS0_CTRL 0x00001fa0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x007f0001
+#define CFG_SYS_CS0_CTRL 0x00001fa0
-#define CONFIG_SYS_CS1_BASE 0x10000000
-#define CONFIG_SYS_CS1_MASK 0x001f0001
-#define CONFIG_SYS_CS1_CTRL 0x002A3780
+#define CFG_SYS_CS1_BASE 0x10000000
+#define CFG_SYS_CS1_MASK 0x001f0001
+#define CFG_SYS_CS1_CTRL 0x002A3780
-#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK (16 << 20)
-#define CONFIG_SYS_CS2_CTRL 0x00001f60
+#define CFG_SYS_CS2_BASE 0x20000000
+#define CFG_SYS_CS2_MASK (16 << 20)
+#define CFG_SYS_CS2_CTRL 0x00001f60
#endif /* _M5373EVB_H */
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
index 2e7140c..232cf9e 100644
--- a/include/configs/MCR3000.h
+++ b/include/configs/MCR3000.h
@@ -59,21 +59,21 @@
/* Miscellaneous configurable options */
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
-#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
+#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
+#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
#define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* Environment Configuration */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index d9627e3..85c080c 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -25,20 +25,20 @@
*/
/* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
+#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
+#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
+#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
/*
* System IO Config
*/
-#define CONFIG_SYS_SICRH 0x08200000
-#define CONFIG_SYS_SICRL 0x00000000
+#define CFG_SYS_SICRH 0x08200000
+#define CFG_SYS_SICRL 0x00000000
/*
* Output Buffer Impedance
*/
-#define CONFIG_SYS_OBIR 0x30100000
+#define CFG_SYS_OBIR 0x30100000
/*
* Device configurations
@@ -60,9 +60,9 @@
* DDR Setup
*/
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
+#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
+#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
@@ -70,14 +70,14 @@
* Manually set up DDR parameters
*/
#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_3 0x00000000
+#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
@@ -86,7 +86,7 @@
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00260802 */ /* DDR400 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
@@ -95,7 +95,7 @@
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3937d322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (5 << TIMING_CFG2_CPO_SHIFT) \
| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
@@ -104,23 +104,23 @@
| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x02984cc8 */
-#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
+#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x06090100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2)
/* 0x43000000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
+#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
+#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
| (0x0442 << SDRAM_MODE_SD_SHIFT))
/* 0x04400442 */ /* DDR400 */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
+#define CFG_SYS_DDR_MODE2 0x00000000
/*
* Memory test
*/
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
/*
* The reserved memory
@@ -129,14 +129,14 @@
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
+#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
/*
* NAND Flash on the Local Bus
@@ -146,14 +146,14 @@
/* Vitesse 7385 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CFG_SYS_VSC7385_BASE 0xF0000000
/*
* Serial Port
*/
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
@@ -165,13 +165,13 @@
#define CONFIG_FSL_SERDES2 0xe3100
/* I2C */
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
+#define CFG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
@@ -198,7 +198,7 @@
#ifdef CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CFG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
@@ -226,7 +226,7 @@
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 25b4fe0..ff02c2c 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -28,16 +28,16 @@
* Only possible on E500 Version 2 or newer cores.
*/
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xe0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
@@ -112,32 +112,32 @@
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
+#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST \
+ {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_HWCONFIG /* enable hwconfig */
/*
* SDRAM on the Local Bus
*/
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
#else
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -149,12 +149,12 @@
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
@@ -167,10 +167,10 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* Common settings for all Local Bus SDRAM commands.
@@ -178,7 +178,7 @@
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
+#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| LSDMR_PRETOACT7 \
| LSDMR_ACTTORW7 \
| LSDMR_BL8 \
@@ -226,25 +226,25 @@
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/*
* I2C
*/
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+#define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
#endif
/*
@@ -326,7 +326,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
/*
* Environment Configuration
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 21491b9..a8af0a1 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -16,10 +16,10 @@
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CFG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#endif
#ifdef CONFIG_SPIFLASH
@@ -27,10 +27,10 @@
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#endif
#endif
@@ -111,11 +111,11 @@
extern unsigned long get_sdram_size(void);
#endif
#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xffe00000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/*
* Memory map
@@ -136,15 +136,15 @@
*/
/* NOR Flash on IFC */
-#define CONFIG_SYS_FLASH_BASE 0xee000000
+#define CFG_SYS_FLASH_BASE 0xee000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -161,7 +161,7 @@
FTIM2_NOR_TWP(0x1c)
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* CFI for NOR Flash */
@@ -237,85 +237,85 @@
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffb00000
+#define CFG_SYS_CPLD_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
+#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
#else
-#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
#endif
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 0x0
+#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Config the L2 Cache as L2 SRAM
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif
#endif
#endif
@@ -324,11 +324,11 @@
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */
#define I2C_PCA9557_ADDR1 0x18
@@ -343,7 +343,7 @@
/* RTC */
#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/*
* SPI interface will not be available in case of NAND boot SPI CS0 will be
@@ -393,7 +393,7 @@
*/
#if defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#endif
@@ -410,7 +410,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index c3ef216..1e02855 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -39,32 +39,32 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
+#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
CONFIG_RAMBOOT_TEXT_BASE)
#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
+#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
#endif
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
@@ -74,18 +74,18 @@
*/
/* Set the local bus clock 1/8 of platform clock */
-#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
+#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
/*
* This board doesn't have a promjet connector.
* However, it uses commone corenet board LAW and TLB.
* It is necessary to use the same start address with proper offset.
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CFG_SYS_FLASH_BASE 0xe0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
+#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
#define CONFIG_FSL_CPLD
@@ -130,28 +130,28 @@
| OR_FCM_EHTR)
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
@@ -159,13 +159,13 @@
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -244,52 +244,52 @@
#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
+#define CFG_SYS_BMAN_MEM_SIZE 0x00200000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf4200000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
+#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull
#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_MEM_SIZE 0x00200000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
-#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
+#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
+#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
+#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
+#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
+#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
+#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
+#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
+#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
+#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
+#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
-#define CONFIG_SYS_TBIPA_VALUE 8
+#define CFG_SYS_TBIPA_VALUE 8
#endif
#ifdef CONFIG_MMC
@@ -305,7 +305,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
/*
* Environment Configuration
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index 417b9ae..bad34d9 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h
@@ -12,7 +12,7 @@
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
@@ -32,7 +32,7 @@
* U-Boot bootcode configuration
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index 87b6822..9a9663b 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h
@@ -12,7 +12,7 @@
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
@@ -37,7 +37,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index b567b63..b5fb0a9 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -29,18 +29,18 @@
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
@@ -93,7 +93,7 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
@@ -101,20 +101,20 @@
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS 0x51
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
@@ -125,15 +125,15 @@
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE 0xe8000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -160,30 +160,30 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT (0xf)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
+#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
+#define CFG_SYS_CS2_FTIM3 0x0
#endif
/* NAND Flash on IFC */
@@ -235,72 +235,72 @@
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -315,7 +315,7 @@
*/
#define RTC
#define CONFIG_RTC_DS1337 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/*
* eSPI - Enhanced SPI
@@ -363,36 +363,37 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -421,7 +422,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 37dfe32..bee4b70 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -36,18 +36,18 @@
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif
@@ -63,7 +63,7 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
@@ -71,24 +71,24 @@
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
/*
- * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
- * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
- * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
+ * (CFG_SYS_INIT_L3_VADDR) will be different.
*/
-#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
@@ -97,11 +97,11 @@
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR_CSPR_EXT (0xf)
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -128,7 +128,7 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* CPLD on IFC */
#define CPLD_LBMAP_MASK 0x3F
@@ -157,25 +157,25 @@
#define CPLD_INT_MASK_TDMR2 0x01
#endif
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT (0xf)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
+#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
+#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
@@ -213,55 +213,55 @@
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
@@ -269,13 +269,13 @@
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
@@ -289,7 +289,7 @@
*/
#define RTC
#define CONFIG_RTC_DS1337 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/*DVI encoder*/
#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
@@ -344,58 +344,58 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#define CFG_SYS_SGMII1_PHY_ADDR 0x03
#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
+#define CFG_SYS_SGMII1_PHY_ADDR 0x01
#elif defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
-#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
-#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
+#define CFG_SYS_SGMII1_PHY_ADDR 0x02
+#define CFG_SYS_SGMII2_PHY_ADDR 0x03
+#define CFG_SYS_SGMII3_PHY_ADDR 0x01
#endif
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
+#define CFG_SYS_RGMII1_PHY_ADDR 0x04
+#define CFG_SYS_RGMII2_PHY_ADDR 0x05
#else
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
+#define CFG_SYS_RGMII1_PHY_ADDR 0x01
+#define CFG_SYS_RGMII2_PHY_ADDR 0x02
#endif
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_VSC9953
#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#else
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
#endif
#endif
#endif
@@ -409,7 +409,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Dynamic MTD Partition support with mtdparts
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 798822e..be8c30d 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -31,18 +31,18 @@
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
@@ -69,18 +69,18 @@
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
@@ -90,16 +90,16 @@
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_FLASH_BASE 0xe0000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR_EXT (0xf)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -121,8 +121,8 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
#define QIXIS_BASE 0xffdf0000
#define QIXIS_LBMAP_SWITCH 6
@@ -141,23 +141,23 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_EXT (0xf)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 0x0
/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
@@ -195,81 +195,81 @@
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/*
* I2C
@@ -360,28 +360,28 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 18
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 18
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 18
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 18
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -418,7 +418,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index ea366b6..795873f 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -31,18 +31,18 @@
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
@@ -69,18 +69,18 @@
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
@@ -90,10 +90,10 @@
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -116,29 +116,29 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS }
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT (0xf)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
+#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
+#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
@@ -176,65 +176,65 @@
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/*
* I2C
@@ -319,28 +319,28 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 18
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 18
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 18
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 18
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -384,7 +384,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index cc86c9d..ffd5645 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -24,10 +24,10 @@
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST 0x00200000
+#define CFG_SYS_MMC_U_BOOT_START 0x00200000
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif
@@ -51,39 +51,39 @@
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE 0xe0000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
@@ -91,13 +91,13 @@
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -135,7 +135,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
@@ -159,14 +159,14 @@
/*
* IFC Definitions
*/
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR_EXT (0xf)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -188,8 +188,8 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
@@ -227,71 +227,71 @@
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR3_EXT (0xf)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
/* I2C */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
@@ -318,28 +318,28 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 50
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 50
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 25d9c96..69b8b04 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -205,8 +205,8 @@
* 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
*/
#if defined(CONFIG_NOR)
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CFG_SYS_FLASH_BASE (0x08000000)
+#define CFG_SYS_FLASH_SIZE 0x01000000
#endif /* NOR support */
#endif /* ! __CONFIG_AM335X_EVM_H */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index a9a4c8d..c57a0dd 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -89,7 +89,7 @@
/* on one chip */
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CFG_SYS_FLASH_BASE NAND_BASE
#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 4ff8528..bcdff2e 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -9,7 +9,7 @@
#define __CONFIG_AM43XX_EVM_H
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
@@ -25,7 +25,7 @@
/* SPL defines. */
/* Enabling L2 Cache */
-#define CONFIG_SYS_PL310_BASE 0x48242000
+#define CFG_SYS_PL310_BASE 0x48242000
/*
* When building U-Boot such that there is no previous loader
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 84555f3..340a8ce 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -53,9 +53,9 @@
* 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
* 0x9E0000 - 0x2000000 : USERLAND
*/
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
+#define CFG_SYS_SPI_ARGS_OFFS 0x140000
+#define CFG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index eba78d3..ee0be97 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -10,7 +10,7 @@
#define CONFIG_HOSTNAME "AMCORE"
-#define CONFIG_SYS_UART_PORT 0
+#define CFG_SYS_UART_PORT 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"upgrade_uboot=loady; " \
@@ -24,21 +24,21 @@
"erase 0xfff00000 0xffffffff; " \
"cp.b 0x20000 0xfff00000 ${filesize}\0"
-#define CONFIG_SYS_CLK 45000000
-#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
+#define CFG_SYS_CLK 45000000
+#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2)
/* Register Base Addrs */
-#define CONFIG_SYS_MBAR 0x10000000
+#define CFG_SYS_MBAR 0x10000000
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
/* size of internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 0x1000000
-#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CFG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/* reserve 128-4KB */
#define LDS_BOARD_TEXT \
@@ -46,7 +46,7 @@
env/embedded.o(.text*);
/* memory map space for linux boot data */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/*
* Cache Configuration
@@ -56,25 +56,25 @@
* sdram - single region - no masks
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
CF_ACR_EN)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
CF_CACR_EC)
/* CS0 - AMD Flash, address 0xffc00000 */
-#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
+#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16)
/* 4MB, AA=0,V=1 C/I BIT for errata */
-#define CONFIG_SYS_CS0_MASK 0x003f0001
+#define CFG_SYS_CS0_MASK 0x003f0001
/* WS=10, AA=1, PS=16bit (10) */
-#define CONFIG_SYS_CS0_CTRL 0x1980
+#define CFG_SYS_CS0_CTRL 0x1980
/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
-#define CONFIG_SYS_CS1_BASE 0x3000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x0100
+#define CFG_SYS_CS1_BASE 0x3000
+#define CFG_SYS_CS1_MASK 0x00070001
+#define CFG_SYS_CS1_CTRL 0x0100
#endif /* __AMCORE_CONFIG_H */
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 63c7dfc..9c6f763 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Miscellaneous configurable options */
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 865aad2..034cd7a 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
/*
* Serial Port
diff --git a/include/configs/ap152.h b/include/configs/ap152.h
index 0464a69..c56b351 100644
--- a/include/configs/ap152.h
+++ b/include/configs/ap152.h
@@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
/*
* Serial Port
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 356d4c3..c9375b4 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -107,7 +107,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index ed32e77..60758b0 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h
@@ -7,9 +7,9 @@
#define __CONFIG_ARBEL_H
#define CFG_SYS_SDRAM_BASE 0x0
-#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
-#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_BOOTMAPSZ (20 << 20)
+#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 90cf470..c1eec5d 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -20,7 +20,7 @@
#endif
/* Framebuffer */
-#define CONFIG_SYS_LDB_CLOCK 28341000
+#define CFG_SYS_LDB_CLOCK 28341000
#include "mx6_common.h"
@@ -407,8 +407,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_FSL_USDHC_NUM 2
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
index cbd0d6c..bb1bd50 100644
--- a/include/configs/aspeed-common.h
+++ b/include/configs/aspeed-common.h
@@ -17,11 +17,11 @@
#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ
-#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
-#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
+#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
+#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
-#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
+#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
#endif
/*
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index b142ea3..f5922fc 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -55,19 +55,19 @@
* interface etc.
*/
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3)
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/*
* Define baudrate for UART1 (console output, tftp, ...)
* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * CFG_SYS_BAUDRATE_TABLE defines values that can be selected
* in u-boot command interface
*/
-#define CONFIG_SYS_UART_PORT (2)
-#define CONFIG_SYS_UART2_ALT3_GPIO
+#define CFG_SYS_UART_PORT (2)
+#define CFG_SYS_UART2_ALT3_GPIO
/*
* Watchdog configuration; Watchdog is disabled for running from RAM
@@ -125,7 +125,7 @@
* it needs non-blocking CFI routines.
*/
-#define CONFIG_SYS_FPGA_WAIT 1000
+#define CFG_SYS_FPGA_WAIT 1000
/* End of user parameters to be customized */
@@ -139,19 +139,19 @@
/* Base register address */
-#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
/* System Conf. Reg. & System Protection Reg. */
-#define CONFIG_SYS_SCR 0x0003;
-#define CONFIG_SYS_SPR 0xffff;
+#define CFG_SYS_SCR 0x0003;
+#define CFG_SYS_SPR 0xffff;
/*
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
@@ -170,23 +170,23 @@
* CS4 - unused
* CS5 - unused
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x00ff0001
-#define CONFIG_SYS_CS0_CTRL 0x00001fc0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x00ff0001
+#define CFG_SYS_CS0_CTRL 0x00001fc0
-#define CONFIG_SYS_CS1_BASE 0x01000000
-#define CONFIG_SYS_CS1_MASK 0x00ff0001
-#define CONFIG_SYS_CS1_CTRL 0x00001fc0
+#define CFG_SYS_CS1_BASE 0x01000000
+#define CFG_SYS_CS1_MASK 0x00ff0001
+#define CFG_SYS_CS1_CTRL 0x00001fc0
-#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK 0x00ff0001
-#define CONFIG_SYS_CS2_CTRL 0x0000fec0
+#define CFG_SYS_CS2_BASE 0x20000000
+#define CFG_SYS_CS2_MASK 0x00ff0001
+#define CFG_SYS_CS2_CTRL 0x0000fec0
-#define CONFIG_SYS_CS3_BASE 0x21000000
-#define CONFIG_SYS_CS3_MASK 0x00ff0001
-#define CONFIG_SYS_CS3_CTRL 0x0000fec0
+#define CFG_SYS_CS3_BASE 0x21000000
+#define CFG_SYS_CS3_MASK 0x00ff0001
+#define CFG_SYS_CS3_CTRL 0x0000fec0
-#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CFG_SYS_FLASH_BASE 0x00000000
/* Reserve 256 kB for Monitor */
@@ -195,12 +195,12 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
(CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_SIZE 0x2000000
+#define CFG_SYS_FLASH_SIZE 0x2000000
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
@@ -208,15 +208,15 @@
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
#endif /* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 4631acf..4aa876a 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -12,7 +12,7 @@
#include <linux/kconfig.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#endif
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 0d76f41..b9cc7ba 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -24,8 +24,8 @@
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/*
* SDRAM: 1 bank, min 32, max 128 MB
@@ -34,11 +34,11 @@
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
#ifdef CONFIG_AT91SAM9XE
-# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
#else
-# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
#endif
/* NAND flash */
@@ -51,6 +51,6 @@
#endif
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
#endif
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index dcc1cca..56247e3 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -11,16 +11,16 @@
#define __CONFIG_H
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#include <asm/hardware.h>
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */
#ifdef CONFIG_CMD_NAND
@@ -42,6 +42,6 @@
#define CONFIG_DM9000_NO_SROM
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
#endif
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index aefa9fc..afdb747 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -19,20 +19,20 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NOR flash, if populated */
#ifdef CONFIG_SYS_USE_NORFLASH
#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* Address and size of Primary Environment Sector */
@@ -50,9 +50,9 @@
#define MASTER_PLL_OUT 3
/* clocks */
-#define CONFIG_SYS_MOR_VAL \
+#define CFG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
-#define CONFIG_SYS_PLLAR_VAL \
+#define CFG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | \
AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
AT91_PMC_PLLXR_PLLCOUNT(63) | \
@@ -60,31 +60,31 @@
AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+#define CFG_SYS_MATRIX_EBICSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 0
+#define CFG_SYS_SDRC_MR_VAL1 0
/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+#define CFG_SYS_SDRC_TR_VAL1 0x13C
/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
+#define CFG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
@@ -98,10 +98,10 @@
(1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
@@ -110,35 +110,35 @@
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
+#define CFG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
+#define CFG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+#define CFG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
+#define CFG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
+#define CFG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_MR_URSTEN | \
AT91_RSTC_MR_ERSTL(15))
/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
+#define CFG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
@@ -160,6 +160,6 @@
#endif
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#endif
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 08cfee1..2ceb806 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -11,8 +11,8 @@
#define __CONFIG_H
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x70000000
@@ -41,9 +41,9 @@
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 76f87c1..0f9e2cf 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -10,8 +10,8 @@
#define __AT91SAM9N12_CONFIG_H_
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
#define CFG_SYS_SDRAM_BASE 0x20000000
@@ -35,9 +35,9 @@
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20953f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20953f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index e1111b6..cad00f6 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -13,15 +13,15 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index eb1d1ad..509c458 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -9,8 +9,8 @@
#define __CONFIG_H__
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* general purpose I/O */
@@ -38,9 +38,9 @@
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index 83ac87b..03e04e6 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -39,15 +39,15 @@
/* support JEDEC */
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
/* max number of memory banks */
/*
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
-#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
@@ -63,7 +63,7 @@
*/
/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+#define CFG_SYS_BOOTMAPSZ (64 << 20)
/* Increase max gunzip size */
/* Support autoboot from RAM (kernel image is loaded via debug port) */
diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h
index 6d82712..04dc50b 100644
--- a/include/configs/axs10x.h
+++ b/include/configs/axs10x.h
@@ -19,8 +19,8 @@
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_512M
/*
diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h
index cba109b..43edc91 100644
--- a/include/configs/bcm7260.h
+++ b/include/configs/bcm7260.h
@@ -12,7 +12,7 @@
#define CFG_SYS_NS16550_COM1 0xf040c000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
+#define CFG_SYS_INIT_RAM_ADDR 0x10200000
#include "bcmstb.h"
diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h
index a07f1b7..1143372 100644
--- a/include/configs/bcm7445.h
+++ b/include/configs/bcm7445.h
@@ -12,7 +12,7 @@
#define CFG_SYS_NS16550_COM1 0xf040ab00
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
+#define CFG_SYS_INIT_RAM_ADDR 0x80200000
#include "bcmstb.h"
diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h
index f1b68ba..c61acf6 100644
--- a/include/configs/bcm963138.h
+++ b/include/configs/bcm963138.h
@@ -7,6 +7,6 @@
#define __BCM963138_H
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_HZ_CLOCK 500000000
+#define CFG_SYS_HZ_CLOCK 500000000
#endif
diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h
index 9769a71..57360b6 100644
--- a/include/configs/bcmstb.h
+++ b/include/configs/bcmstb.h
@@ -82,7 +82,7 @@
* initramfs images, in which case this limitation is eliminated.
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
+#define CFG_SYS_INIT_RAM_SIZE 0x100000
/*
* CONFIG_SYS_LOAD_ADDR - 1 MiB.
@@ -102,7 +102,7 @@
/*
* Serial console configuration.
*/
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/*
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index a075a5b..0842a4a 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -200,7 +200,7 @@
#define PHYS_SDRAM_SIZE (SZ_512M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index 0b1fc91..cb28ae2 100644
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -26,10 +26,10 @@
#define CONFIG_SH_QSPI_BASE 0xE6B10000
#else
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
+#define CFG_SYS_FLASH_BASE 0x00000000
+#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
+#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
+#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) }
#endif
/* Board Clock */
diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h
index e40f110..0d254cd 100644
--- a/include/configs/bmips_bcm3380.h
+++ b/include/configs/bmips_bcm3380.h
@@ -14,7 +14,7 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM3380_H */
diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
index 508317f..7865b9c 100644
--- a/include/configs/bmips_bcm6318.h
+++ b/include/configs/bmips_bcm6318.h
@@ -14,7 +14,7 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6318_H */
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
index c5bda16..93426d2 100644
--- a/include/configs/bmips_bcm63268.h
+++ b/include/configs/bmips_bcm63268.h
@@ -14,7 +14,7 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM63268_H */
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index 32397c2..e992fe6 100644
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h
@@ -14,7 +14,7 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6328_H */
diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h
index 18c9972..224b697 100644
--- a/include/configs/bmips_bcm6338.h
+++ b/include/configs/bmips_bcm6338.h
@@ -14,9 +14,9 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xbfc00000
+#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6338_H */
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
index f8d7148..3211d23 100644
--- a/include/configs/bmips_bcm6348.h
+++ b/include/configs/bmips_bcm6348.h
@@ -14,9 +14,9 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xbfc00000
+#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6348_H */
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
index d564a32..7e2449c 100644
--- a/include/configs/bmips_bcm6358.h
+++ b/include/configs/bmips_bcm6358.h
@@ -14,9 +14,9 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xbe000000
+#define CFG_SYS_FLASH_BASE 0xbe000000
#endif /* __CONFIG_BMIPS_BCM6358_H */
diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
index f982a43..443ee47 100644
--- a/include/configs/bmips_bcm6362.h
+++ b/include/configs/bmips_bcm6362.h
@@ -14,7 +14,7 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6362_H */
diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
index 11d623c..c550f97 100644
--- a/include/configs/bmips_bcm6368.h
+++ b/include/configs/bmips_bcm6368.h
@@ -14,9 +14,9 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xb8000000
+#define CFG_SYS_FLASH_BASE 0xb8000000
#endif /* __CONFIG_BMIPS_BCM6368_H */
diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h
index 30965c8..f212914 100644
--- a/include/configs/bmips_bcm6838.h
+++ b/include/configs/bmips_bcm6838.h
@@ -14,7 +14,7 @@
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6838_H */
diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
index 7e358a6..3cdd0e4 100644
--- a/include/configs/bmips_common.h
+++ b/include/configs/bmips_common.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 500000, 1500000 }
#endif /* __CONFIG_BMIPS_COMMON_H */
diff --git a/include/configs/boston.h b/include/configs/boston.h
index 0033a7f..14ce8a4 100644
--- a/include/configs/boston.h
+++ b/include/configs/boston.h
@@ -27,7 +27,7 @@
# define CFG_SYS_SDRAM_BASE 0x80000000
#endif
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/*
* Console
diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h
index 78b2000..d35c7c4 100644
--- a/include/configs/brppt2.h
+++ b/include/configs/brppt2.h
@@ -13,7 +13,7 @@
/* -- i.mx6 specifica -- */
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
+#define CFG_SYS_PL310_BASE L2_PL310_BASE
#endif /* !CONFIG_SYS_L2CACHE_OFF */
#define CONFIG_MXC_GPT_HCLK
@@ -77,8 +77,8 @@
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Ethernet */
#define CONFIG_FEC_FIXED_SPEED _1000BASET
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index f1734aa..3e0b425 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -22,7 +22,7 @@
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index 6f2b824..6f3396b 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -19,7 +19,7 @@
/* Flat Device Tree Definitions */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
index f268dfd..3329c24 100644
--- a/include/configs/ci20.h
+++ b/include/configs/ci20.h
@@ -12,7 +12,7 @@
/* Memory configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */
#define CFG_SYS_NS16550_CLK 48000000
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index eb899c4..b1f9470 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -23,8 +23,8 @@
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
+#define CFG_SYS_I2C_PCA953X_ADDR 0x20
+#define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
#undef CONFIG_EXTRA_ENV_SETTINGS
@@ -83,8 +83,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* SPI Flash support */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 47c4aac..d5c0395 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -22,8 +22,8 @@
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Serial console */
#define CONFIG_MXC_UART_BASE UART4_BASE
@@ -139,7 +139,7 @@
#define CONFIG_MXC_USB_FLAGS 0
/* Boot */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* misc */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 8f05821..8ad1cfb 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -9,7 +9,7 @@
#define __CONFIG_CM_T43_H
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
@@ -32,7 +32,7 @@
#define CONFIG_POWER_TPS65218
/* Enabling L2 Cache */
-#define CONFIG_SYS_PL310_BASE 0x48242000
+#define CFG_SYS_PL310_BASE 0x48242000
/*
* Since SPL did pll and ddr initialization for us,
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 65b9074..01828ea 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -29,18 +29,18 @@
* ---
*/
-#define CONFIG_SYS_CLK 66000000
+#define CFG_SYS_CLK 66000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
* interface
* ---
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
/* ---
* set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
@@ -133,21 +133,21 @@
* ---
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
/* ---
* System Conf. Reg. & System Protection Reg.
* ---
*/
-#define CONFIG_SYS_SCR 0x0003
-#define CONFIG_SYS_SPR 0xffff
+#define CFG_SYS_SCR 0x0003
+#define CFG_SYS_SPR 0xffff
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -168,28 +168,28 @@
*-----------------------------------------------------------------------
*/
-#define CONFIG_SYS_FLASH_BASE 0xffe00000
+#define CFG_SYS_FLASH_BASE 0xffe00000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -209,15 +209,15 @@
/*-----------------------------------------------------------------------
* Port configuration (GPIO)
*/
-#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
+#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
GPIO*/
-#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
+#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
(1^=output, 0^=input) */
-#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
-#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
+#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
+#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
configuration */
-#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
-#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
-#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
+#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
+#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
+#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
#endif /* _CONFIG_COBRA5272_H */
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index ca8445a..12dc946 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -117,8 +117,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 14278e9..c6a79de 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -101,7 +101,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index c080955..32a79b0 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -161,8 +161,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 1128307..fa778ec 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -86,8 +86,8 @@
#define PHYS_SDRAM_SIZE (256 * SZ_1M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB Host Support */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index c7a3e47..8a61086 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -24,8 +24,8 @@
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* serial console */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
@@ -63,10 +63,10 @@
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_MASTER_CLOCK 132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index e2e1cfe..578277f 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -17,13 +17,13 @@
/*
* SoC Configuration
*/
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_OSCIN_FREQ 24000000
+#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+#define CFG_SYS_DV_NOR_BOOT_CFG (0x11)
#endif
/*
@@ -36,7 +36,7 @@
/* memtest will be run on 16MB */
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
@@ -47,17 +47,17 @@
* PLL configuration
*/
-#define CONFIG_SYS_DA850_PLL0_PLLM 24
-#define CONFIG_SYS_DA850_PLL1_PLLM 21
+#define CFG_SYS_DA850_PLL0_PLLM 24
+#define CFG_SYS_DA850_PLL1_PLLM 21
/*
* DDR2 memory configuration
*/
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+#define CFG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
@@ -67,9 +67,9 @@
(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR ( \
(14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
@@ -79,7 +79,7 @@
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(0 << DV_DDR_SDTMR1_WTR_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(0 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
@@ -88,20 +88,20 @@
(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(0 << DV_DDR_SDTMR2_CKE_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494
+#define CFG_SYS_DA850_DDR2_PBBPR 0x30
/*
* Serial Driver info
*/
#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/*
* I2C Configuration
*/
-#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
/*
* Flash & Environment
@@ -125,7 +125,7 @@
#endif
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
#endif
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index b16f3d4..4b31bbf 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -43,8 +43,8 @@
#define PHYS_SDRAM_SIZE SZ_512M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index c473f3d..66aa6d5 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -29,8 +29,8 @@
/*
* NOR Flash
*/
-#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
-#define CONFIG_SYS_FLASH_SIZE SZ_4M
+#define CFG_SYS_FLASH_BASE EMC_CS0_BASE
+#define CFG_SYS_FLASH_SIZE SZ_4M
/*
* NAND controller
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index ddc436d..f9b3d19 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -73,8 +73,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment */
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 0a7428b..7636d28 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -30,9 +30,9 @@
*/
/* Below values are "dummy" - only to avoid build break */
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000
+#define CFG_SYS_SPI_KERNEL_OFFS 0x150000
+#define CFG_SYS_SPI_ARGS_OFFS 0x140000
+#define CFG_SYS_SPI_ARGS_SIZE 0x10000
#define CONFIG_MXC_UART_BASE UART5_BASE
@@ -285,8 +285,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* ENV config */
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index bb335a0..8217712 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -63,9 +63,9 @@
* 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
* 0x9E0000 - 0x2000000 : USERLAND
*/
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
+#define CFG_SYS_SPI_ARGS_OFFS 0x140000
+#define CFG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
@@ -87,8 +87,8 @@
/* Parallel NOR Support */
#if defined(CONFIG_NOR)
/* NOR: device related configs */
-#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
+#define CFG_SYS_FLASH_BASE (0x08000000)
/* Reduce SPL size by removing unlikey targets */
#endif /* NOR support */
diff --git a/include/configs/draak.h b/include/configs/draak.h
index 8bfba78..8140bc4 100644
--- a/include/configs/draak.h
+++ b/include/configs/draak.h
@@ -14,7 +14,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __DRAAK_H */
diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h
index 677a485..bd88c42 100644
--- a/include/configs/dragonboard845c.h
+++ b/include/configs/dragonboard845c.h
@@ -11,7 +11,7 @@
#include <linux/sizes.h>
#include <asm/arch/sysmap-sdm845.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 80de73d..426155d 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -12,7 +12,7 @@
* High Level Configuration Options (easy to change) *
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
@@ -27,18 +27,18 @@
* Environment is in the second sector of the first 256k of flash *
*----------------------------------------------------------------------*/
-/*#define CONFIG_SYS_DRAM_TEST 1 */
-#undef CONFIG_SYS_DRAM_TEST
+/*#define CFG_SYS_DRAM_TEST 1 */
+#undef CFG_SYS_DRAM_TEST
/*----------------------------------------------------------------------*
* Clock and PLL Configuration *
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
+#define CFG_SYS_CLK 80000000 /* 8MHz * 8 */
/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
+#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*----------------------------------------------------------------------*
* Network *
@@ -54,14 +54,14 @@
* You should know what you are doing if you make changes here.
*-----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*-----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -79,34 +79,34 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
+#define CFG_SYS_INT_FLASH_BASE 0xF0000000
+#define CFG_SYS_INT_FLASH_ENABLE 0x21
-#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
+#define CFG_SYS_FLASH_SIZE 16*1024*1024
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
CF_CACR_EUSP)
@@ -114,36 +114,36 @@
* Memory bank definitions
*/
-#define CONFIG_SYS_CS0_BASE 0xFF000000
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
+#define CFG_SYS_CS0_BASE 0xFF000000
+#define CFG_SYS_CS0_CTRL 0x00001980
+#define CFG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS2_BASE 0xE0000000
-#define CONFIG_SYS_CS2_CTRL 0x00001980
-#define CONFIG_SYS_CS2_MASK 0x000F0001
+#define CFG_SYS_CS2_BASE 0xE0000000
+#define CFG_SYS_CS2_CTRL 0x00001980
+#define CFG_SYS_CS2_MASK 0x000F0001
-#define CONFIG_SYS_CS3_BASE 0xE0100000
-#define CONFIG_SYS_CS3_CTRL 0x00001980
-#define CONFIG_SYS_CS3_MASK 0x000F0001
+#define CFG_SYS_CS3_BASE 0xE0100000
+#define CFG_SYS_CS3_CTRL 0x00001980
+#define CFG_SYS_CS3_MASK 0x000F0001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
-#define CONFIG_SYS_PADDR 0x0000000
-#define CONFIG_SYS_PADAT 0x0000000
+#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_SYS_PADDR 0x0000000
+#define CFG_SYS_PADAT 0x0000000
-#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
-#define CONFIG_SYS_PBDDR 0x0000000
-#define CONFIG_SYS_PBDAT 0x0000000
+#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_SYS_PBDDR 0x0000000
+#define CFG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
-#define CONFIG_SYS_PASPAR 0x0F0F
-#define CONFIG_SYS_PEHLPAR 0xC0
-#define CONFIG_SYS_PUAPAR 0x0F
-#define CONFIG_SYS_DDRUA 0x05
-#define CONFIG_SYS_PJPAR 0xFF
+#define CFG_SYS_PASPAR 0x0F0F
+#define CFG_SYS_PEHLPAR 0xC0
+#define CFG_SYS_PUAPAR 0x0F
+#define CFG_SYS_DDRUA 0x05
+#define CFG_SYS_PJPAR 0xFF
/*-----------------------------------------------------------------------
* I2C
diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
index 597efd6..d1882a9 100644
--- a/include/configs/ebisu.h
+++ b/include/configs/ebisu.h
@@ -16,7 +16,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __EBISU_H */
diff --git a/include/configs/edison.h b/include/configs/edison.h
index b05141a..455a889 100644
--- a/include/configs/edison.h
+++ b/include/configs/edison.h
@@ -10,6 +10,6 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CFG_SYS_STACK_SIZE (32 * 1024)
#endif
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index d24bc56..141f991 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -51,8 +51,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index e39bb94..29b7748 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -28,8 +28,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index 6cae663..6647148 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -16,7 +16,7 @@
/* NAND specific changes for etamin due to different page size */
#undef CFG_SYS_NAND_ECCPOS
-#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
+#define CFG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 97a8ffb..52eb0be 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -18,19 +18,19 @@
/* CPU information */
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
/* 32kB internal SRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
-#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10)
+#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
+#define CFG_SYS_INIT_RAM_SIZE (32 << 10)
/* 128MB SDRAM in 1 bank */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE (128 << 20)
/* 512kB on-chip NOR flash */
-# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
+# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
@@ -53,16 +53,16 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
+#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
#endif
/* RTC */
#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+#define CFG_SYS_I2C_RTC_ADDR 0x51
#endif
/* I2C */
-#define CONFIG_SYS_MAX_I2C_BUS 1
+#define CFG_SYS_MAX_I2C_BUS 1
#define I2C_SOFT_DECLARATIONS
diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h
index cd6cb06..bec1660 100644
--- a/include/configs/evb_ast2500.h
+++ b/include/configs/evb_ast2500.h
@@ -11,7 +11,7 @@
#include <configs/aspeed-common.h>
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Misc */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h
index ecd05fe..c9c988b 100644
--- a/include/configs/evb_ast2600.h
+++ b/include/configs/evb_ast2600.h
@@ -8,7 +8,7 @@
#include <configs/aspeed-common.h>
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Misc */
#define STR_HELPER(s) #s
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
index a94f5a1..c9e0c13 100644
--- a/include/configs/exynos5-dt-common.h
+++ b/include/configs/exynos5-dt-common.h
@@ -15,7 +15,7 @@
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SYS_SPI_BASE 0x12D30000
+#define CFG_SYS_SPI_BASE 0x12D30000
#define FLASH_SIZE (4 << 20)
#define CONFIG_SPI_BOOTING
diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h
index 68c36dc..8672b9e 100644
--- a/include/configs/exynos78x0-common.h
+++ b/include/configs/exynos78x0-common.h
@@ -18,7 +18,7 @@
#define CPU_RELEASE_ADDR secondary_boot_addr
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index f5353ec..89e5316 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -14,8 +14,8 @@
#endif
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
@@ -32,10 +32,10 @@
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000
#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
index a755714..0ba4efe 100644
--- a/include/configs/gardena-smart-gateway-mt7688.h
+++ b/include/configs/gardena-smart-gateway-mt7688.h
@@ -9,14 +9,14 @@
/* RAM */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
@@ -25,7 +25,7 @@
#endif
/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* RAM */
diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
index 6cdfe8c..36dcee8 100644
--- a/include/configs/gazerbeam.h
+++ b/include/configs/gazerbeam.h
@@ -14,7 +14,7 @@
*/
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */
-#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
/*
* Memory test
@@ -28,16 +28,16 @@
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
+#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
@@ -49,7 +49,7 @@
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h
index 85ceaf8..97fe76c 100644
--- a/include/configs/ge_b1x5v2.h
+++ b/include/configs/ge_b1x5v2.h
@@ -38,8 +38,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Command definition */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 1dba2e9..cbaf03c 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -92,11 +92,11 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index fe00272..b855bbc 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -54,8 +54,8 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/*
* MTD Command for mtdparts
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 0d281a3..4aef0b4 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
+#define CFG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_PL011_CLOCK 150000000
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 775f166..c5ef2f9 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -26,7 +26,7 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xf6801000
diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h
index 914c3ad..fad1f98 100644
--- a/include/configs/hikey960.h
+++ b/include/configs/hikey960.h
@@ -18,7 +18,7 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xe82b1000
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h
index fcb2dec..59ea896 100644
--- a/include/configs/hsdk-4xd.h
+++ b/include/configs/hsdk-4xd.h
@@ -21,8 +21,8 @@
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h
index 0ae9352..fbfcded 100644
--- a/include/configs/hsdk.h
+++ b/include/configs/hsdk.h
@@ -20,8 +20,8 @@
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 594aa4f..b0abd54 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -80,7 +80,7 @@
/* CS2 Base address */
#define PHYS_FLASH_1 0xc0000000
/* Flash Base for U-Boot */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* Address and size of Redundant Environment Sector */
/*
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index d4e2583..1f30798 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h
@@ -110,8 +110,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* UART */
#ifdef CONFIG_MXC_UART
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 1b08c5e..4e23f1a 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -106,8 +106,8 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h
index a074df5..402f83c 100644
--- a/include/configs/imx6dl-mamoj.h
+++ b/include/configs/imx6dl-mamoj.h
@@ -56,7 +56,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __IMX6DL_MAMOJ_CONFIG_H */
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
index 855af29..99da081 100644
--- a/include/configs/imx6q-bosch-acc.h
+++ b/include/configs/imx6q-bosch-acc.h
@@ -86,8 +86,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* SPL */
#ifdef CONFIG_SPL
diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h
index 0a688af..2d9d3c3 100644
--- a/include/configs/imx6ulz_smm_m2.h
+++ b/include/configs/imx6ulz_smm_m2.h
@@ -64,8 +64,8 @@
#define PHYS_SDRAM_SIZE SZ_128M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index e5118f1..76771fd 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -70,8 +70,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Config*/
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index e62f9c5..c228cf7 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -11,7 +11,7 @@
#include <asm/arch/imx-regs.h>
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -123,8 +123,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 143da00..03325e6 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -71,8 +71,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index c766930..80321cf 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -18,8 +18,8 @@
#endif
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 9937071..8a694c8 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -15,10 +15,10 @@
#define UBOOT_ITB_OFFSET_FSPI \
(UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE)
#ifdef CONFIG_FSPI_CONF_HEADER
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI)
#else
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#endif
@@ -53,8 +53,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index cd47d84..41ab930 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -10,7 +10,7 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -38,8 +38,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 58e165c..28ce834 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -29,8 +29,8 @@
"splblk=0x42\0" \
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index f532c10..85fd5e2 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Initial environment variables */
@@ -75,8 +75,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h
index 415248e..204fc4b 100644
--- a/include/configs/imx8mn_bsh_smm_s2_common.h
+++ b/include/configs/imx8mn_bsh_smm_s2_common.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define MEM_LAYOUT_ENV_SETTINGS \
@@ -23,8 +23,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 8857bc7..024b86c 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define BOOT_TARGET_DEVICES(func) \
@@ -45,8 +45,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index 628bb58..4633843 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define BOOT_TARGET_DEVICES(func) \
@@ -43,8 +43,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index a169be3..a585cbf 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Enable Distro Boot */
@@ -23,8 +23,8 @@
"splblk=0x40\0" \
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
index 62bcef5..5443022 100644
--- a/include/configs/imx8mp_dhcom_pdk2.h
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -11,8 +11,8 @@
#include <asm/arch/imx-regs.h>
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index d394762..738677f 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
@@ -50,8 +50,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */
diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h
index 3e995c9..d67bad8 100644
--- a/include/configs/imx8mp_icore_mx8mp.h
+++ b/include/configs/imx8mp_icore_mx8mp.h
@@ -11,7 +11,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
@@ -52,8 +52,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index 1943a24..58f7dc6 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* GUIDs for capsule updatable firmware images */
#define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
@@ -131,8 +131,8 @@
"fi;\0"
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 6GB or 4G DDR */
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index 7d36058..e79aa57 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Enable Distro Boot */
@@ -23,8 +23,8 @@
"splblk=0x40\0" \
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index 271376c..4df98e3 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h
@@ -46,8 +46,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 672a9fa..aa29e78 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -52,8 +52,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index dd354b0..3b4cd65 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h
@@ -84,8 +84,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h
index fe27ac3..2e2e5ed 100644
--- a/include/configs/imx8qm_rom7720.h
+++ b/include/configs/imx8qm_rom7720.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index 592df27..d313bdc 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_MALLOC_F_ADDR 0x22040000
@@ -50,8 +50,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x80000000
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index 077a4d8..895c50f 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -124,8 +124,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h
index a2c0048..e180387 100644
--- a/include/configs/imxrt1020-evk.h
+++ b/include/configs/imxrt1020-evk.h
@@ -22,6 +22,6 @@
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_UBOOT_START 0x800023FD
+#define CFG_SYS_UBOOT_START 0x800023FD
#endif /* __IMXRT1020_EVK_H */
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index d1a7dab..8422867 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -29,6 +29,6 @@
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_UBOOT_START 0x800023FD
+#define CFG_SYS_UBOOT_START 0x800023FD
#endif /* __IMXRT1050_EVK_H */
diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h
index 2459fe2..f834290 100644
--- a/include/configs/imxrt1170-evk.h
+++ b/include/configs/imxrt1170-evk.h
@@ -23,7 +23,7 @@
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)
/* For SPL */
-#define CONFIG_SYS_UBOOT_START 0x202403FD
+#define CFG_SYS_UBOOT_START 0x202403FD
/* For SPL ends */
#endif /* __IMXRT1170_EVK_H */
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 8d0458d..7a55c6a 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -6,7 +6,7 @@
* Common ARM Integrator configuration settings
*/
-#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
+#define CFG_SYS_TIMERBASE 0x13000100 /* Timer1 */
/*
* The ARM boot monitor initializes the board.
@@ -41,6 +41,6 @@
* - SIB block
* - U-Boot environment
*/
-#define CONFIG_SYS_FLASH_BASE 0x24000000
+#define CFG_SYS_FLASH_BASE 0x24000000
/* Timeout values in ticks */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index c8457d9..6bee098 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -17,10 +17,10 @@
#include "integrator-common.h"
/* Integrator/AP-specific configuration */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
+#define CFG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
/* Flash settings */
-#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
+#define CFG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
/*-----------------------------------------------------------------------
* PCI definitions
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index bf09510..25bb41e 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -17,7 +17,7 @@
#include "integrator-common.h"
/* Integrator CP-specific configuration */
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
#define CONFIG_SERVERIP 192.168.1.100
#define CONFIG_IPADDR 192.168.1.104
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 2a0b0c7..e66f994 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -18,14 +18,14 @@
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* FLASH Configuration */
-#define CONFIG_SYS_FLASH_BASE 0x000000000
+#define CFG_SYS_FLASH_BASE 0x000000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-#define CONFIG_SYS_UBOOT_BASE 0x50280000
+#define CFG_SYS_UBOOT_BASE 0x50280000
/* Image load address in RAM for DFU boot*/
#else
-#define CONFIG_SYS_UBOOT_BASE 0x50080000
+#define CFG_SYS_UBOOT_BASE 0x50080000
#endif
/* HyperFlash related configuration */
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index e690ef9..ab204c6 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -21,10 +21,10 @@
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-#define CONFIG_SYS_UBOOT_BASE 0x50280000
+#define CFG_SYS_UBOOT_BASE 0x50280000
/* Image load address in RAM for DFU boot*/
#else
-#define CONFIG_SYS_UBOOT_BASE 0x50080000
+#define CFG_SYS_UBOOT_BASE 0x50080000
#endif
/* U-Boot general configuration */
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 35cf27a..cc5ec21 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -13,7 +13,7 @@
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h
index 888bb29..f64c0ee 100644
--- a/include/configs/km/km-mpc832x.h
+++ b/include/configs/km/km-mpc832x.h
@@ -1,34 +1,34 @@
/*
* System IO Config
*/
-#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
+#define CFG_SYS_SICRL SICRL_IRQ_CKS
-#define CONFIG_SYS_DDRCDR (\
+#define CFG_SYS_DDRCDR (\
DDRCDR_EN | \
DDRCDR_PZ_MAXZ | \
DDRCDR_NZ_MAXZ | \
DDRCDR_M_ODR)
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+#define CFG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_32_BE | \
SDRAM_CFG_SREN | \
SDRAM_CFG_HSE)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ODT_WR_CFG | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_MODE 0x47860242
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
+#define CFG_SYS_DDR_MODE 0x47860242
+#define CFG_SYS_DDR_MODE2 0x8080c000
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
@@ -37,7 +37,7 @@
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
+#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(3 << TIMING_CFG1_WRREC_SHIFT) | \
@@ -46,7 +46,7 @@
(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
@@ -54,7 +54,7 @@
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(5 << TIMING_CFG2_CPO_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CFG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CFG_SYS_KMBEC_FPGA_SIZE 128
diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h
index fb43fb8..5c9f912 100644
--- a/include/configs/km/km-mpc8360.h
+++ b/include/configs/km/km-mpc8360.h
@@ -1,6 +1,6 @@
/* KMBEC FPGA (PRIO) */
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
+#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CFG_SYS_KMBEC_FPGA_SIZE 64
/*
* High Level Configuration Options
@@ -9,34 +9,34 @@
/*
* System IO Setup
*/
-#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
+#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
/**
* DDR RAM settings
*/
-#define CONFIG_SYS_DDR_SDRAM_CFG (\
+#define CFG_SYS_DDR_SDRAM_CFG (\
SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_SREN | \
SDRAM_CFG_HSE)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (\
+#define CFG_SYS_DDR_CLK_CNTL (\
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL (\
+#define CFG_SYS_DDR_INTERVAL (\
(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CFG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDRCDR (\
+#define CFG_SYS_DDRCDR (\
DDRCDR_EN | \
DDRCDR_Q_DRN)
-#define CONFIG_SYS_DDR_MODE 0x47860452
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
+#define CFG_SYS_DDR_MODE 0x47860452
+#define CFG_SYS_DDR_MODE2 0x8080c000
-#define CONFIG_SYS_DDR_TIMING_0 (\
+#define CFG_SYS_DDR_TIMING_0 (\
(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
@@ -46,7 +46,7 @@
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
+#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(3 << TIMING_CFG1_WRREC_SHIFT) | \
@@ -55,7 +55,7 @@
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_2 (\
+#define CFG_SYS_DDR_TIMING_2 (\
(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
@@ -64,11 +64,11 @@
(5 << TIMING_CFG2_CPO_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CFG_SYS_DDR_TIMING_3 0x00000000
/* EEprom support */
/*
* PAXE on the local bus CS3
*/
-#define CONFIG_SYS_PAXE_BASE 0xA0000000
+#define CFG_SYS_PAXE_BASE 0xA0000000
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index db1daee..e6a3613 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -9,7 +9,7 @@
*/
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
@@ -22,15 +22,15 @@
/*
* The reserved memory
*/
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
+#define CFG_SYS_FLASH_BASE 0xF0000000
/* Reserve 768 kB for Mon */
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
/*
* Init Local Bus Memory Controller:
*
@@ -44,21 +44,21 @@
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
+#define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/* I2C */
#define CFG_SYS_NUM_I2C_BUSES 4
-#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
+#define CFG_SYS_I2C_MAX_HOPS 1
+#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
{1, {I2C_NULL_HOP} } }
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
-#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
+#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE
#endif
/*
@@ -66,7 +66,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/*
* Environment
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index b5913ed..7307c49 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -9,8 +9,8 @@
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
CONFIG_KM_PHRAM + \
@@ -19,24 +19,24 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
/* POST memory regions test */
-#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
/*
* IFC Definitions
*/
/* NOR Flash Definitions */
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_TE | \
CSPR_MSEL_NOR | \
@@ -63,18 +63,18 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
#define CFG_SYS_NAND_BASE 0x68000000
@@ -110,40 +110,40 @@
FTIM2_NAND_TWHRE(0x3c))
#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */
-#define CONFIG_SYS_QRIO_BASE 0x70000000
-#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
+#define CFG_SYS_QRIO_BASE 0x70000000
+#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE
-#define CONFIG_SYS_CSPR2_EXT (0x00)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define CFG_SYS_CSPR2_EXT (0x00)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_20 | \
CSOR_GPCM_BCTLD)
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
FTIM0_GPCM_TEADC(0x8) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x6))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x7))
-#define CONFIG_SYS_CS2_FTIM3 0x04000000
+#define CFG_SYS_CS2_FTIM3 0x04000000
/*
* Serial Port
@@ -155,11 +155,11 @@
*/
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CFG_SYS_I2C_MAX_HOPS 1
#define CFG_SYS_NUM_I2C_BUSES 3
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x0
-#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+#define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{1, {I2C_NULL_HOP} }, \
}
@@ -205,12 +205,12 @@
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
- "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "erase " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
- __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
"set_fdthigh=true\0" \
@@ -238,6 +238,6 @@
"ethrotate=no\0" \
""
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
#endif
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index dbf038c..e152714 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -25,10 +25,10 @@
#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
/* Application IFC CS4 MRAM */
-#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
+#define CFG_SYS_MRAM_BASE SYS_LAWAPP_BASE
#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
#define SYS_MRAM_CSPR_EXT (0x0f)
-#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \
CSPR_PORT_SIZE_8 | /* 8 bit */ \
CSPR_MSEL_GPCM | /* msel = gpcm */ \
CSPR_V /* bank is valid */)
@@ -44,14 +44,14 @@
FTIM2_GPCM_TCH(0x2) | \
FTIM2_GPCM_TWP(0x8))
#define SYS_MRAM_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
-#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
-#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
-#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
-#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
-#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
-#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
-#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
+#define CFG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
+#define CFG_SYS_CSPR4 SYS_MRAM_CSPR
+#define CFG_SYS_AMASK4 SYS_MRAM_AMASK
+#define CFG_SYS_CSOR4 SYS_MRAM_CSOR
+#define CFG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
+#define CFG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
+#define CFG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
+#define CFG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
/* Application IFC CS6: BFTIC */
#define SYS_BFTIC_BASE 0xd0000000
@@ -73,20 +73,20 @@
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define SYS_BFTIC_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
-#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
-#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
-#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
-#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
-#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
-#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
-#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
+#define CFG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
+#define CFG_SYS_CSPR6 SYS_BFTIC_CSPR
+#define CFG_SYS_AMASK6 SYS_BFTIC_AMASK
+#define CFG_SYS_CSOR6 SYS_BFTIC_CSOR
+#define CFG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
+#define CFG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
+#define CFG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
+#define CFG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
/* Application IFC CS7 PAXE */
-#define CONFIG_SYS_PAXE_BASE 0xd8000000
-#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define CFG_SYS_PAXE_BASE 0xd8000000
+#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CFG_SYS_PAXE_BASE)
#define SYS_PAXE_CSPR_EXT (0x0f)
-#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \
CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
CSPR_MSEL_GPCM | /* MSEL = GPCM */\
CSPR_V) /* valid */
@@ -102,14 +102,14 @@
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define SYS_PAXE_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
-#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
-#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
-#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
-#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
-#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
-#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
-#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
+#define CFG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
+#define CFG_SYS_CSPR7 SYS_PAXE_CSPR
+#define CFG_SYS_AMASK7 SYS_PAXE_AMASK
+#define CFG_SYS_CSOR7 SYS_PAXE_CSOR
+#define CFG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
+#define CFG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
+#define CFG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
+#define CFG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
/* PRST */
#define KM_BFTIC4_RST 0
@@ -145,25 +145,25 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
/* POST memory regions test */
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
@@ -189,12 +189,12 @@
* IFC Definitions
*/
/* NOR flash on IFC CS0 */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
- CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
+ CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR_CSPR_EXT (0x0f)
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_NOR | /* MSEL = NOR */\
@@ -217,18 +217,18 @@
FTIM2_NOR_TWPH(0x6))
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* More NOR Flash params */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC CS1*/
#define CFG_SYS_NAND_BASE 0xfa000000
@@ -266,23 +266,23 @@
FTIM2_NAND_TWHRE(0x3c))
#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
/* More NAND Flash Params */
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO on IFC CS2 */
-#define CONFIG_SYS_QRIO_BASE 0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define CFG_SYS_QRIO_BASE 0xfb000000
+#define CFG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CFG_SYS_QRIO_BASE)
#define SYS_QRIO_CSPR_EXT (0x0f)
-#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_GPCM | /* MSEL = GPCM */\
@@ -300,28 +300,28 @@
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x7))
#define SYS_QRIO_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
-#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
-#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
-#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
-#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
+#define CFG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
+#define CFG_SYS_CSPR2 SYS_QRIO_CSPR
+#define CFG_SYS_AMASK2 SYS_QRIO_AMASK
+#define CFG_SYS_CSOR2 SYS_QRIO_CSOR
+#define CFG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
+#define CFG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
+#define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
+#define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port - controlled on board with jumper J8
@@ -331,7 +331,7 @@
*/
#if !defined(CONFIG_DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500)
#endif
#ifndef __ASSEMBLY__
@@ -351,30 +351,30 @@
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
/* Qman / Bman */
/* RGMII (FM1@DTESC5) is local managemant interface */
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
+#define CFG_SYS_RGMII2_PHY_ADDR 0x11
/*
* Hardware Watchdog
@@ -387,7 +387,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
@@ -412,12 +412,12 @@
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
- "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "erase " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
- __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
"set_fdthigh=true\0" \
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index b954029..2be996a 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -12,7 +12,7 @@
#define CONFIG_NAND_ECC_BCH
#define CONFIG_NAND_KMETER1
#define NAND_MAX_CHIPS 1
-#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
@@ -26,7 +26,7 @@
/**
* KMCOGE5NE has 512 MB RAM
*/
-#define CONFIG_SYS_DDR_CS0_CONFIG (\
+#define CFG_SYS_DDR_CS0_CONFIG (\
CSCONFIG_EN | \
CSCONFIG_AP | \
CSCONFIG_ODT_WR_ONLY_CURRENT | \
@@ -35,7 +35,7 @@
CSCONFIG_COL_BIT_10)
/* enable POST tests */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 4245875..910fc1b 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -16,7 +16,7 @@
#include "km/km-mpc83xx.h"
#include "km/km-mpc8360.h"
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | \
CSCONFIG_ODT_WR_ONLY_CURRENT)
diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h
index e2808ec..6fcacdb 100644
--- a/include/configs/kontron-sl-mx6ul.h
+++ b/include/configs/kontron-sl-mx6ul.h
@@ -16,10 +16,10 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Board and environment settings */
#define CONFIG_MXC_UART_BASE UART4_BASE
diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h
index 73b5951..80a3230 100644
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -19,8 +19,8 @@
#define PHYS_SDRAM_SIZE (SZ_4G)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
/* Board and environment settings */
#define CONFIG_HOSTNAME "kontron-mx8mm"
diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index 9b45281..2abcb84 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h
@@ -61,8 +61,8 @@
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index bbf0761..9c3174d 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -12,17 +12,17 @@
/* we don't have secure memory unless we have a BL31 */
#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
-#undef CONFIG_SYS_MEM_RESERVE_SECURE
+#undef CFG_SYS_MEM_RESERVE_SECURE
#endif
/* DDR */
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* early stack pointer */
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index 967de66..c551585 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -68,8 +68,8 @@
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* environment organization */
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index de1fc0b..136e228 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -87,8 +87,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment */
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 9b70eed..828f910 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -31,7 +31,7 @@
#ifdef CONFIG_CMD_I2C
/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
#if defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_I2C_G762_ADDR 0x3e
+#define CFG_SYS_I2C_G762_ADDR 0x3e
#endif
#endif /* CONFIG_CMD_I2C */
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index bee064c..2664982 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -17,10 +17,10 @@
/*
* SoC Configuration
*/
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_OSCIN_FREQ 24000000
+#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/*
* Memory Info
@@ -38,7 +38,7 @@
*/
#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
+#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
/*
* U-Boot general configuration
diff --git a/include/configs/librem5.h b/include/configs/librem5.h
index 3a2c508..11b3fa6 100644
--- a/include/configs/librem5.h
+++ b/include/configs/librem5.h
@@ -79,8 +79,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
index b913450..f16c7e9 100644
--- a/include/configs/linkit-smart-7688.h
+++ b/include/configs/linkit-smart-7688.h
@@ -9,14 +9,14 @@
/* RAM */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
@@ -26,7 +26,7 @@
#endif
/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* RAM */
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index d1ebd99..721da81 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -88,8 +88,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* FLASH and environment organization */
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 0712437..7598e54 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -10,10 +10,10 @@
#include <asm/arch/stream_id_lsch2.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */
#define CFG_SYS_FSL_QSPI_BASE 0x40000000
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 54555b3..e772c01 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -17,7 +17,7 @@
*/
#ifdef CONFIG_FSL_QIXIS
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_BRDCFG_REG 0x04
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x08
@@ -47,7 +47,7 @@
* RTC configuration
*/
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* Voltage monitor on channel 2*/
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 49a77fd..b058308 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -7,8 +7,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
* DDR: 800 MHz ( 1600 MT/s data rate )
@@ -41,8 +41,8 @@
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* Serial Port
@@ -104,7 +104,7 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 1f5a80f..5494b71 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -7,8 +7,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifdef CONFIG_NAND_BOOT
#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10)
@@ -19,8 +19,8 @@
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -30,16 +30,16 @@
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT (0x0)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
@@ -61,10 +61,10 @@
#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
- CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
+ CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/*
* NAND Flash Definitions
@@ -111,7 +111,7 @@
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
@@ -131,96 +131,96 @@
#define QIXIS_PWR_CTL2 0x21
#define QIXIS_PWR_CTL2_PCTL 0x2
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/*
* QIXIS Timing parameters for IFC GPCM
*/
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
FTIM0_GPCM_TEADC(0xe) | \
FTIM0_GPCM_TEAHC(0xe))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
FTIM2_GPCM_TCH(0xe) | \
FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_FPGA_FTIM3 0x0
#endif
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#endif
/*
@@ -296,7 +296,7 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index 4954606..bc9eac7 100644
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h
@@ -6,8 +6,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/* XHCI Support - enabled by default */
@@ -56,8 +56,8 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Serial Port */
#define CFG_SYS_NS16550_CLK get_serial_clock()
@@ -141,7 +141,7 @@
"bootm $load_addr#$board\0"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index d772249..f1ccb5f 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -7,8 +7,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
@@ -59,18 +59,18 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -94,52 +94,52 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif
/* CPLD */
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
FTIM0_GPCM_TEADC(0xf) | \
FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3
/*
* Serial Port
@@ -298,7 +298,7 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 064c4f0..bdd3951 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -13,10 +13,10 @@
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/*
* SMP Definitinos
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index 2539115..228fb12 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -17,7 +17,7 @@
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 1
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 5
@@ -35,19 +35,19 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
#endif
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 1
+#define CFG_SYS_RTC_BUS_NUM 1
#define I2C_MUX_CH_RTC 0xB
/* Store environment at top of flash */
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
index e7b2543..5c13461 100644
--- a/include/configs/ls1028ardb.h
+++ b/include/configs/ls1028ardb.h
@@ -10,7 +10,7 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_RTC_BUS_NUM 0
/* Store environment at top of flash */
@@ -21,7 +21,7 @@
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_LBMAP_MASK 0xe0
#define QIXIS_LBMAP_SHIFT 0x5
@@ -39,12 +39,12 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
#endif
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e940dff..b404874 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -32,10 +32,10 @@
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
@@ -82,14 +82,14 @@
#if defined(CONFIG_TFABOOT) || \
(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
/*
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x60000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -104,7 +104,7 @@
/* FMan ucode */
#ifndef SPL_NO_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CFG_SYS_FM_MURAM_SIZE 0x60000
#endif
#endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 87751f7..dab5738 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -39,13 +39,13 @@
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT (0x0)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
@@ -66,10 +66,10 @@
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
- CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
+ CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/*
* NAND Flash Definitions
@@ -125,7 +125,7 @@
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
@@ -143,130 +143,130 @@
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/*
* QIXIS Timing parameters for IFC GPCM
*/
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
FTIM0_GPCM_TEADC(0x20) | \
FTIM0_GPCM_TEAHC(0x10))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_FPGA_FTIM3 0x0
#endif
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#endif
#endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 76251fd..12c4853 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -21,7 +21,7 @@
#define CFG_SYS_NOR_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -41,11 +41,11 @@
FTIM2_NOR_TWPH(0x8) | \
FTIM2_NOR_TWP(0x10))
#define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/*
* NAND Flash Definitions
@@ -91,97 +91,97 @@
/*
* CPLD
*/
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
-#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_CPLD_CSPR_EXT (0x0)
+#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
+#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
FTIM0_GPCM_TEADC(0xf) | \
FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_CPLD_FTIM3 0x0
+#define CFG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
/*
* Environment
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index ce254d8..cac30e4 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -32,10 +32,10 @@
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
@@ -68,7 +68,7 @@
/* FMan ucode */
#ifndef SPL_NO_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CFG_SYS_FM_MURAM_SIZE 0x60000
#endif
#endif
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 8402eac..58ae0fb 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -8,7 +8,7 @@
#include "ls1046a_common.h"
-#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CFG_SYS_UBOOT_BASE 0x40100000
/*
* NAND Flash Definitions
@@ -48,14 +48,14 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
/* EEPROM */
#define I2C_RETIMER_ADDR 0x18
@@ -67,8 +67,8 @@
/* RTC */
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
+#define CFG_SYS_RTC_BUS_NUM 0
/*
* Environment
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index d565492..553ae84 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -33,14 +33,14 @@
/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
/*
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x60000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -58,13 +58,13 @@
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT (0x0)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
@@ -86,10 +86,10 @@
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
- CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
+ CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/*
* NAND Flash Definitions
@@ -145,7 +145,7 @@
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
@@ -163,130 +163,130 @@
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/*
* QIXIS Timing parameters for IFC GPCM
*/
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
FTIM0_GPCM_TEADC(0x20) | \
FTIM0_GPCM_TEAHC(0x10))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_FPGA_FTIM3 0x0
#endif
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#endif
#endif
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 0df6891..f3904e7 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -16,7 +16,7 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CFG_SYS_UBOOT_BASE 0x40100000
#endif
#define CFG_SYS_NAND_BASE 0x7e800000
@@ -55,46 +55,46 @@
/*
* CPLD
*/
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
-#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_CPLD_CSPR_EXT (0x0)
+#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
+#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CPLD_FTIM3 0x0
+#define CFG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
/* EEPROM */
#define I2C_RETIMER_ADDR 0x18
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index f8eaee8..bacc84f 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -30,10 +30,10 @@
#define CFG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
* SMP Definitinos
*/
@@ -64,18 +64,18 @@
* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
*
* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x30000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x580000000ULL
+#define CFG_SYS_FLASH_BASE_PHYS 0x80000000
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
+#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
+#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
@@ -92,12 +92,12 @@
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
+#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/*
* Carve out a DDR region which will not be used by u-boot/Linux
@@ -107,7 +107,7 @@
*/
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Miscellaneous configurable options */
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index b75d4cc..d84622f 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -22,27 +22,27 @@
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR1_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -59,13 +59,13 @@
FTIM2_NOR_TWPH(0xe) | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
+ CFG_SYS_FLASH_BASE + 0x40000000}
#endif
#endif
@@ -101,7 +101,7 @@
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_QMAP_SHIFT 5
@@ -127,8 +127,8 @@
#define QIXIS_SDID_MASK 0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
@@ -139,9 +139,9 @@
#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
+#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
#else
-#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
#endif
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
@@ -155,102 +155,102 @@
#define SYS_FPGA_CS_FTIM3 0x0
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3 SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK2 SYS_FPGA_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3 SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#endif
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* I2C bus multiplexer
@@ -281,7 +281,7 @@
* RTC configuration
*/
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#ifdef CONFIG_FSL_DSPI
#if !defined(CONFIG_TFABOOT) && \
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 27510ad..187b307 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -20,17 +20,17 @@
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -44,12 +44,12 @@
FTIM2_NOR_TCH(0x0) | \
FTIM2_NOR_TWP(0x1))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
#endif
@@ -85,7 +85,7 @@
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_BRDCFG4_OFFSET 0x54
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_QMAP_MASK 0xe0
@@ -107,8 +107,8 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
@@ -117,8 +117,8 @@
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
@@ -132,36 +132,36 @@
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define I2C_MUX_CH_VOL_MONITOR 0xA
/* Voltage monitor on channel 2*/
@@ -191,7 +191,7 @@
* RTC configuration
*/
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#endif
#ifndef SPL_NO_ENV
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 21c097e..18defd5 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -17,10 +17,10 @@
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
* SMP Definitinos
@@ -56,18 +56,18 @@
* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
*
* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x30000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x580000000ULL
+#define CFG_SYS_FLASH_BASE_PHYS 0x80000000
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
+#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
+#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
@@ -84,13 +84,13 @@
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
/* For LS2085A */
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
+#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/*
* Carve out a DDR region which will not be used by u-boot/Linux
@@ -99,7 +99,7 @@
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Miscellaneous configurable options */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 7315790..067587b 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -10,10 +10,10 @@
#include "ls2080a_common.h"
#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
+#define CFG_SYS_I2C_IFDR_DIV 0x7e
#endif
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -25,27 +25,27 @@
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR1_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -61,13 +61,13 @@
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
+ CFG_SYS_FLASH_BASE + 0x40000000}
#endif
#define CFG_SYS_NAND_CSPR_EXT (0x0)
@@ -119,92 +119,92 @@
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_CSPR3_EXT (0x0)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_CSPR3_EXT (0x0)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL)
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#endif
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* I2C
@@ -229,7 +229,7 @@
*/
#define RTC
#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index daca3be..32a1194 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -32,17 +32,17 @@
#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -58,13 +58,13 @@
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
+ CFG_SYS_FLASH_BASE + 0x40000000}
#endif
#define CFG_SYS_NAND_CSPR_EXT (0x0)
@@ -113,70 +113,70 @@
#define QIXIS_RCW_SRC_NAND 0x119
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_CSPR3_EXT (0x0)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_CSPR3_EXT (0x0)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#ifdef CONFIG_TARGET_LS2081ARDB
#define QIXIS_QMAP_MASK 0x07
@@ -197,7 +197,7 @@
* I2C
*/
#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#endif
#define I2C_MUX_PCA_ADDR 0x75
#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
@@ -212,10 +212,10 @@
*/
#define RTC
#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+#define CFG_SYS_I2C_RTC_ADDR 0x51
#else
#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index ad85e2d..bbee9df 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -10,15 +10,15 @@
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
-#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CFG_SYS_FLASH_BASE 0x20000000
/* DDR */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CFG_SYS_SDRAM_SIZE 0x200000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
@@ -42,22 +42,22 @@
/* Serial Port */
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
-#define CONFIG_SYS_SERIAL0 0x21c0000
-#define CONFIG_SYS_SERIAL1 0x21d0000
-#define CONFIG_SYS_SERIAL2 0x21e0000
-#define CONFIG_SYS_SERIAL3 0x21f0000
+#define CFG_SYS_SERIAL0 0x21c0000
+#define CFG_SYS_SERIAL1 0x21d0000
+#define CFG_SYS_SERIAL2 0x21e0000
+#define CFG_SYS_SERIAL3 0x21f0000
/*below might needs to be removed*/
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1, \
- (void *)CONFIG_SYS_SERIAL2, \
- (void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
+ (void *)CFG_SYS_SERIAL1, \
+ (void *)CFG_SYS_SERIAL2, \
+ (void *)CFG_SYS_SERIAL3 }
/* MC firmware */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* Carve out a DDR region which will not be used by u-boot/Linux
@@ -66,7 +66,7 @@
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
#endif
/* I2C bus multiplexer */
@@ -75,10 +75,10 @@
/* RTC */
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* Qixis */
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
/* USB */
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 4e8a904..9f89106 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -9,7 +9,7 @@
#include "lx2160a_common.h"
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_RTC_BUS_NUM 0
/* MAC/PHY configuration */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index bb9239c..58c0ff3 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -9,7 +9,7 @@
#include "lx2160a_common.h"
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 4
+#define CFG_SYS_RTC_BUS_NUM 4
/* EMC2305 */
#define I2C_MUX_CH_EMC2305 0x09
diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
index b70abb0..157688e 100644
--- a/include/configs/lx2162aqds.h
+++ b/include/configs/lx2162aqds.h
@@ -11,7 +11,7 @@
/* USB */
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_RTC_BUS_NUM 0
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index cbdb2fa..f87bbf7 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -21,8 +21,8 @@
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/*
* U-Boot general configurations
@@ -58,13 +58,13 @@
#define CONFIG_FEC_MXC_PHYADDR 0x0
#endif
-#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
+#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */
/*
* RTC
*/
#ifdef CONFIG_CMD_DATE
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
/*
@@ -77,7 +77,7 @@
#endif
/* LVDS display */
-#define CONFIG_SYS_LDB_CLOCK 33260000
+#define CFG_SYS_LDB_CLOCK 33260000
#define CONFIG_IMX_VIDEO_SKIP
/* IIM Fuses */
diff --git a/include/configs/malta.h b/include/configs/malta.h
index c9aee00..65f4b05 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -28,7 +28,7 @@
#endif
#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/*
* Serial driver
@@ -38,9 +38,9 @@
* Flash configuration
*/
#ifdef CONFIG_64BIT
-# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
+# define CFG_SYS_FLASH_BASE 0xffffffffbe000000
#else
-# define CONFIG_SYS_FLASH_BASE 0xbe000000
+# define CFG_SYS_FLASH_BASE 0xbe000000
#endif
/*
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 8aa3b0c..7c401a2 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -9,7 +9,7 @@
#include "mx6_common.h"
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
+#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + 0x80000)
/*
* Below defines are set but NOT really used since we by
@@ -24,12 +24,12 @@
#define CFG_SYS_FSL_ESDHC_ADDR 0
/* NOR 16-bit mode */
-#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#define CONFIG_FLASH_VERIFY
/* NOR Flash MTD */
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
+#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
+#define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* Ethernet Configuration */
#define CONFIG_FEC_MXC_PHYADDR 1
@@ -116,7 +116,7 @@
"nor_img_addr=0x11000000\0" \
"nor_img_file=core-image-lwn-mccmon6.nor\0" \
"emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
- "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
+ "nor_bank_start=" __stringify(CFG_SYS_FLASH_BASE) "\0" \
"nor_img_size=0x02000000\0" \
"factory_script_file=factory.scr\0" \
"factory_load_script=" \
@@ -215,8 +215,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h
index 2422cbf..9e480fe 100644
--- a/include/configs/meerkat96.h
+++ b/include/configs/meerkat96.h
@@ -18,8 +18,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment configs */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 2e07886..d190e4b 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -28,8 +28,8 @@
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
+#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
/* Misc CPU related */
@@ -47,8 +47,8 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 139b5bc..edd2466 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -13,7 +13,7 @@
/* uart */
/* The following table includes the supported baudrates */
-# define CONFIG_SYS_BAUDRATE_TABLE \
+# define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CONFIG_HOSTNAME "microblaze-generic"
@@ -95,6 +95,6 @@
/* SPL part */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
#endif /* __CONFIG_H */
diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h
index ac5ff92..cfe926c 100644
--- a/include/configs/msc_sm2s_imx8mp.h
+++ b/include/configs/msc_sm2s_imx8mp.h
@@ -14,7 +14,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
@@ -46,8 +46,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h
index 65cd6f5..d5bd492 100644
--- a/include/configs/mt7620.h
+++ b/include/configs/mt7620.h
@@ -10,13 +10,13 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7620_H */
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h
index 1211bb4..7c8c67f 100644
--- a/include/configs/mt7621.h
+++ b/include/configs/mt7621.h
@@ -13,7 +13,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x1c000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x800000
+#define CFG_SYS_INIT_SP_OFFSET 0x800000
/* MMC */
#define MMC_SUPPORTS_TUNING
@@ -27,10 +27,10 @@
#endif
/* Serial common */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7621_H */
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
index e5d60e1..8c29726 100644
--- a/include/configs/mt7622.h
+++ b/include/configs/mt7622.h
@@ -10,10 +10,10 @@
#define __MT7622_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
index 9c5034f..9df2715 100644
--- a/include/configs/mt7628.h
+++ b/include/configs/mt7628.h
@@ -10,7 +10,7 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
+#define CFG_SYS_INIT_SP_OFFSET 0x80000
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
@@ -19,14 +19,14 @@
#endif
/* Serial common */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7628_H */
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
index d330adb..bfa44aa 100644
--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h
@@ -18,7 +18,7 @@
/* Defines for SPL */
#define CONFIG_SPI_ADDR 0x30000000
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
/* SPL -> Uboot */
diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h
index 249f0b9..14c885e 100644
--- a/include/configs/mt7981.h
+++ b/include/configs/mt7981.h
@@ -10,10 +10,10 @@
#define __MT7981_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h
index 990e411..0c41af1 100644
--- a/include/configs/mt7986.h
+++ b/include/configs/mt7986.h
@@ -10,10 +10,10 @@
#define __MT7986_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h
index d159416..3a35527 100644
--- a/include/configs/mt8512.h
+++ b/include/configs/mt8512.h
@@ -10,7 +10,7 @@
#define __MT8512_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
#define ENV_BOOT_READ_IMAGE \
"boot_rd_img=mmc dev 0" \
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index e45bfd7..fa275d6 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -32,13 +32,13 @@
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
-#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE)
-#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+#if defined(CONFIG_ARMADA_38X) && !defined(CFG_SYS_BAUDRATE_TABLE)
+#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
921600, 1000000, 1152000, 1500000, \
diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
index 9c4038b..5c96203 100644
--- a/include/configs/mvebu_alleycat-5.h
+++ b/include/configs/mvebu_alleycat-5.h
@@ -11,7 +11,7 @@
/* additions for new ARM relocation support */
#define CFG_SYS_SDRAM_BASE 0x200000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
/* Default Env vars */
@@ -37,6 +37,6 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_SYS_TCLK 325000000
+#define CFG_SYS_TCLK 325000000
#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 7641b56..9bfc48c 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -15,7 +15,7 @@
/* additions for new ARM relocation support */
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
921600, 1000000, 1152000, 1500000, \
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 358e06f..beac3ae 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -9,14 +9,14 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+#define CFG_SYS_TCLK 250000000 /* 250MHz */
/* additions for new ARM relocation support */
#define CFG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
/*
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 2229980..3c99b70 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -113,12 +113,12 @@
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-#define CONFIG_SYS_DDR_CLKSEL 0
-#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
-#define CONFIG_SYS_MAIN_PWR_ON
+#define CFG_SYS_DDR_CLKSEL 0
+#define CFG_SYS_CLKTL_CBCDR 0x59E35100
+#define CFG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* environment organization
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index e84bac6..2bc462c 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -61,8 +61,8 @@
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* environment organization */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 9e837a3..b52e70c 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -24,7 +24,7 @@
/* PMIC Controller */
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
+#define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
@@ -96,8 +96,8 @@
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* Framebuffer and LCD */
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index 52ff7b0..7160654 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -87,7 +87,7 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
@@ -97,8 +97,8 @@
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* FLASH and environment organization */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 4314556..245530a 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -12,7 +12,7 @@
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#else
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
+#define CFG_SYS_PL310_BASE L2_PL310_BASE
#endif
#endif
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 3c4ba09..12741c0 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -86,8 +86,8 @@
/* Physical Memory Map */
#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h
index 9c160c4..f6d3b2e 100644
--- a/include/configs/mx6memcal.h
+++ b/include/configs/mx6memcal.h
@@ -28,8 +28,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 711b5a3..5e95e43 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -140,8 +140,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index 3fdf829..1a2160c 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h
@@ -16,7 +16,7 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
#include "mx6sabre_common.h"
@@ -26,7 +26,7 @@
#endif
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#endif
#define CFG_SYS_FSL_USDHC_NUM 2
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3c2621d..358d9f4 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -83,8 +83,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index a3a12ae..6632e4e 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -83,8 +83,8 @@
#define PHYS_SDRAM_SIZE SZ_2G
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index f0e239f..0dd4056 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -79,8 +79,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index a0f9c53..6f5dffe 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -107,8 +107,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 8199b4b..cb1019b 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -109,8 +109,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 827385c..4154d32 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -103,8 +103,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index c39b357..6c16552 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -82,8 +82,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
index 362de48..85922fa 100644
--- a/include/configs/mx7ulp_com.h
+++ b/include/configs/mx7ulp_com.h
@@ -18,7 +18,7 @@
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
/* UART */
#define LPUART_BASE LPUART4_RBASE
@@ -48,8 +48,8 @@
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi;\0" \
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE SZ_256K
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif /* __CONFIG_H */
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 9ef1eea..99e0189 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -15,7 +15,7 @@
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
/* UART */
#define LPUART_BASE LPUART4_RBASE
@@ -92,7 +92,7 @@
"bootz; " \
"fi;\0" \
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE SZ_256K
#endif /* __CONFIG_H */
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 9d6b3d4..5df080a 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -46,11 +46,11 @@
/* Memory sizes */
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
+#define CFG_SYS_INIT_RAM_ADDR 0x00000000
#if defined(CONFIG_MX23)
-#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE (32 * 1024)
#elif defined(CONFIG_MX28)
-#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE (128 * 1024)
#endif
/* Point initial SP in SRAM so SPL can use it too. */
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index cdd1286..a32fcd5 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -23,8 +23,8 @@
#define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 9d09811..dd7f951 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -91,8 +91,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 9ad4f59..9c364ad 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -47,7 +47,7 @@
*/
#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
/* USB device configuration */
#define CONFIG_USB_DEVICE
@@ -64,7 +64,7 @@
* Board ONENAND Info.
*/
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#define CFG_SYS_ONENAND_BASE ONENAND_MAP
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -150,7 +150,7 @@
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
/*
* Physical Memory Map
@@ -162,8 +162,8 @@
*/
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CFG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CFG_SYS_INIT_RAM_SIZE 0x800
/*
* Attached kernel image
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 8d39d75..6f588f9 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -31,8 +31,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* I2C */
#define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index 080c659..09c4ddb 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h
@@ -24,8 +24,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
diff --git a/include/configs/nsim.h b/include/configs/nsim.h
index b930a53..013a349 100644
--- a/include/configs/nsim.h
+++ b/include/configs/nsim.h
@@ -12,8 +12,8 @@
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_256M
/*
diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h
index 5ac951a..ea1edab 100644
--- a/include/configs/o4-imx6ull-nano.h
+++ b/include/configs/o4-imx6ull-nano.h
@@ -8,8 +8,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#if IS_ENABLED(CONFIG_CMD_USB)
# define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h
index b475354..c0ea9e8 100644
--- a/include/configs/octeon_common.h
+++ b/include/configs/octeon_common.h
@@ -8,10 +8,10 @@
#define __OCTEON_COMMON_H__
#if defined(CONFIG_RAM_OCTEON)
-#define CONFIG_SYS_INIT_SP_OFFSET 0x20180000
+#define CFG_SYS_INIT_SP_OFFSET 0x20180000
#else
/* No DDR init -> run in L2 cache with limited resources */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
+#define CFG_SYS_INIT_SP_OFFSET 0x00180000
#endif
#define CFG_SYS_SDRAM_BASE 0xffffffff80000000
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index ce8ea58..8b00a27 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -14,7 +14,7 @@
#include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x10502000
+#define CFG_SYS_PL310_BASE 0x10502000
#endif
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 0890f51..f4e23bb 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -20,7 +20,7 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CFG_SYS_FLASH_BASE NAND_BASE
#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CFG_SYS_NAND_ECCSIZE 512
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 6eec955..8bb8521 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -25,7 +25,7 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CFG_SYS_FLASH_BASE NAND_BASE
#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CFG_SYS_NAND_ECCSIZE 512
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 10f6ba6..a6b5e55 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -66,8 +66,8 @@
BOOTENV
/* OneNAND config */
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
+#define CFG_SYS_ONENAND_BASE ONENAND_MAP
+#define CFG_SYS_ONENAND_BLOCK_SIZE (128*1024)
/* NAND config */
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 6001037..3895537 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -144,9 +144,9 @@
/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CFG_SYS_FLASH_BASE 0x10000000
#endif
-#define CONFIG_SYS_FLASH_SIZE 0x4000000
+#define CFG_SYS_FLASH_SIZE 0x4000000
#endif /* __CONFIG_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 883cc0b..1634db8 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -37,8 +37,8 @@
/* Required support for the TCA642X GPIO we have on the uEVM */
#define CONFIG_TCA642X
-#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
-#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
+#define CFG_SYS_I2C_TCA642X_ADDR 0x22
/* Enabled commands */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 5b0d87a..788a111 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -17,9 +17,9 @@
/*
* SoC Configuration
*/
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_OSCIN_FREQ 24000000
+#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/*
* Memory Info
@@ -32,7 +32,7 @@
/* memtest will be run on 16MB */
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
@@ -44,17 +44,17 @@
*/
/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
-#define CONFIG_SYS_DA850_PLL0_PLLM 18
-#define CONFIG_SYS_DA850_PLL1_PLLM 21
+#define CFG_SYS_DA850_PLL0_PLLM 18
+#define CFG_SYS_DA850_PLL1_PLLM 21
/*
* DDR2 memory configuration
*/
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+#define CFG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
@@ -64,9 +64,9 @@
(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR ( \
(19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
@@ -76,7 +76,7 @@
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(1 << DV_DDR_SDTMR1_WTR_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
@@ -85,21 +85,21 @@
(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(2 << DV_DDR_SDTMR2_CKE_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492
+#define CFG_SYS_DA850_DDR2_PBBPR 0x30
/*
* Serial Driver info
*/
#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/*
* I2C Configuration
*/
-#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
/*
* Flash & Environment
diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index 53889d6..e42a736 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h
@@ -15,8 +15,8 @@
/* Physical Memory Map */
#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB */
#ifdef CONFIG_USB_EHCI_MX6
diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
index d155e55..c96deda 100644
--- a/include/configs/p1_p2_bootsrc.h
+++ b/include/configs/p1_p2_bootsrc.h
@@ -7,11 +7,11 @@
#include <linux/stringify.h>
-#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR)
-#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required"
+#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CFG_SYS_I2C_PCA9557_ADDR)
+#error "CONFIG_SYS_SPD_BUS_NUM and CFG_SYS_I2C_PCA9557_ADDR are required"
#endif
-#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1
+#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CFG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CFG_SYS_I2C_PCA9557_ADDR 3 msk 1
#define __VAR_CMD(var, cmd) __stringify(var=cmd\0)
#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 14d702e..e8b7527 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -83,19 +83,19 @@
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
+#define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
#else
-#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#endif
#elif defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10)
@@ -118,8 +118,8 @@
*/
#define CONFIG_L2_CACHE
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xffe00000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define SPD_EEPROM_ADDRESS 0x52
@@ -130,40 +130,40 @@
#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
#endif
#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Default settings for DDR3 */
#ifndef CONFIG_TARGET_P2020RDB
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
+#define CFG_SYS_DDR_CS0_BNDS 0x0000003f
+#define CFG_SYS_DDR_CS0_CONFIG 0x80014302
+#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CFG_SYS_DDR_CS1_BNDS 0x0040007f
+#define CFG_SYS_DDR_CS1_CONFIG 0x80014302
+#define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+#define CFG_SYS_DDR_INIT_ADDR 0x00000000
+#define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CFG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
+#define CFG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608
+#define CFG_SYS_DDR_SR_CNTR 0x00000000
+#define CFG_SYS_DDR_RCW_1 0x00000000
+#define CFG_SYS_DDR_RCW_2 0x00000000
+#define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
+#define CFG_SYS_DDR_CONTROL_2 0x04401050
+#define CFG_SYS_DDR_TIMING_4 0x00220001
+#define CFG_SYS_DDR_TIMING_5 0x03402400
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x40461520
-#define CONFIG_SYS_DDR_MODE_2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
+#define CFG_SYS_DDR_TIMING_3 0x00020000
+#define CFG_SYS_DDR_TIMING_0 0x00330004
+#define CFG_SYS_DDR_TIMING_1 0x6f6B4846
+#define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF
+#define CFG_SYS_DDR_CLK_CTRL 0x03000000
+#define CFG_SYS_DDR_MODE_1 0x40461520
+#define CFG_SYS_DDR_MODE_2 0x8000c000
+#define CFG_SYS_DDR_INTERVAL 0x0C300000
#endif
/*
@@ -186,23 +186,23 @@
* Local Bus Definitions
*/
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_FLASH_BASE 0xec000000
+#define CFG_SYS_FLASH_BASE 0xec000000
#else
-#define CONFIG_SYS_FLASH_BASE 0xef000000
+#define CFG_SYS_FLASH_BASE 0xef000000
#endif
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \
| BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* Nand Flash */
@@ -241,42 +241,42 @@
#endif
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_CPLD_BASE 0xffa00000
+#define CFG_SYS_CPLD_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
+#define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
#else
-#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
#endif
/* CPLD config size: 1Mb */
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
-#define CONFIG_SYS_VSC7385_BASE 0xffb00000
+#define CFG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
+#define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
#else
-#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
+#define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE
#endif
/* The size of the VSC7385 firmware image */
@@ -292,18 +292,18 @@
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif /* CONFIG_TPL_BUILD */
#endif
#endif
@@ -315,15 +315,15 @@
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
+#define CFG_SYS_I2C_NOPROBES { {0, 0x29} }
#endif
/*
@@ -331,8 +331,8 @@
*/
#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
+#define CFG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_PCA9557_ADDR 0x18
/* enable read and write access to EEPROM */
@@ -397,7 +397,7 @@
*/
#if defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#endif
@@ -418,7 +418,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
/*
* Environment Configuration
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index 85cedde..2a1660b 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -35,8 +35,8 @@
#define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index f7e36f2..4421e74 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -37,8 +37,8 @@
#define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 586cddf..5c2ff5d 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -119,8 +119,8 @@
#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index cf705dc..3674e4c 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h
@@ -16,8 +16,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define ENV_MMC \
diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h
index e08d941..1b72739 100644
--- a/include/configs/pg-wcom-expu1.h
+++ b/include/configs/pg-wcom-expu1.h
@@ -13,23 +13,23 @@
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* CLIPS FPGA Definitions */
-#define CONFIG_SYS_CSPR3_EXT (0x00)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
+#define CFG_SYS_CSPR3_EXT (0x00)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
-#define CONFIG_SYS_CS3_FTIM3 0x04000000
+#define CFG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define WCOM_CLIPS_RST 0
diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h
index 9a7669c..e4bcae5 100644
--- a/include/configs/pg-wcom-seli8.h
+++ b/include/configs/pg-wcom-seli8.h
@@ -12,23 +12,23 @@
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* PAXK FPGA Definitions */
-#define CONFIG_SYS_CSPR3_EXT (0x00)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
+#define CFG_SYS_CSPR3_EXT (0x00)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
-#define CONFIG_SYS_CS3_FTIM3 0x04000000
+#define CFG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define KM_LIU_RST 0
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index ac68c93..7f73117 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -11,7 +11,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -60,8 +60,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index aedaf80..11a833b 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -10,7 +10,7 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -59,8 +59,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index d9abbbc..3cc2a69 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -18,9 +18,9 @@
* Memory Layout
*/
/* Initial RAM for temporary stack, global data */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_INIT_RAM_ADDR \
- (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
+#define CFG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */
#define CFG_SYS_SDRAM_BASE 0x88000000
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index fc2cab9..9e6c210 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -92,8 +92,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 22b4976..8af8883 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -92,8 +92,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_VIDEO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index f5b9eed..7028264 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -94,8 +94,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* PMIC */
#define CONFIG_POWER_PFUZE3000
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index 91baff9..f9301a5 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h
@@ -63,8 +63,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 3fbddd9..a233fb8 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -22,47 +22,47 @@
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000
/* clocks */
/* CKGR_MOR - enable main osc. */
-#define CONFIG_SYS_MOR_VAL \
+#define CFG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
+#define CFG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
AT91_PMC_PLLXR_OUT(3) | \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
+#define CFG_SYS_PIOC_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
+#define CFG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+#define CFG_SYS_MATRIX_EBICSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+#define CFG_SYS_SDRC_TR_VAL1 0x13C
/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
+#define CFG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
@@ -76,10 +76,10 @@
(1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
@@ -88,37 +88,37 @@
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
+#define CFG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
+#define CFG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+#define CFG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
+#define CFG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | \
AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
+#define CFG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_CR_PROCRST | \
AT91_RSTC_MR_ERSTL(1) | \
AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
+#define CFG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
@@ -139,10 +139,10 @@
/* NOR flash */
#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000
#define CONFIG_EXTRA_ENV_SETTINGS \
"partition=nand0,0\0" \
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index c1f6334..9fd8979 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -22,14 +22,14 @@
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
/* clocks */
-#define CONFIG_SYS_MOR_VAL \
+#define CFG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
+#define CFG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
AT91_PMC_PLLXR_OUT(3) | \
AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
@@ -38,43 +38,43 @@
#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
#else
/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_4)
/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_4)
#endif
/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
+#define CFG_SYS_MATRIX_EBI0CSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 0
+#define CFG_SYS_SDRC_MR_VAL1 0
/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
+#define CFG_SYS_SDRC_TR_VAL1 0x3AA
/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
+#define CFG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
@@ -88,10 +88,10 @@
(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
@@ -100,37 +100,37 @@
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
+#define CFG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
+#define CFG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+#define CFG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
+#define CFG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | \
AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
+#define CFG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_CR_PROCRST | \
AT91_RSTC_MR_ERSTL(1) | \
AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
+#define CFG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
@@ -142,7 +142,7 @@
/* NOR flash, if populated */
#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
@@ -166,7 +166,7 @@
AT91_MATRIX_SCFG_SLOT_CYCLE(255))
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#define CONFIG_EXTRA_ENV_SETTINGS \
"partition=nand0,0\0" \
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 4a0a168..686411e 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -16,8 +16,8 @@
#define __CONFIG_H
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x70000000
@@ -53,9 +53,9 @@
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
diff --git a/include/configs/poleg.h b/include/configs/poleg.h
index 365fdd3..518d7a3 100644
--- a/include/configs/poleg.h
+++ b/include/configs/poleg.h
@@ -7,10 +7,10 @@
#define __CONFIG_POLEG_H
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/
+#define CFG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/
#endif
-#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20)
+#define CFG_SYS_BOOTMAPSZ (0x30 << 20)
#define CFG_SYS_SDRAM_BASE 0x0
/* Default environemnt variables */
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index bee1ef6..2b25c31 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h
@@ -9,8 +9,8 @@
#define __PRESIDIO_ASIC_H
/* Generic Timer Definitions */
-#define CONFIG_SYS_TIMER_RATE 25000000
-#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
+#define CFG_SYS_TIMER_RATE 25000000
+#define CFG_SYS_TIMER_COUNTER 0xf4321008
/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
* does not yet support DT. Thus define it here.
@@ -18,7 +18,7 @@
#define GICD_BASE 0xf7011000
#define GICC_BASE 0xf7012000
-#define CONFIG_SYS_TIMER_BASE 0xf4321000
+#define CFG_SYS_TIMER_BASE 0xf4321000
/* Use external clock source */
#define PRESIDIO_APB_CLK 125000000
@@ -26,11 +26,11 @@
/* Cortina Serial Configuration */
#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
-#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1}
+#define CORTINA_SERIAL_PORTS {(void *)CFG_SYS_SERIAL0, \
+ (void *)CFG_SYS_SERIAL1}
-#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
-#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
+#define CFG_SYS_SERIAL0 PER_UART0_CFG
+#define CFG_SYS_SERIAL1 PER_UART1_CFG
/* SDRAM Bank #1 */
#define DDR_BASE 0x00000000
@@ -58,7 +58,7 @@
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
- #define CFG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
+ #define CFG_SYS_NAND_BASE CFG_SYS_FLASH_BASE
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h
index 58020ae..c41bb34 100644
--- a/include/configs/qcs404-evb.h
+++ b/include/configs/qcs404-evb.h
@@ -11,7 +11,7 @@
#include <linux/sizes.h>
#include <asm/arch/sysmap-qcs404.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index e7c8109..aa9cae0 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -12,39 +12,39 @@
/* Needed to fill the ccsrbar pointer */
/* Virtual address to CCSRBAR */
-#define CONFIG_SYS_CCSRBAR 0xe0000000
+#define CFG_SYS_CCSRBAR 0xe0000000
/* Physical address should be a function call */
#ifndef __ASSEMBLY__
extern unsigned long long get_phys_ccsrbar_addr_early(void);
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
+#define CFG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
+#define CFG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
#endif
/* Virtual address to a temporary map if we need it (max 128MB) */
-#define CONFIG_SYS_TMPVIRT 0xe8000000
+#define CFG_SYS_TMPVIRT 0xe8000000
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_HWCONFIG
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
+#define CFG_SYS_INIT_RAM_ADDR 0x00100000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* RTC */
#define CONFIG_RTC_PT7C4338
@@ -58,7 +58,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index f6ee720..bad74cc 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -10,12 +10,12 @@
#define CFG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+#define CFG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/*
* NOR Flash ( Spantion S29GL256P )
*/
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BASE (0xA0000000)
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif /* __CONFIG_H */
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 606a0a7..a86180e 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -15,14 +15,14 @@
#endif
/* console */
-#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
+#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 }
#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
/* Timer */
#define CONFIG_TMU_TIMER
-#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
+#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
#endif /* __RCAR_GEN2_COMMON_H */
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 5853072..e9cbd25 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -18,7 +18,7 @@
#define GICC_BASE 0xF1020000
/* console */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* PHY needs a longer autoneg timeout */
#define PHY_ANEG_TIMEOUT 20000
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index b4c1972..a4cae69 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -8,7 +8,7 @@
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index fac27a7..3025466 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -8,7 +8,7 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 6889ba5..58ad62a 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -8,7 +8,7 @@
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 4aa7e04..6b55c57 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -9,7 +9,7 @@
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0xff700000
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 2c24944..e354927 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -17,14 +17,14 @@
/* Use SoC timer for AArch32, but architected timer for AArch64 */
#ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER \
+#define CFG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_COUNTER \
(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
#endif
/* Memory layout */
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/*
* The board really has 256M. However, the VC (VideoCore co-processor) shares
* the RAM, and uses a configurable portion at the top. We tell U-Boot that a
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 76836ad..84a5ae6 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -10,10 +10,10 @@
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
+#define CFG_SYS_TIMER_RATE (24 * 1000 * 1000)
/* TIMER1,initialized by ddr initialize code */
-#define CONFIG_SYS_TIMER_BASE 0x10350020
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CFG_SYS_TIMER_BASE 0x10350020
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMER_BASE + 8)
#define CFG_SYS_SDRAM_BASE 0x60000000
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index ed891ab..3d49d52 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -124,6 +124,6 @@
/* FLASH and environment organization */
#define CONFIG_MMC_DEFAULT_DEV 0
-#define CONFIG_SYS_ONENAND_BASE 0xB0000000
+#define CFG_SYS_ONENAND_BASE 0xB0000000
#endif /* __CONFIG_H */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 614d04f..06be9c0 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -87,7 +87,7 @@
"mmcrootpart=3\0" \
"opts=always_resume=1"
-#define CONFIG_SYS_ONENAND_BASE 0x0C000000
+#define CFG_SYS_ONENAND_BASE 0x0C000000
#ifndef __ASSEMBLY__
void universal_spi_scl(int bit);
diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index 41e5254..2e422cd 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h
@@ -14,7 +14,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __SALVATOR_X_H */
diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h
index 75302bf..f44ce90 100644
--- a/include/configs/sam9x60_curiosity.h
+++ b/include/configs/sam9x60_curiosity.h
@@ -10,8 +10,8 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0 /* ignored in arm */
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index 22813d4..27b39eb 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -11,8 +11,8 @@
#define __CONFIG_H__
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0 /* ignored in arm */
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 79f354d..d62146e 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -11,8 +11,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SPL */
diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h
index f826eab..1979cb3 100644
--- a/include/configs/sama5d27_wlsom1_ek.h
+++ b/include/configs/sama5d27_wlsom1_ek.h
@@ -12,8 +12,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h
index 01ed1a3..a072b21 100644
--- a/include/configs/sama5d2_icp.h
+++ b/include/configs/sama5d2_icp.h
@@ -11,8 +11,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h
index 2e3c1ea..bf3c92b 100644
--- a/include/configs/sama5d2_ptc_ek.h
+++ b/include/configs/sama5d2_ptc_ek.h
@@ -12,8 +12,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 3f58928..4f579ad 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -27,7 +27,7 @@
/* NOR flash */
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CFG_SYS_FLASH_BASE 0x10000000
#endif
/* SDRAM */
diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h
index 68fa31f..59f13ed 100644
--- a/include/configs/sama7g5ek.h
+++ b/include/configs/sama7g5ek.h
@@ -9,8 +9,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x60000000
#define CFG_SYS_SDRAM_SIZE 0x20000000
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 5a7f5e1..1081e0b 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -17,7 +17,7 @@
#define CFG_SYS_SDRAM_SIZE \
(SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#ifndef SANDBOX_NO_SDL
diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
index af5fe27..f7cdd5a 100644
--- a/include/configs/sdm845.h
+++ b/include/configs/sdm845.h
@@ -11,7 +11,7 @@
#include <linux/sizes.h>
#include <asm/arch/sysmap-sdm845.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x4000000\0" \
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 31552f4..5a00171 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -35,7 +35,7 @@
#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1
/* Platform/Board specific defs */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* NS16550 Configuration */
#define CFG_SYS_NS16550_CLK (48000000)
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index d2bc73a..7944759 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -36,8 +36,8 @@
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
/* misc settings */
@@ -87,8 +87,8 @@
* leaving the correct space for initial global data structure above that
* address while providing maximum stack area below.
*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* Defines for SPL */
@@ -102,11 +102,11 @@
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
+#define CFG_SYS_MASTER_CLOCK (198656000/2)
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x2060bf09
-#define CONFIG_SYS_MCKR 0x100
-#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB 0x10483f0e
+#define CFG_SYS_AT91_PLLA 0x2060bf09
+#define CFG_SYS_MCKR 0x100
+#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB 0x10483f0e
#endif /* __CONFIG_H */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 64963ee..ffa1a1f 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -88,7 +88,7 @@
* Boot configuration
*/
-#define CONFIG_SYS_ONENAND_BASE 0xE7100000
+#define CFG_SYS_ONENAND_BASE 0xE7100000
/*
* Ethernet Contoller driver
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 44b9109..14f9cf5 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -39,7 +39,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index 9b1cb37..b7aa49c 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -15,16 +15,16 @@
#include <linux/sizes.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* CPU */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* Mem test settings */
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 9551680..afca7e1 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -15,7 +15,7 @@
* Clocks
*/
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CFG_SYS_TIMERBASE OMAP34XX_GPT2
#define V_NS16550_CLK 48000000
#define V_OSCK 26000000
@@ -55,7 +55,7 @@
#define CFG_SYS_NS16550_CLK V_NS16550_CLK
#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
115200 }
/*
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
index 49883ea..35c777b 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -18,7 +18,7 @@
/*
* Serial / UART configurations
*/
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
/*
* L4 OSC1 Timer 0
diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h
index 261ae56..29b4b22 100644
--- a/include/configs/socfpga_arria5_secu1.h
+++ b/include/configs/socfpga_arria5_secu1.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
/* Eternal oscillator */
-#define CONFIG_SYS_TIMER_RATE 40000000
+#define CFG_SYS_TIMER_RATE 40000000
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */
@@ -21,7 +21,7 @@
* the last two bytes of the 128 bytes large NVRAM in the
* RTC which begin at address 0x20
*/
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Environment settings */
diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h
index 7012097..aa13878 100644
--- a/include/configs/socfpga_chameleonv3.h
+++ b/include/configs/socfpga_chameleonv3.h
@@ -17,7 +17,7 @@
/*
* Serial / UART configurations
*/
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=no\0" \
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 7ef7c5d..bbbdea6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -12,12 +12,12 @@
*/
#define PHYS_SDRAM_1 0x0
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
/* SPL memory allocation configuration, this is for FAT implementation */
-#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE)
#endif
@@ -27,9 +27,9 @@
* at this address to not overwrite the bootcounter by checking, if the
* bootcounter address is located in the internal SRAM.
*/
-#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
- (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE)))
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \
+ (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE)))
#endif
/*
@@ -48,16 +48,16 @@
/*
* Cache
*/
-#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
+#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* L4 OSC1 Timer 0
*/
#ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#ifndef CONFIG_SYS_TIMER_RATE
-#define CONFIG_SYS_TIMER_RATE 25000000
+#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
+#ifndef CFG_SYS_TIMER_RATE
+#define CFG_SYS_TIMER_RATE 25000000
#endif
#endif
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 9403e2f..47089f3 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -26,8 +26,8 @@
/*
* U-Boot run time memory configurations
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CFG_SYS_INIT_RAM_SIZE 0x40000
/*
* U-Boot environment configurations
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index c628860..0a2d581 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -42,20 +42,20 @@
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
+#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_CCSRBAR 0xE0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xE0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */
@@ -63,46 +63,46 @@
/* Hardcoded values, to use instead of SPD */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
-#define CONFIG_SYS_DDR_MODE 0x00480432
-#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
-#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
-#define CONFIG_SYS_DDR_CONFIG 0xC3008000
-#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
+#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CFG_SYS_DDR_CS0_CONFIG 0x80010102
+#define CFG_SYS_DDR_TIMING_0 0x00260802
+#define CFG_SYS_DDR_TIMING_1 0x3935D322
+#define CFG_SYS_DDR_TIMING_2 0x14904CC8
+#define CFG_SYS_DDR_MODE 0x00480432
+#define CFG_SYS_DDR_INTERVAL 0x030C0100
+#define CFG_SYS_DDR_CONFIG_2 0x04400000
+#define CFG_SYS_DDR_CONFIG 0xC3008000
+#define CFG_SYS_DDR_CLK_CONTROL 0x03800000
#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */
/*
* Flash on the LocalBus
*/
-#define CONFIG_SYS_FLASH0 0xFE000000
-#define CONFIG_SYS_FLASH1 0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+#define CFG_SYS_FLASH0 0xFE000000
+#define CFG_SYS_FLASH1 0xFC000000
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH1, CFG_SYS_FLASH0 }
-#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
+#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH1 /* Localbus flash start */
+#define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
+#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
+#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* FPGA and NAND */
-#define CONFIG_SYS_FPGA_BASE 0xc0000000
-#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
+#define CFG_SYS_FPGA_BASE 0xc0000000
+#define CFG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
-#define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
+#define CFG_SYS_NAND_BASE (CFG_SYS_FPGA_BASE + 0x70)
/* LIME GDC */
-#define CONFIG_SYS_LIME_BASE 0xc8000000
+#define CFG_SYS_LIME_BASE 0xc8000000
/*
* General PCI
@@ -137,7 +137,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
index 008aa50..de0f48b 100644
--- a/include/configs/somlabs_visionsom_6ull.h
+++ b/include/configs/somlabs_visionsom_6ull.h
@@ -54,8 +54,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h
index 3c70856..a5987c5 100644
--- a/include/configs/stemmy.h
+++ b/include/configs/stemmy.h
@@ -15,7 +15,7 @@
*/
/* FIXME: This should be loaded from device tree... */
-#define CONFIG_SYS_PL310_BASE 0xa0412000
+#define CFG_SYS_PL310_BASE 0xa0412000
/* Linux does not boot if FDT / initrd is loaded to end of RAM */
#define BOOT_ENV \
diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
index 806323e..9294d57 100644
--- a/include/configs/stih410-b2260.h
+++ b/include/configs/stih410-b2260.h
@@ -14,7 +14,7 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x3E000000
-#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
+#define CFG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
/* Environment */
@@ -22,7 +22,7 @@
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+#define CFG_SYS_BOOTMAPSZ SZ_256M
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 51f6901..afd7d50 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -7,13 +7,13 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h
index 221b7ab..c8aad47 100644
--- a/include/configs/stm32f429-evaluation.h
+++ b/include/configs/stm32f429-evaluation.h
@@ -10,15 +10,15 @@
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_16M
+#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h
index 55e70ce..573a6b1 100644
--- a/include/configs/stm32f469-discovery.h
+++ b/include/configs/stm32f469-discovery.h
@@ -10,15 +10,15 @@
#include <linux/sizes.h>
/* For booting Linux, use the first 12MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M
+#define CFG_SYS_BOOTMAPSZ SZ_8M + SZ_4M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index c7d6d93..14e883a 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -10,15 +10,15 @@
#include <linux/sizes.h>
/* For booting Linux, use the first 6MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
+#define CFG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
@@ -33,7 +33,7 @@
"ramdisk_addr_r=0xC0438000\0" \
BOOTENV
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \
CONFIG_SPL_PAD_TO)
/* For splashcreen */
diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h
index f959fcf..67e6a3a 100644
--- a/include/configs/stm32h743-disco.h
+++ b/include/configs/stm32h743-disco.h
@@ -11,11 +11,11 @@
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_16M
+#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_HZ_CLOCK 1000000
+#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h
index c8688e9..4786eb0 100644
--- a/include/configs/stm32h743-eval.h
+++ b/include/configs/stm32h743-eval.h
@@ -11,11 +11,11 @@
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_16M
+#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_HZ_CLOCK 1000000
+#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h
index f7fa8c5..e667fe6 100644
--- a/include/configs/stm32h750-art-pi.h
+++ b/include/configs/stm32h750-art-pi.h
@@ -11,11 +11,11 @@
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M)
+#define CFG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M)
-#define CONFIG_SYS_FLASH_BASE 0x90000000
+#define CFG_SYS_FLASH_BASE 0x90000000
-#define CONFIG_SYS_HZ_CLOCK 1000000
+#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index d711149..c259a61 100644
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h
@@ -19,7 +19,7 @@
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+#define CFG_SYS_BOOTMAPSZ SZ_256M
/* NAND support */
diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h
index c51022b..ad8126f 100644
--- a/include/configs/stm32mp13_st_common.h
+++ b/include/configs/stm32mp13_st_common.h
@@ -15,7 +15,7 @@
#include <configs/stm32mp13_common.h>
/* uart with on-board st-link */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600, \
1000000, 2000000, 4000000}
diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h
index f78ce41..c9cfadd 100644
--- a/include/configs/stm32mp15_common.h
+++ b/include/configs/stm32mp15_common.h
@@ -19,7 +19,7 @@
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+#define CFG_SYS_BOOTMAPSZ SZ_256M
/* NAND support */
diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index 6bdc286..38b5aa7 100644
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h
@@ -14,7 +14,7 @@
#include <configs/stm32mp15_common.h>
/* uart with on-board st-link */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600, \
1000000, 2000000 }
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index 234327e..faff8d6 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -10,7 +10,7 @@
#define CONFIG_HOSTNAME "stmark2"
-#define CONFIG_SYS_UART_PORT 0
+#define CFG_SYS_UART_PORT 0
#define LDS_BOARD_TEXT \
board/sysam/stmark2/sbf_dram_init.o (.text*)
@@ -34,24 +34,24 @@
"sf write ${loadaddr} 0x00800000 ${filesize}\0" \
""
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
+#define CFG_SYS_SBFHDR_SIZE 0x7
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_PRAM 2048 /* 2048 KB */
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
/*
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
+#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32)
/*
* Start addresses for the final memory configuration
@@ -61,7 +61,7 @@
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
-#define CONFIG_SYS_DRAM_TEST
+#define CFG_SYS_DRAM_TEST
#if defined(CONFIG_CF_SBF)
#define CONFIG_SERIAL_BOOT
@@ -75,7 +75,7 @@
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
(CFG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
@@ -83,22 +83,22 @@
*/
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA)
+#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
+#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 12)
+#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 12)
#endif /* __STMARK2_CONFIG_H */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index b2dcb60..7eadb6d 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_STV0991_H
#define __CONFIG_STV0991_H
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
/* ram memory-related information */
#define PHYS_SDRAM_1 0x00000000
@@ -16,8 +16,8 @@
/* user interface */
/* MISC */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_ADDR 0x00190000
/* U-Boot Load Address */
/* Misc configuration */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index e1a66f5..1677aaf 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -62,9 +62,9 @@
* is known yet.
* H6 has SRAM A1 at 0x00020000.
*/
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
+#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
/* FIXME: this may be larger on some SoCs */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index daa9bbe..6992689 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -6,7 +6,7 @@
#define __CONFIG_H
/* Timers for fasp(TIMCLK) */
-#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
/*
* SDRAM (for initialize)
@@ -28,7 +28,7 @@
*/
/* RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+#define CFG_SYS_I2C_RTC_ADDR 0x51
/* Serial (pl011) */
#define UART_CLK (62500000)
@@ -36,8 +36,8 @@
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CFG_SYS_FLASH_BASE (0x08000000)
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE}
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 1aba986..baaf94e 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -29,8 +29,8 @@
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* Misc CPU related */
@@ -49,8 +49,8 @@
* leaving the correct space for initial global data structure above
* that address while providing maximum stack area below.
*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
@@ -136,11 +136,11 @@
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_MASTER_CLOCK 132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x202A3F01
-#define CONFIG_SYS_MCKR 0x1300
-#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB 0x10193F05
+#define CFG_SYS_AT91_PLLA 0x202A3F01
+#define CFG_SYS_MCKR 0x1300
+#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB 0x10193F05
#endif
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index cd1309b..1318f5e 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -12,8 +12,8 @@
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_128M
/*
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 2d8bde1..f6544f6 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -15,10 +15,10 @@
/* Physical Memory Map */
#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_BOOTMAPSZ 0x10000000
+#define CFG_SYS_BOOTMAPSZ 0x10000000
/* Framebuffer */
#define CONFIG_IMX_HDMI
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 7e764b0..66cf7ae 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -17,8 +17,8 @@
/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
#ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
+#define CFG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
#endif
/* Environment */
@@ -42,11 +42,11 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#ifndef CONFIG_ARM64
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
+#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
+#define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
/* Defines for SPL */
#endif
diff --git a/include/configs/ten64.h b/include/configs/ten64.h
index 04772c9..5772471 100644
--- a/include/configs/ten64.h
+++ b/include/configs/ten64.h
@@ -10,7 +10,7 @@
#include "ls1088a_common.h"
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
#define SD_BOOTCOMMAND "run distro_bootcmd"
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 1f60b9b..7becf1e 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -8,7 +8,7 @@
#define MEM_BASE 0x00500000
-#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
+#define CFG_SYS_LOWMEM_BASE MEM_BASE
/* Link Definitions */
@@ -22,8 +22,8 @@
/* Generic Interrupt Controller Definitions */
#define GICD_BASE (0x801000000000)
#define GICR_BASE (0x801000002000)
-#define CONFIG_SYS_SERIAL0 0x87e024000000
-#define CONFIG_SYS_SERIAL1 0x87e025000000
+#define CFG_SYS_SERIAL0 0x87e024000000
+#define CFG_SYS_SERIAL1 0x87e025000000
/* Miscellaneous configurable options */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index e5b23d2..03849ad 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -74,7 +74,7 @@
/**
* Platform/Board specific defs
*/
-#define CONFIG_SYS_TIMERBASE 0x4802E000
+#define CFG_SYS_TIMERBASE 0x4802E000
/* NS16550 Configuration */
#define CFG_SYS_NS16550_CLK (48000000)
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 4a7c3d5..7b04292 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -25,7 +25,7 @@
/**
* Platform/Board specific defs
*/
-#define CONFIG_SYS_TIMERBASE 0x4802E000
+#define CFG_SYS_TIMERBASE 0x4802E000
/*
* NS16550 Configuration
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 00eb329..ed17b42 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -12,7 +12,7 @@
#define __CONFIG_TI_AM335X_COMMON_H__
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 65abb18..ea45bba 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -14,7 +14,7 @@
/* SoC Configuration */
/* Memory Configuration */
-#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
+#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
#ifdef CONFIG_SYS_MALLOC_F_LEN
@@ -44,7 +44,7 @@
#endif
/* SPI Configuration */
-#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
+#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
/* Keystone net */
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
@@ -176,9 +176,9 @@
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
+#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
#else
-#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk)
+#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk)
#endif
#endif /* __CONFIG_KS2_EVM_H */
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index d282c39..36a05b6 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -27,7 +27,7 @@
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CFG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/* Select serial console configuration */
@@ -46,7 +46,7 @@
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
/* SPL */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index ce50e35..9a068e2 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -12,7 +12,7 @@
#define __CONFIG_TI_OMAP4_COMMON_H
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x48242000
+#define CFG_SYS_PL310_BASE 0x48242000
#endif
/* Get CPU defs */
@@ -20,7 +20,7 @@
#include <asm/arch/omap.h>
/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CFG_SYS_TIMERBASE GPT2_BASE
#include <configs/ti_armv7_omap.h>
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index c49c177..37ab2e4 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -17,7 +17,7 @@
#define __CONFIG_TI_OMAP5_COMMON_H
/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CFG_SYS_TIMERBASE GPT2_BASE
#include <linux/stringify.h>
diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h
index a609aa3..0f28690 100644
--- a/include/configs/total_compute.h
+++ b/include/configs/total_compute.h
@@ -41,6 +41,6 @@
* Else boot FIT image.
*/
-#define CONFIG_SYS_FLASH_BASE 0x0C000000
+#define CFG_SYS_FLASH_BASE 0x0C000000
#endif /* __TOTAL_COMPUTE_H */
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 1378981..24943c8 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0xa0000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
/*
* Serial Port
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index f8e3a2d..9c3454a 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -269,8 +269,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/*
* All the defines above are for the TQMa6 SoM
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index 9991306..ce897fc 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -17,8 +17,8 @@
/* Config on-board RTC */
#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_BUS_NUM 2
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_RTC_BUS_NUM 2
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Turn off RTC square-wave output to save battery */
#define CONFIG_RTC_DS1337_NOOSC
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 23dcf20..5bd0ca2 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -12,7 +12,7 @@
#include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x10502000
+#define CFG_SYS_PL310_BASE 0x10502000
#endif
/* TRATS has 4 banks of DRAM */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 9c6433c..cef5636 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -13,7 +13,7 @@
#include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x10502000
+#define CFG_SYS_PL310_BASE 0x10502000
#endif
/* TRATS2 has 4 banks of DRAM */
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index 4ca8eaf..fdb420e 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h
@@ -9,7 +9,7 @@
#define _CONFIG_TURRIS_MOX_H
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
921600, 1000000, 1152000, 1500000, \
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index c1e80b4..fac8c1e 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -50,8 +50,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index f730926..0e0d5b5 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -58,8 +58,8 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* PMIC */
#define CONFIG_POWER_PFUZE3000
diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
index a977271..ab199bc 100644
--- a/include/configs/ulcb.h
+++ b/include/configs/ulcb.h
@@ -14,7 +14,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __ULCB_H */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index a57ecff..8cd81f1 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -37,7 +37,7 @@
#if !defined(CONFIG_ARM64)
/* Time clock 1MHz */
-#define CONFIG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_RATE 1000000
#endif
#define CFG_SYS_NAND_REGS_BASE 0x68100000
@@ -162,11 +162,11 @@
LINUXBOOT_ENV_SETTINGS \
BOOTENV
-#define CONFIG_SYS_BOOTMAPSZ 0x20000000
+#define CFG_SYS_BOOTMAPSZ 0x20000000
/* only for SPL */
/* subtract sizeof(struct legacy_img_hdr) */
-#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40)
+#define CFG_SYS_UBOOT_BASE (0x130000 - 0x40)
#endif /* __CONFIG_UNIPHIER_H__ */
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index d2fd23e..657dbad 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -17,8 +17,8 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
/*
* Hardware drivers
@@ -28,8 +28,8 @@
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index e944e78..da68d7a 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -61,7 +61,7 @@
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
index d9e5dfa..b031598 100644
--- a/include/configs/vcoreiii.h
+++ b/include/configs/vcoreiii.h
@@ -10,7 +10,7 @@
/* Onboard devices */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index b209d97..18ac6b2 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -53,8 +53,8 @@
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \
"${blkcnt}; fi\0"
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#if defined(CONFIG_ENV_IS_IN_MMC)
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index 1b9f2ca..88839a6 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
@@ -65,8 +65,8 @@
"${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \
"${blkcnt}; fi\0"
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h
index 9a46d50..30c1f50 100644
--- a/include/configs/vexpress_aemv8.h
+++ b/include/configs/vexpress_aemv8.h
@@ -254,9 +254,9 @@
BOOTENV
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
#else
-#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
+#define CFG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
#endif
#endif /* __VEXPRESS_AEMV8_H */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index de571f6..e8b6acf 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -112,16 +112,16 @@
#define SCTL_BASE V2M_SYSCTL
#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
+#define CFG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
+ (void *)CFG_SYS_SERIAL1}
-#define CONFIG_SYS_SERIAL0 V2M_UART0
-#define CONFIG_SYS_SERIAL1 V2M_UART1
+#define CFG_SYS_SERIAL0 V2M_UART0
+#define CFG_SYS_SERIAL1 V2M_UART1
/* Miscellaneous configurable options */
#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
@@ -135,7 +135,7 @@
/* additions for new relocation code */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Basic environment settings */
#define BOOT_TARGET_DEVICES(func) \
@@ -164,7 +164,7 @@
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
/* FLASH and environment organization */
-#define CONFIG_SYS_FLASH_SIZE 0x04000000
+#define CFG_SYS_FLASH_SIZE 0x04000000
/* Timeout values in ticks */
@@ -177,6 +177,6 @@
*/
/* Store environment at top of flash */
-#define CONFIG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 }
+#define CFG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 }
#endif /* VEXPRESS_COMMON_H */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 7b526f7..14e6b2b 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -124,7 +124,7 @@
#define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index df0e269..9f72bdd 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -21,7 +21,7 @@
#define CONFIG_USART_ID 30
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
+#define CFG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
@@ -31,7 +31,7 @@
#ifdef CONFIG_CMD_MMC
#define ATMEL_BASE_MMCI 0xfc000000
-#define CONFIG_SYS_MMC_CLK_OD 500000
+#define CFG_SYS_MMC_CLK_OD 500000
/* For generating MMC partitions */
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 7555d97..ab5cd5c 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -24,8 +24,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
index 38b940d..43050d6 100644
--- a/include/configs/vocore2.h
+++ b/include/configs/vocore2.h
@@ -9,14 +9,14 @@
/* RAM */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */
#define CFG_SYS_NS16550_CLK 40000000
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 3acef22..23027b1 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -90,8 +90,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index cba215c..56c90aa 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -85,8 +85,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 32555c9..065006f 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -42,7 +42,7 @@
*/
/* driver configuration */
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#define CFG_SYS_MAX_NAND_CHIPS 1
#define CFG_SYS_NAND_BASE MLC_NAND_BASE
/*
diff --git a/include/configs/x530.h b/include/configs/x530.h
index a0162ca..dee87cb 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -13,7 +13,7 @@
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index f76c1f8..3e17b53 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -30,7 +30,7 @@
* CPU Features
*/
-#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CFG_SYS_STACK_SIZE (32 * 1024)
/*-----------------------------------------------------------------------
* Environment configuration
diff --git a/include/configs/xea.h b/include/configs/xea.h
index 87f628d..b432ab2 100644
--- a/include/configs/xea.h
+++ b/include/configs/xea.h
@@ -16,9 +16,9 @@
/* SPL */
-#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M
-#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K
-#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K
+#define CFG_SYS_SPI_KERNEL_OFFS SZ_1M
+#define CFG_SYS_SPI_ARGS_OFFS SZ_512K
+#define CFG_SYS_SPI_ARGS_SIZE SZ_32K
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index 8caf539..ee3130e 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -15,7 +15,7 @@
#define GICR_BASE 0xF9080000
/* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
/* GUID for capsule updatable firmware image */
diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 0ccd38b..7d77189 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h
@@ -20,7 +20,7 @@
#define GICR_BASE 0xF9060000
/* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
#if defined(CONFIG_CMD_DFU)
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 60f007a..efe241d 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -15,7 +15,7 @@
#define GICC_BASE 0xF9020000
/* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
/* GUIDs for capsule updatable firmware images */
@@ -192,9 +192,9 @@
#endif
#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
-# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000
-# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000
-# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000
+# define CFG_SYS_SPI_KERNEL_OFFS 0x80000
+# define CFG_SYS_SPI_ARGS_OFFS 0xa0000
+# define CFG_SYS_SPI_ARGS_SIZE 0xa0000
#endif
/* u-boot is like dtb */
diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h
index b6bc402..3a7b7e0 100644
--- a/include/configs/xilinx_zynqmp_r5.h
+++ b/include/configs/xilinx_zynqmp_r5.h
@@ -10,13 +10,13 @@
/* Serial drivers */
/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Boot configuration */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Extend size of kernel image for uncompression */
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 613ed95..3e60489 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -22,8 +22,8 @@
#define PHYS_SDRAM_SIZE (128 << 20)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment is in stored in the eMMC boot partition */
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index 8739bb2..9201dac 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -21,12 +21,12 @@
/*===================*/
#if XCHAL_HAVE_PTP_MMU
-#define CONFIG_SYS_MEMORY_BASE \
+#define CFG_SYS_MEMORY_BASE \
(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
-#define CONFIG_SYS_IO_BASE 0xf0000000
+#define CFG_SYS_IO_BASE 0xf0000000
#else
-#define CONFIG_SYS_MEMORY_BASE 0x60000000
-#define CONFIG_SYS_IO_BASE 0x90000000
+#define CFG_SYS_MEMORY_BASE 0x60000000
+#define CFG_SYS_IO_BASE 0x90000000
#define CONFIG_MAX_MEM_MAPPED 0x10000000
#endif
@@ -100,16 +100,16 @@
*/
/* FPGA core clock frequency in Hz (also input to UART) */
-#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
+#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
/*
* DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
* Bits 0..5 set the lower 6 bits of the default ethernet MAC.
* Bit 6 is reserved for future use by Tensilica.
- * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
+ * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to
* the base of flash * (when on/1) or to the base of RAM (when off/0).
*/
-#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
+#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
#define FPGAREG_MAC_WIDTH 6
#define FPGAREG_MAC_MASK 0x3f
@@ -120,8 +120,8 @@
#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
/* Force hard reset of board by writing a code to this register */
-#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
-#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
+#define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
+#define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
/*====================*/
/* Serial Driver Info */
@@ -137,25 +137,25 @@
/*======================*/
#define CONFIG_ETHBASE 00:50:C2:13:6f:00
-#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
-#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
+#define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000)
+#define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_XTFPGA_LX60
-# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
#elif defined(CONFIG_XTFPGA_KC705)
-# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
+# define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x00000000)
#else
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
#endif
/*
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 2d6522a..b8c142f 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -11,12 +11,12 @@
/* Cache options */
#ifndef CONFIG_SYS_L2CACHE_OFF
-# define CONFIG_SYS_PL310_BASE 0xf8f02000
+# define CFG_SYS_PL310_BASE 0xf8f02000
#endif
#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
-#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
+#define CFG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
/* GUIDs for capsule updatable firmware images */
#define XILINX_BOOT_IMAGE_GUID \
@@ -29,7 +29,7 @@
/* Serial drivers */
/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Ethernet driver */
@@ -188,8 +188,8 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
/* Extend size of kernel image for uncompression */
@@ -200,10 +200,10 @@
/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
-#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \
- CONFIG_SYS_SPI_ARGS_SIZE)
+#define CFG_SYS_SPI_ARGS_OFFS 0x200000
+#define CFG_SYS_SPI_ARGS_SIZE 0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS (CFG_SYS_SPI_ARGS_OFFS + \
+ CFG_SYS_SPI_ARGS_SIZE)
#endif
/* SP location before relocation, must use scratch RAM */
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
index cb982c2..ac6e8c4 100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h
@@ -14,9 +14,9 @@
/* Undef unneeded configs */
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_SYS_INIT_RAM_ADDR
-#undef CONFIG_SYS_INIT_RAM_SIZE
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#undef CFG_SYS_INIT_RAM_ADDR
+#undef CFG_SYS_INIT_RAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFDE000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
#endif /* __CONFIG_ZYNQ_CSE_H */
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index 07a46a4..c701dc1 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -66,7 +66,7 @@
int get_dpl_apply_status(void);
int is_lazy_dpl_addr_valid(void);
void fdt_fixup_mc_ddr(u64 *base, u64 *size);
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
u64 mc_get_dram_addr(void);
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index 9f243cd..de1e70a 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -801,7 +801,7 @@
#define IFC_RREGS_64KOFFSET (64*1024)
#define IFC_FCM_BASE_ADDR \
- ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
+ ((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR)
#define get_ifc_cspr_ext(i) \
(ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
diff --git a/include/i2c.h b/include/i2c.h
index c07e60b..51390f8 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -633,10 +633,10 @@
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
+#if !defined(CFG_SYS_I2C_MAX_HOPS)
/* no muxes used bus = i2c adapters */
#define CONFIG_SYS_I2C_DIRECT_BUS 1
-#define CONFIG_SYS_I2C_MAX_HOPS 0
+#define CFG_SYS_I2C_MAX_HOPS 0
#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
#else
/* we use i2c muxes */
@@ -644,8 +644,8 @@
#endif
/* define the I2C bus number for RTC and DTT if not already done */
-#if !defined(CONFIG_SYS_RTC_BUS_NUM)
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#if !defined(CFG_SYS_RTC_BUS_NUM)
+#define CFG_SYS_RTC_BUS_NUM 0
#endif
struct i2c_adapter {
@@ -705,7 +705,7 @@
struct i2c_bus_hose {
int adapter;
- struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS];
+ struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS];
};
#define I2C_NULL_HOP {{-1, ""}, 0, 0}
extern struct i2c_bus_hose i2c_bus[];
@@ -931,12 +931,12 @@
* completely to new multibus support.
*/
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
-# if !defined(CONFIG_SYS_MAX_I2C_BUS)
-# define CONFIG_SYS_MAX_I2C_BUS 2
+# if !defined(CFG_SYS_MAX_I2C_BUS)
+# define CFG_SYS_MAX_I2C_BUS 2
# endif
# define I2C_MULTI_BUS 1
#else
-# define CONFIG_SYS_MAX_I2C_BUS 1
+# define CFG_SYS_MAX_I2C_BUS 1
# define I2C_MULTI_BUS 0
#endif
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 053b68a..636734d 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -26,38 +26,38 @@
* Define default values for some CCSR macros to make header files cleaner*
*
* To completely disable CCSR relocation in a board header file, define
- * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
- * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CFG_SYS_CCSRBAR.
*/
-#ifdef CONFIG_SYS_CCSRBAR_PHYS
-#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
-CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#ifdef CFG_SYS_CCSRBAR_PHYS
+#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \
+CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead."
#endif
#if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE)
-#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#undef CFG_SYS_CCSRBAR_PHYS_HIGH
+#undef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
- CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CFG_SYS_CCSRBAR_PHYS_LOW)
#endif /* __MPC85xx_H__ */
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 9fe4748..ea8d17d 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -16,9 +16,9 @@
* platform register addresses
*/
-#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4)
-#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000)
-#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008)
+#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4)
+#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000)
+#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008)
/*
* l2cr values. Look in config_<BOARD>.h for the actual setup
diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
index 1321da1..52cd1c4 100644
--- a/include/mtd/cfi_flash.h
+++ b/include/mtd/cfi_flash.h
@@ -147,8 +147,8 @@
u8 minor_version;
} __attribute__((packed));
-#ifndef CONFIG_SYS_FLASH_BANKS_LIST
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#ifndef CFG_SYS_FLASH_BANKS_LIST
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*
diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h
index e75c3fa..0f6f5c2 100644
--- a/include/mvebu_mmc.h
+++ b/include/mvebu_mmc.h
@@ -21,7 +21,7 @@
#define MVEBU_MMC_CLOCKRATE_MAX 50000000
#define MVEBU_MMC_BASE_DIV_MAX 0x7ff
-#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK
+#define MVEBU_MMC_BASE_FAST_CLOCK CFG_SYS_TCLK
#define MVEBU_MMC_BASE_FAST_CLK_100 100000000
#define MVEBU_MMC_BASE_FAST_CLK_200 200000000
diff --git a/include/post.h b/include/post.h
index ec03556..867a66f 100644
--- a/include/post.h
+++ b/include/post.h
@@ -142,7 +142,7 @@
#define CONFIG_SYS_POST_RTC 0x00000001
#define CONFIG_SYS_POST_WATCHDOG 0x00000002
-#define CONFIG_SYS_POST_MEMORY 0x00000004
+#define CFG_SYS_POST_MEMORY 0x00000004
#define CONFIG_SYS_POST_CPU 0x00000008
#define CONFIG_SYS_POST_I2C 0x00000010
#define CONFIG_SYS_POST_CACHE 0x00000020
@@ -163,7 +163,7 @@
#define CONFIG_SYS_POST_CODEC 0x00200000
#define CONFIG_SYS_POST_COPROC 0x00400000
#define CONFIG_SYS_POST_FLASH 0x00800000
-#define CONFIG_SYS_POST_MEM_REGIONS 0x01000000
+#define CFG_SYS_POST_MEM_REGIONS 0x01000000
#endif /* CONFIG_POST */
diff --git a/include/spl.h b/include/spl.h
index 3eb27de..fb8c279 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -470,7 +470,7 @@
* spl_set_header_raw_uboot() - Set up a standard SPL image structure
*
* This sets up the given spl_image which the standard values obtained from
- * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START,
+ * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START,
* CONFIG_TEXT_BASE.
*
* @spl_image: Image description to set up
diff --git a/include/system-constants.h b/include/system-constants.h
index 07c3505..0d6b71b 100644
--- a/include/system-constants.h
+++ b/include/system-constants.h
@@ -12,10 +12,10 @@
#define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR
#else
#ifdef CONFIG_MIPS
-#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET)
+#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CFG_SYS_INIT_SP_OFFSET)
#else
#define SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+ (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#endif
#endif
diff --git a/include/tca642x.h b/include/tca642x.h
index bda86c1..c0a3cef 100644
--- a/include/tca642x.h
+++ b/include/tca642x.h
@@ -41,13 +41,13 @@
#define TCA642X_DIR_IN 1
/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_TCA642X_ADDR
-#define CONFIG_SYS_I2C_TCA642X_ADDR (~0)
+#ifndef CFG_SYS_I2C_TCA642X_ADDR
+#define CFG_SYS_I2C_TCA642X_ADDR (~0)
#endif
/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM
-#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0)
+#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM
+#define CFG_SYS_I2C_TCA642X_BUS_NUM (0)
#endif
struct tca642x_bank_info {
diff --git a/include/tsec.h b/include/tsec.h
index 72f3485..de279b2 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -124,8 +124,8 @@
#define RCTRL_PROM 0x00000008
-#ifndef CONFIG_SYS_TBIPA_VALUE
-# define CONFIG_SYS_TBIPA_VALUE 0x1f
+#ifndef CFG_SYS_TBIPA_VALUE
+# define CFG_SYS_TBIPA_VALUE 0x1f
#endif
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN