| commit | 6666017f44e39ec0385e3c7736b8c9af46cf4f08 | [log] [tgz] |
|---|---|---|
| author | vijay rai <vijay.rai@freescale.com> | Fri Jun 20 10:45:29 2014 +0530 |
| committer | York Sun <yorksun@freescale.com> | Tue Jul 22 16:25:54 2014 -0700 |
| tree | fab7529d9b9ac0b7f28fcbcd358c2ca52633311e | |
| parent | 591dd192307d81cf8f8705b06854e973c53d4c4d [diff] |
powerpc/t1040qds: Initialize EPHY2 clock to RGMII only Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode. Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>