Merge with /home/m8/git/u-boot
diff --git a/CHANGELOG b/CHANGELOG
index b2f2aa9..be18ac2 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,25 +2,22 @@
Changes since U-Boot 1.1.4:
======================================================================
+* Fix coldfire build problems.
+ Patch by Marian Balakowicz, 01 Sep 2006
+
* Add support for a saving build objects in a separate directory.
- Modifications are based on the linux kernel approach and
- support two use cases:
-
- 1) Add O= to the make command line
- 'make O=/tmp/build all'
-
+ Modifications are based on the Linux kernel approach and support
+ two use cases:
+ 1) Add O= to the make command line 'make O=/tmp/build all'
2) Set environement variable BUILD_DIR to point to the desired location
- 'export BUILD_DIR=/tmp/build'
- 'make'
-
+ 'export BUILD_DIR=/tmp/build'
+ 'make'
The second approach can also be used with a MAKEALL script
- 'export BUILD_DIR=/tmp/build'
- './MAKEALL'
-
- Command line 'O=' setting overrides BUILD_DIR environent variable.
-
- When none of the above methods is used the local build is performed and
- the object files are placed in the source directory.
+ 'export BUILD_DIR=/tmp/build'
+ './MAKEALL'
+ Command line 'O=' setting overrides the BUILD_DIR environent variable.
+ When none of the above methods is used the local build is performed
+ and the object files are placed in the source directory.
* Remove the board/netstar/crcit binary from git repository.
@@ -28,6 +25,46 @@
* Fix tools/easylogo build error.
+
+* Fixed problems on PRS200 board caused by adding splash screen on MCC200
+
+* Extended README entry on coding style
+
+* Added another example showing simple interrupt interception.
+
+* Added simple_strtoul(), getenv() and setenv() to the exported functions.
+ Also bumped up ABI version to reflect this change.
+
+* Added interrupt handling capabilities for mpc5xxx processors.
+ Also added Linux like BUG() macros.
+
+* Coding Style cleanup.
+ Patch by Stefano Babic, 31 Aug 2006
+
+* Add splashscreen support for MCC200 board.
+
+* Make the serial driver framework work with CONFIG_SERIAL_MULTI
+ enabled
+
+* PCIe endpoint support for AMCC Yucca 440SPe board
+ Patch by Tirumala R Marri, 26 Aug 2006
+
+* Improve DIMM detection for AMCC Yucca 440SPe board
+ Improved the memory DIMM detection for the Yucca 440SPe board for
+ the case where a memory DIMM is falsely detected as present.
+ This issue is seen on some AMCC Yucca 440SPe validation boards if
+ only one 512MB memory DIMM is installed, i.e. DIMM slot 0 is
+ populated and DIMM slot 1 is empty. In this case, U-Boot does
+ not correctly detect that there is only one DIMM memory module
+ installed and will falsely detect two DIMM memory modules are
+ present and therefore U-Boot will not calculate the correct amount
+ of total memory and u-boot will not booting up.
+ Patch by Adam Graham, 24 Aug 2006
+
+* Fix typo.
+
+* Code cleanup
+
* Update for MCC200 / PRS200 boards:
- auto-adjust console device for Linux.
- fix typos.
diff --git a/MAINTAINERS b/MAINTAINERS
index e1baa42..0c4cfb43 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -318,6 +318,11 @@
MPC8266ADS MPC8266
+
+David Updegraff <dave@cray.com>
+
+ CRAYL1 PPC4xx
+
Josef Wagner <Wagner@Microsys.de>
CPC45 MPC8245
@@ -347,7 +352,6 @@
RPXClassic MPC8xx
RPXlite MPC8xx
- CRAYL1 PPC4xx
ERIC PPC4xx
MOUSSE MPC824x
diff --git a/README b/README
index e772c1a..e024023 100644
--- a/README
+++ b/README
@@ -3469,12 +3469,19 @@
-----------------
All contributions to U-Boot should conform to the Linux kernel
-coding style; see the file "Documentation/CodingStyle" in your Linux
-kernel source directory.
+coding style; see the file "Documentation/CodingStyle" and the script
+"scripts/Lindent" in your Linux kernel source directory. In sources
+originating from U-Boot a style corresponding to "Lindent -pcs" (adding
+spaces before parameters to function calls) is actually used.
-Please note that U-Boot is implemented in C (and to some small parts
-in Assembler); no C++ is used, so please do not use C++ style
-comments (//) in your code.
+Source files originating from a different project (for example the
+MTD subsystem) are generally exempt from these guidelines and are not
+reformated to ease subsequent migration to newer versions of those
+sources.
+
+Please note that U-Boot is implemented in C (and to some small parts in
+Assembler); no C++ is used, so please do not use C++ style comments (//)
+in your code.
Please also stick to the following formatting rules:
- remove any trailing white space
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index a0acbba..e6429ec 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -35,7 +35,7 @@
#include <ppc4xx.h>
#include <asm/processor.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@@ -76,7 +76,7 @@
case FLASH_MAN_SST:
printf("SST ");
break;
- case FLASH_MAN_MX:
+ case FLASH_MAN_MX:
printf ("MACRONIX ");
break;
default:
@@ -223,75 +223,75 @@
return (0); /* no or unknown flash */
}
- value = addr2[1]; /* device ID */
+ value = addr2[1]; /* device ID */
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
+ info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
+ info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
+ info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
info->flash_id += FLASH_AMD016;
info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64;
- info->size = 0x00400000;
- break; /* => 4 MB */
+ info->size = 0x00400000; /* => 4 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
+ info->size = 0x00080000; /* => 512 KiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
+ info->size = 0x00080000; /* => 512 KiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
+ info->size = 0x00100000; /* => 1 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
+ info->size = 0x00100000; /* => 1 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
default:
info->flash_id = FLASH_UNKNOWN;
@@ -306,7 +306,7 @@
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
+ /* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
@@ -316,7 +316,7 @@
base + (i * 0x00010000) - 0x00030000;
}
} else {
- /* set sector offsets for top boot block type */
+ /* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
@@ -666,7 +666,7 @@
return (0); /* no or unknown flash */
}
- value = addr2[1]; /* device ID */
+ value = addr2[1]; /* device ID */
DEBUGF("\nFLASH DEVICEID: %x\n", value);
@@ -675,17 +675,17 @@
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
+ info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
+ info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
info->flash_id += FLASH_STMW320DT;
info->sector_count = 67;
- info->size = 0x00400000; break; /* => 4 MB */
+ info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
info->flash_id += FLASH_MXLV320T;
@@ -743,7 +743,7 @@
info->start[i] = base + i * 0x00010000;
} else {
if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
+ /* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
@@ -753,7 +753,7 @@
base + (i * 0x00010000) - 0x00030000;
}
} else {
- /* set sector offsets for top boot block type */
+ /* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index af12839..cd17526 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -32,6 +32,10 @@
#include <asm-ppc/io.h>
#include "yucca.h"
+#include "../cpu/ppc4xx/440spe_pcie.h"
+
+#undef PCIE_ENDPOINT
+/* #define PCIE_ENDPOINT 1 */
void fpga_init (void);
@@ -562,10 +566,11 @@
static long int yucca_probe_for_dimms(void)
{
- long int dimm_installed[MAXDIMMS];
- long int dimm_num, probe_result;
- long int dimms_found = 0;
- uchar dimm_addr = IIC0_DIMM0_ADDR;
+ int dimm_installed[MAXDIMMS];
+ int dimm_num, result;
+ int dimms_found = 0;
+ uchar dimm_addr = IIC0_DIMM0_ADDR;
+ uchar dimm_spd_data[MAX_SPD_BYTES];
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
/* check if there is a chip at the dimm address */
@@ -577,12 +582,28 @@
dimm_addr = IIC0_DIMM1_ADDR;
break;
}
- probe_result = i2c_probe(dimm_addr);
- if (probe_result == 0) {
+ result = i2c_probe(dimm_addr);
+
+ memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
+ if (result == 0) {
+ /* read first byte of SPD data, if there is any data */
+ result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
+
+ if (result == 0) {
+ result = dimm_spd_data[0];
+ result = result > MAX_SPD_BYTES ?
+ MAX_SPD_BYTES : result;
+ result = i2c_read(dimm_addr, 0, 1,
+ dimm_spd_data, result);
+ }
+ }
+
+ if ((result == 0) &&
+ (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
dimm_installed[dimm_num] = TRUE;
dimms_found++;
- debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num);
+ debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
} else {
dimm_installed[dimm_num] = FALSE;
debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
@@ -1012,6 +1033,57 @@
out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
}
+/*
+ * For the given slot, set endpoint mode, send power to the slot,
+ * turn on the green LED and turn off the yellow LED, enable the clock
+ * .In end point mode reset bit is read only.
+ */
+void yucca_setup_pcie_fpga_endpoint(int port)
+{
+ u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
+
+ switch(port) {
+ case 0:
+ rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
+ endpoint = 0;
+ power = FPGA_REG1A_PE0_PWRON;
+ green_led = FPGA_REG1A_PE0_GLED;
+ clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE0_YLED;
+ reset_off = FPGA_REG1C_PE0_PERST;
+ break;
+ case 1:
+ rootpoint = 0;
+ endpoint = FPGA_REG1C_PE1_ENDPOINT;
+ power = FPGA_REG1A_PE1_PWRON;
+ green_led = FPGA_REG1A_PE1_GLED;
+ clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE1_YLED;
+ reset_off = FPGA_REG1C_PE1_PERST;
+ break;
+ case 2:
+ rootpoint = 0;
+ endpoint = FPGA_REG1C_PE2_ENDPOINT;
+ power = FPGA_REG1A_PE2_PWRON;
+ green_led = FPGA_REG1A_PE2_GLED;
+ clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE2_YLED;
+ reset_off = FPGA_REG1C_PE2_PERST;
+ break;
+
+ default:
+ return;
+ }
+
+ out_be16((u16 *)FPGA_REG1A,
+ ~(power | clock | green_led) &
+ (yellow_led | in_be16((u16 *)FPGA_REG1A)));
+
+ out_be16((u16 *)FPGA_REG1C,
+ ~(rootpoint | reset_off) &
+ (endpoint | in_be16((u16 *)FPGA_REG1C)));
+}
+
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
@@ -1031,9 +1103,13 @@
if (!yucca_pcie_card_present(i))
continue;
+#ifdef PCIE_ENDPOINT
+ yucca_setup_pcie_fpga_endpoint(i);
+ if (ppc440spe_init_pcie_endport(i)) {
+#else
yucca_setup_pcie_fpga_rootpoint(i);
-
if (ppc440spe_init_pcie_rootport(i)) {
+#endif
printf("PCIE%d: initialization failed\n", i);
continue;
}
@@ -1053,8 +1129,19 @@
hose->region_count = 1;
pci_register_hose(hose);
- ppc440spe_setup_pcie(hose, i);
+#ifdef PCIE_ENDPOINT
+ ppc440spe_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+#else
+ ppc440spe_setup_pcie_rootpoint(hose, i);
+ /*
+ * Config access can only go down stream
+ */
hose->last_busno = pci_hose_scan(hose);
+#endif
}
}
#endif /* defined(CONFIG_PCI) */
diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h
index 66f7584..4d13021 100644
--- a/board/amcc/yucca/yucca.h
+++ b/board/amcc/yucca/yucca.h
@@ -60,6 +60,9 @@
#define NUM_TLB_ENTRIES 64
+/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
+#define MICRON_SPD_JEDEC_ID 0x2c
+
/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
index e8c2614..9fecdd0 100644
--- a/board/cpu87/cpu87.c
+++ b/board/cpu87/cpu87.c
@@ -294,15 +294,15 @@
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
-
+
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
-
+
size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
(uchar *) CFG_SDRAM_BASE);
-
+
psize = max(size8,max(size9,size10));
-
+
if (psize == size8) {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
index 4b2bbe2..eb1d059 100644
--- a/board/mcc200/Makefile
+++ b/board/mcc200/Makefile
@@ -25,7 +25,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS := $(BOARD).o lcd.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c
new file mode 100644
index 0000000..b262516
--- /dev/null
+++ b/board/mcc200/lcd.c
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <mpc5xxx.h>
+
+#ifdef CONFIG_LCD
+
+#define SWAPPED_LCD
+/*
+ * The name of the device used for communication
+ * with the PSoC.
+ */
+#define PSOC_PSC MPC5XXX_PSC2
+#define PSOC_BAUD 500000UL
+
+#define RTS_ASSERT 1
+#define RTS_NEGATE 0
+#define CTS_ASSERT 1
+#define CTS_NEGATE 0
+
+/*
+ * Dimensions in pixels
+ */
+#define LCD_WIDTH 160
+#define LCD_HEIGHT 100
+
+/*
+ * Dimensions in bytes
+ */
+#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3)
+
+#if LCD_BPP != LCD_MONOCHROME
+#error "MCC200 support only monochrome displays (1 bpp)!"
+#endif
+
+#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */
+#define PSOC_WAIT_TIME 10 /* usec */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * LCD information
+ */
+vidinfo_t panel_info = {
+ LCD_WIDTH, LCD_HEIGHT, LCD_BPP
+};
+
+int lcd_line_length;
+
+int lcd_color_fg;
+int lcd_color_bg;
+
+/*
+ * Frame buffer memory information
+ */
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+short console_col = 0;
+short console_row = 0;
+
+/*
+ * The device we use to communicate with PSoC
+ */
+int serial_inited = 0;
+
+/*
+ * Exported functions
+ */
+void lcd_initcolregs (void);
+void lcd_ctrl_init (void *lcdbase);
+void lcd_enable (void);
+
+/*
+ * Imported functions to support the PSoC protocol
+ */
+extern int serial_init_dev (unsigned long dev_base);
+extern void serial_setrts_dev (unsigned long dev_base, int s);
+extern int serial_getcts_dev (unsigned long dev_base);
+extern void serial_putc_raw_dev(unsigned long dev_base, const char c);
+
+/*
+ * Just stubs for our driver, needed for compiling compabilty with
+ * the common LCD driver code.
+ */
+void lcd_initcolregs (void)
+{
+}
+
+void lcd_ctrl_init (void *lcdbase)
+{
+}
+
+/*
+ * Function sends the contents of the frame-buffer to the LCD
+ */
+void lcd_enable (void)
+{
+ int i, retries, fb_size;
+
+ if (!serial_inited) {
+ unsigned long baud;
+
+ baud = gd->baudrate;
+ gd->baudrate = PSOC_BAUD;
+ serial_init_dev(PSOC_PSC);
+ gd->baudrate = baud;
+ serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+ serial_inited = 1;
+ }
+
+ /*
+ * Implement PSoC communication protocol:
+ * 1. Assert RTS, wait CTS assertion
+ * 2. Transmit data
+ * 3. Negate RTS, wait CTS negation
+ */
+
+ /* 1 */
+ serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+ for (retries = PSOC_RETRIES; retries; retries--) {
+ if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT)
+ break;
+ udelay (PSOC_WAIT_TIME);
+ }
+ if (!retries) {
+ printf ("%s Error: PSoC doesn't respond on "
+ "RTS ASSERT\n", __FUNCTION__);
+ }
+
+ /* 2 */
+ fb_size = panel_info.vl_row * (panel_info.vl_col >> 3);
+
+#if !defined(SWAPPED_LCD)
+ for (i=0; i<fb_size; i++) {
+ serial_putc_raw_dev (PSOC_PSC, ((char *)lcd_base)[i]);
+ }
+#else
+ {
+ int x, y, pwidth;
+ char *p = (char *)lcd_base;
+
+ pwidth = ((panel_info.vl_col+7) >> 3);
+ for (y=0; y<panel_info.vl_row; y++) {
+ i = y * pwidth;
+ for (x=0; x<pwidth; x+=5) {
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F));
+ }
+ }
+ }
+#endif
+
+ /* 3 */
+ serial_setrts_dev (PSOC_PSC, RTS_NEGATE);
+ for (retries = PSOC_RETRIES; retries; retries--) {
+ if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE)
+ break;
+ udelay (PSOC_WAIT_TIME);
+ }
+ if (!retries) {
+ printf ("%s Error: PSoC doesn't respond on "
+ "RTS NEGATE\n", __FUNCTION__);
+ }
+
+ return;
+}
+#endif /* CONFIG_LCD */
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 9c57809..71a691b 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -265,8 +265,8 @@
*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
flash_info[0].size = 32 << 20;
- for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
- flash_info[0].start[snum] < flash_sup_end;
+ for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
+ flash_info[0].start[snum] < flash_sup_end;
snum++);
flash_info[0].sector_count = snum;
}
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c
index c8350ab..2a0d542 100644
--- a/board/tqm5200/tqm5200.c
+++ b/board/tqm5200/tqm5200.c
@@ -743,7 +743,7 @@
/* Read in TIMER_3 pin status */
timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
-
+
#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
/* Force silent console mode if S1 switch
* is in closed position (TIMER_3 pin status is LOW). */
@@ -757,5 +757,5 @@
return 0;
}
-#endif
-#endif
+#endif /* CONFIG_FO300 */
+#endif /* CONFIG_BOARD_EARLY_INIT_F */
diff --git a/common/exports.c b/common/exports.c
index ef25338..0cb4396 100644
--- a/common/exports.c
+++ b/common/exports.c
@@ -23,8 +23,11 @@
gd->jt[XF_get_version] = (void *) get_version;
gd->jt[XF_malloc] = (void *) malloc;
gd->jt[XF_free] = (void *) free;
- gd->jt[XF_get_timer] = (void *)get_timer;
- gd->jt[XF_udelay] = (void *)udelay;
+ gd->jt[XF_getenv] = (void *) getenv;
+ gd->jt[XF_setenv] = (void *) setenv;
+ gd->jt[XF_get_timer] = (void *) get_timer;
+ gd->jt[XF_simple_strtoul] = (void *) simple_strtoul;
+ gd->jt[XF_udelay] = (void *) udelay;
#if defined(CONFIG_I386) || defined(CONFIG_PPC)
gd->jt[XF_install_hdlr] = (void *) irq_install_handler;
gd->jt[XF_free_hdlr] = (void *) irq_free_handler;
diff --git a/common/lcd.c b/common/lcd.c
index 0be1912..d79350f 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -585,6 +585,7 @@
uchar *bmap;
ushort padded_line;
unsigned long width, height;
+ unsigned long pwidth = panel_info.vl_col;
unsigned colors,bpix;
unsigned long compression;
#if defined(CONFIG_PXA250)
@@ -628,6 +629,8 @@
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
+#elif defined(CONFIG_MCC200)
+ /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
#else
# error "Don't know location of color map"
#endif
@@ -652,9 +655,28 @@
}
}
+ /*
+ * BMP format for Monochrome assumes that the state of a
+ * pixel is described on a per Bit basis, not per Byte.
+ * So, in case of Monochrome BMP we should align widths
+ * on a byte boundary and convert them from Bit to Byte
+ * units.
+ * Probably, PXA250 and MPC823 process 1bpp BMP images in
+ * their own ways, so make the converting to be MCC200
+ * specific.
+ */
+#if defined(CONFIG_MCC200)
+ if (bpix==1)
+ {
+ width = ((width + 7) & ~7) >> 3;
+ x = ((x + 7) & ~7) >> 3;
+ pwidth= ((pwidth + 7) & ~7) >> 3;
+ }
+#endif
+
padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
- if ((x + width)>panel_info.vl_col)
- width = panel_info.vl_col - x;
+ if ((x + width)>pwidth)
+ width = pwidth - x;
if ((y + height)>panel_info.vl_row)
height = panel_info.vl_row - y;
@@ -666,7 +688,7 @@
for (j = 0; j < width ; j++)
#if defined(CONFIG_PXA250)
*(fb++)=*(bmap++);
-#elif defined(CONFIG_MPC823)
+#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
*(fb++)=255-*(bmap++);
#endif
bmap += (width - padded_line);
diff --git a/common/serial.c b/common/serial.c
index 38057d2..605d4e3 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -42,7 +42,19 @@
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
-#if defined(CONFIG_UART1_CONSOLE)
+#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
+#if (CONFIG_CONS_INDEX==1)
+ return &eserial1_device;
+#elif (CONFIG_CONS_INDEX==2)
+ return &eserial2_device;
+#elif (CONFIG_CONS_INDEX==3)
+ return &eserial3_device;
+#elif (CONFIG_CONS_INDEX==4)
+ return &eserial4_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
+#endif
+#elif defined(CONFIG_UART1_CONSOLE)
return &serial1_device;
#else
return &serial0_device;
@@ -84,6 +96,20 @@
serial_register(&serial1_device);
#endif
+#if defined(CFG_NS16550_SERIAL)
+#if defined(CFG_NS16550_COM1)
+ serial_register(&eserial1_device);
+#endif
+#if defined(CFG_NS16550_COM2)
+ serial_register(&eserial2_device);
+#endif
+#if defined(CFG_NS16550_COM3)
+ serial_register(&eserial3_device);
+#endif
+#if defined(CFG_NS16550_COM4)
+ serial_register(&eserial4_device);
+#endif
+#endif /* CFG_NS16550_SERIAL */
serial_assign (default_serial_console ()->name);
}
diff --git a/common/xyzModem.c b/common/xyzModem.c
index d1d66e8..a209dfa 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -69,135 +69,157 @@
#define BSP 0x08
#define NAK 0x15
#define CAN 0x18
-#define EOF 0x1A /* ^Z for DOS officionados */
+#define EOF 0x1A /* ^Z for DOS officionados */
#define USE_YMODEM_LENGTH
/* Data & state local to the protocol */
-static struct {
+static struct
+{
#ifdef REDBOOT
- hal_virtual_comm_table_t* __chan;
+ hal_virtual_comm_table_t *__chan;
#else
- int *__chan;
+ int *__chan;
#endif
- unsigned char pkt[1024], *bufp;
- unsigned char blk,cblk,crc1,crc2;
- unsigned char next_blk; /* Expected block */
- int len, mode, total_retries;
- int total_SOH, total_STX, total_CAN;
- bool crc_mode, at_eof, tx_ack;
+ unsigned char pkt[1024], *bufp;
+ unsigned char blk, cblk, crc1, crc2;
+ unsigned char next_blk; /* Expected block */
+ int len, mode, total_retries;
+ int total_SOH, total_STX, total_CAN;
+ bool crc_mode, at_eof, tx_ack;
#ifdef USE_YMODEM_LENGTH
- unsigned long file_length, read_length;
+ unsigned long file_length, read_length;
#endif
} xyz;
-#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */
+#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */
#define xyzModem_MAX_RETRIES 20
#define xyzModem_MAX_RETRIES_WITH_CRC 10
-#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */
+#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */
-#ifndef REDBOOT /*SB */
+#ifndef REDBOOT /*SB */
typedef int cyg_int32;
-int CYGACC_COMM_IF_GETC_TIMEOUT (char chan,char *c) {
+int
+CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
+{
#define DELAY 20
- unsigned long counter=0;
- while (!tstc() && (counter < xyzModem_CHAR_TIMEOUT*1000/DELAY)) {
- udelay(DELAY);
- counter++;
- }
- if (tstc()) {
- *c=getc();
- return 1;
- }
- return 0;
+ unsigned long counter = 0;
+ while (!tstc () && (counter < xyzModem_CHAR_TIMEOUT * 1000 / DELAY))
+ {
+ udelay (DELAY);
+ counter++;
+ }
+ if (tstc ())
+ {
+ *c = getc ();
+ return 1;
+ }
+ return 0;
}
-void CYGACC_COMM_IF_PUTC(char x,char y) {
- putc(y);
+void
+CYGACC_COMM_IF_PUTC (char x, char y)
+{
+ putc (y);
}
/* Validate a hex character */
__inline__ static bool
-_is_hex(char c)
+_is_hex (char c)
{
- return (((c >= '0') && (c <= '9')) ||
- ((c >= 'A') && (c <= 'F')) ||
- ((c >= 'a') && (c <= 'f')));
+ return (((c >= '0') && (c <= '9')) ||
+ ((c >= 'A') && (c <= 'F')) || ((c >= 'a') && (c <= 'f')));
}
/* Convert a single hex nibble */
__inline__ static int
-_from_hex(char c)
+_from_hex (char c)
{
- int ret = 0;
+ int ret = 0;
- if ((c >= '0') && (c <= '9')) {
- ret = (c - '0');
- } else if ((c >= 'a') && (c <= 'f')) {
- ret = (c - 'a' + 0x0a);
- } else if ((c >= 'A') && (c <= 'F')) {
- ret = (c - 'A' + 0x0A);
+ if ((c >= '0') && (c <= '9'))
+ {
+ ret = (c - '0');
}
- return ret;
+ else if ((c >= 'a') && (c <= 'f'))
+ {
+ ret = (c - 'a' + 0x0a);
+ }
+ else if ((c >= 'A') && (c <= 'F'))
+ {
+ ret = (c - 'A' + 0x0A);
+ }
+ return ret;
}
/* Convert a character to lower case */
__inline__ static char
-_tolower(char c)
+_tolower (char c)
{
- if ((c >= 'A') && (c <= 'Z')) {
- c = (c - 'A') + 'a';
+ if ((c >= 'A') && (c <= 'Z'))
+ {
+ c = (c - 'A') + 'a';
}
- return c;
+ return c;
}
/* Parse (scan) a number */
bool
-parse_num(char *s, unsigned long *val, char **es, char *delim)
+parse_num (char *s, unsigned long *val, char **es, char *delim)
{
- bool first = true;
- int radix = 10;
- char c;
- unsigned long result = 0;
- int digit;
+ bool first = true;
+ int radix = 10;
+ char c;
+ unsigned long result = 0;
+ int digit;
- while (*s == ' ') s++;
- while (*s) {
- if (first && (s[0] == '0') && (_tolower(s[1]) == 'x')) {
- radix = 16;
- s += 2;
- }
- first = false;
- c = *s++;
- if (_is_hex(c) && ((digit = _from_hex(c)) < radix)) {
- /* Valid digit */
+ while (*s == ' ')
+ s++;
+ while (*s)
+ {
+ if (first && (s[0] == '0') && (_tolower (s[1]) == 'x'))
+ {
+ radix = 16;
+ s += 2;
+ }
+ first = false;
+ c = *s++;
+ if (_is_hex (c) && ((digit = _from_hex (c)) < radix))
+ {
+ /* Valid digit */
#ifdef CYGPKG_HAL_MIPS
- /* FIXME: tx49 compiler generates 0x2539018 for MUL which */
- /* isn't any good. */
- if (16 == radix)
- result = result << 4;
- else
- result = 10 * result;
- result += digit;
+ /* FIXME: tx49 compiler generates 0x2539018 for MUL which */
+ /* isn't any good. */
+ if (16 == radix)
+ result = result << 4;
+ else
+ result = 10 * result;
+ result += digit;
#else
- result = (result * radix) + digit;
+ result = (result * radix) + digit;
#endif
- } else {
- if (delim != (char *)0) {
- /* See if this character is one of the delimiters */
- char *dp = delim;
- while (*dp && (c != *dp)) dp++;
- if (*dp) break; /* Found a good delimiter */
- }
- return false; /* Malformatted number */
- }
+ }
+ else
+ {
+ if (delim != (char *) 0)
+ {
+ /* See if this character is one of the delimiters */
+ char *dp = delim;
+ while (*dp && (c != *dp))
+ dp++;
+ if (*dp)
+ break; /* Found a good delimiter */
+ }
+ return false; /* Malformatted number */
+ }
}
- *val = result;
- if (es != (char **)0) {
- *es = s;
+ *val = result;
+ if (es != (char **) 0)
+ {
+ *es = s;
}
- return true;
+ return true;
}
#endif
@@ -211,24 +233,26 @@
* messages.
*/
static int
-zm_dprintf(char *fmt, ...)
+zm_dprintf (char *fmt, ...)
{
- int cur_console;
- va_list args;
+ int cur_console;
+ va_list args;
- va_start(args, fmt);
+ va_start (args, fmt);
#ifdef REDBOOT
- cur_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+ cur_console =
+ CYGACC_CALL_IF_SET_CONSOLE_COMM
+ (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (1);
#endif
- diag_vprintf(fmt, args);
+ diag_vprintf (fmt, args);
#ifdef REDBOOT
- CYGACC_CALL_IF_SET_CONSOLE_COMM(cur_console);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (cur_console);
#endif
}
static void
-zm_flush(void)
+zm_flush (void)
{
}
@@ -238,42 +262,43 @@
*/
#define FINAL
#ifdef FINAL
-static char *zm_out = (char *)0x00380000;
-static char *zm_out_start = (char *)0x00380000;
+static char *zm_out = (char *) 0x00380000;
+static char *zm_out_start = (char *) 0x00380000;
#else
static char zm_buf[8192];
-static char *zm_out=zm_buf;
+static char *zm_out = zm_buf;
static char *zm_out_start = zm_buf;
#endif
static int
-zm_dprintf(char *fmt, ...)
+zm_dprintf (char *fmt, ...)
{
- int len;
- va_list args;
+ int len;
+ va_list args;
- va_start(args, fmt);
- len = diag_vsprintf(zm_out, fmt, args);
- zm_out += len;
- return len;
+ va_start (args, fmt);
+ len = diag_vsprintf (zm_out, fmt, args);
+ zm_out += len;
+ return len;
}
static void
-zm_flush(void)
+zm_flush (void)
{
#ifdef REDBOOT
- char *p = zm_out_start;
- while (*p) mon_write_char(*p++);
+ char *p = zm_out_start;
+ while (*p)
+ mon_write_char (*p++);
#endif
- zm_out = zm_out_start;
+ zm_out = zm_out_start;
}
#endif
static void
-zm_dump_buf(void *buf, int len)
+zm_dump_buf (void *buf, int len)
{
#ifdef REDBOOT
- diag_vdump_buf_with_offset(zm_dprintf, buf, len, 0);
+ diag_vdump_buf_with_offset (zm_dprintf, buf, len, 0);
#else
#endif
@@ -283,22 +308,22 @@
static unsigned char *zm_bp;
static void
-zm_new(void)
+zm_new (void)
{
- zm_bp = zm_buf;
+ zm_bp = zm_buf;
}
static void
-zm_save(unsigned char c)
+zm_save (unsigned char c)
{
- *zm_bp++ = c;
+ *zm_bp++ = c;
}
static void
-zm_dump(int line)
+zm_dump (int line)
{
- zm_dprintf("Packet at line: %d\n", line);
- zm_dump_buf(zm_buf, zm_bp-zm_buf);
+ zm_dprintf ("Packet at line: %d\n", line);
+ zm_dump_buf (zm_buf, zm_bp - zm_buf);
}
#define ZM_DEBUG(x) x
@@ -308,439 +333,517 @@
/* Wait for the line to go idle */
static void
-xyzModem_flush(void)
+xyzModem_flush (void)
{
- int res;
- char c;
- while (true) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
- if (!res) return;
+ int res;
+ char c;
+ while (true)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c);
+ if (!res)
+ return;
}
}
static int
-xyzModem_get_hdr(void)
+xyzModem_get_hdr (void)
{
- char c;
- int res;
- bool hdr_found = false;
- int i, can_total, hdr_chars;
- unsigned short cksum;
+ char c;
+ int res;
+ bool hdr_found = false;
+ int i, can_total, hdr_chars;
+ unsigned short cksum;
- ZM_DEBUG(zm_new());
- /* Find the start of a header */
- can_total = 0;
- hdr_chars = 0;
+ ZM_DEBUG (zm_new ());
+ /* Find the start of a header */
+ can_total = 0;
+ hdr_chars = 0;
- if (xyz.tx_ack) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- xyz.tx_ack = false;
+ if (xyz.tx_ack)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ xyz.tx_ack = false;
}
- while (!hdr_found) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
- ZM_DEBUG(zm_save(c));
- if (res) {
- hdr_chars++;
- switch (c) {
- case SOH:
- xyz.total_SOH++;
- case STX:
- if (c == STX) xyz.total_STX++;
- hdr_found = true;
- break;
- case CAN:
- xyz.total_CAN++;
- ZM_DEBUG(zm_dump(__LINE__));
- if (++can_total == xyzModem_CAN_COUNT) {
- return xyzModem_cancel;
- } else {
- /* Wait for multiple CAN to avoid early quits */
- break;
- }
- case EOT:
- /* EOT only supported if no noise */
- if (hdr_chars == 1) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- ZM_DEBUG(zm_dprintf("ACK on EOT #%d\n", __LINE__));
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_eof;
- }
- default:
- /* Ignore, waiting for start of header */
- ;
- }
- } else {
- /* Data stream timed out */
- xyzModem_flush(); /* Toss any current input */
- ZM_DEBUG(zm_dump(__LINE__));
- CYGACC_CALL_IF_DELAY_US((cyg_int32)250000);
- return xyzModem_timeout;
- }
+ while (!hdr_found)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c);
+ ZM_DEBUG (zm_save (c));
+ if (res)
+ {
+ hdr_chars++;
+ switch (c)
+ {
+ case SOH:
+ xyz.total_SOH++;
+ case STX:
+ if (c == STX)
+ xyz.total_STX++;
+ hdr_found = true;
+ break;
+ case CAN:
+ xyz.total_CAN++;
+ ZM_DEBUG (zm_dump (__LINE__));
+ if (++can_total == xyzModem_CAN_COUNT)
+ {
+ return xyzModem_cancel;
+ }
+ else
+ {
+ /* Wait for multiple CAN to avoid early quits */
+ break;
+ }
+ case EOT:
+ /* EOT only supported if no noise */
+ if (hdr_chars == 1)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ ZM_DEBUG (zm_dprintf ("ACK on EOT #%d\n", __LINE__));
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_eof;
+ }
+ default:
+ /* Ignore, waiting for start of header */
+ ;
+ }
+ }
+ else
+ {
+ /* Data stream timed out */
+ xyzModem_flush (); /* Toss any current input */
+ ZM_DEBUG (zm_dump (__LINE__));
+ CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);
+ return xyzModem_timeout;
+ }
}
- /* Header found, now read the data */
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.blk);
- ZM_DEBUG(zm_save(xyz.blk));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
+ /* Header found, now read the data */
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.blk);
+ ZM_DEBUG (zm_save (xyz.blk));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
}
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.cblk);
- ZM_DEBUG(zm_save(xyz.cblk));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.cblk);
+ ZM_DEBUG (zm_save (xyz.cblk));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
}
- xyz.len = (c == SOH) ? 128 : 1024;
- xyz.bufp = xyz.pkt;
- for (i = 0; i < xyz.len; i++) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
- ZM_DEBUG(zm_save(c));
- if (res) {
- xyz.pkt[i] = c;
- } else {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
- }
+ xyz.len = (c == SOH) ? 128 : 1024;
+ xyz.bufp = xyz.pkt;
+ for (i = 0; i < xyz.len; i++)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c);
+ ZM_DEBUG (zm_save (c));
+ if (res)
+ {
+ xyz.pkt[i] = c;
+ }
+ else
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
+ }
}
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc1);
- ZM_DEBUG(zm_save(xyz.crc1));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.crc1);
+ ZM_DEBUG (zm_save (xyz.crc1));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
}
- if (xyz.crc_mode) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc2);
- ZM_DEBUG(zm_save(xyz.crc2));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
- }
+ if (xyz.crc_mode)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.crc2);
+ ZM_DEBUG (zm_save (xyz.crc2));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
+ }
}
- ZM_DEBUG(zm_dump(__LINE__));
- /* Validate the message */
- if ((xyz.blk ^ xyz.cblk) != (unsigned char)0xFF) {
- ZM_DEBUG(zm_dprintf("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, (xyz.blk ^ xyz.cblk)));
- ZM_DEBUG(zm_dump_buf(xyz.pkt, xyz.len));
- xyzModem_flush();
- return xyzModem_frame;
+ ZM_DEBUG (zm_dump (__LINE__));
+ /* Validate the message */
+ if ((xyz.blk ^ xyz.cblk) != (unsigned char) 0xFF)
+ {
+ ZM_DEBUG (zm_dprintf
+ ("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk,
+ (xyz.blk ^ xyz.cblk)));
+ ZM_DEBUG (zm_dump_buf (xyz.pkt, xyz.len));
+ xyzModem_flush ();
+ return xyzModem_frame;
}
- /* Verify checksum/CRC */
- if (xyz.crc_mode) {
- cksum = cyg_crc16(xyz.pkt, xyz.len);
- if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) {
- ZM_DEBUG(zm_dprintf("CRC error - recvd: %02x%02x, computed: %x\n",
- xyz.crc1, xyz.crc2, cksum & 0xFFFF));
- return xyzModem_cksum;
- }
- } else {
- cksum = 0;
- for (i = 0; i < xyz.len; i++) {
- cksum += xyz.pkt[i];
- }
- if (xyz.crc1 != (cksum & 0xFF)) {
- ZM_DEBUG(zm_dprintf("Checksum error - recvd: %x, computed: %x\n", xyz.crc1, cksum & 0xFF));
- return xyzModem_cksum;
- }
+ /* Verify checksum/CRC */
+ if (xyz.crc_mode)
+ {
+ cksum = cyg_crc16 (xyz.pkt, xyz.len);
+ if (cksum != ((xyz.crc1 << 8) | xyz.crc2))
+ {
+ ZM_DEBUG (zm_dprintf ("CRC error - recvd: %02x%02x, computed: %x\n",
+ xyz.crc1, xyz.crc2, cksum & 0xFFFF));
+ return xyzModem_cksum;
+ }
}
- /* If we get here, the message passes [structural] muster */
- return 0;
+ else
+ {
+ cksum = 0;
+ for (i = 0; i < xyz.len; i++)
+ {
+ cksum += xyz.pkt[i];
+ }
+ if (xyz.crc1 != (cksum & 0xFF))
+ {
+ ZM_DEBUG (zm_dprintf
+ ("Checksum error - recvd: %x, computed: %x\n", xyz.crc1,
+ cksum & 0xFF));
+ return xyzModem_cksum;
+ }
+ }
+ /* If we get here, the message passes [structural] muster */
+ return 0;
}
int
-xyzModem_stream_open(connection_info_t *info, int *err)
+xyzModem_stream_open (connection_info_t * info, int *err)
{
#ifdef REDBOOT
- int console_chan;
+ int console_chan;
#endif
- int stat = 0;
- int retries = xyzModem_MAX_RETRIES;
- int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
+ int stat = 0;
+ int retries = xyzModem_MAX_RETRIES;
+ int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
/* ZM_DEBUG(zm_out = zm_out_start); */
#ifdef xyzModem_zmodem
- if (info->mode == xyzModem_zmodem) {
- *err = xyzModem_noZmodem;
- return -1;
+ if (info->mode == xyzModem_zmodem)
+ {
+ *err = xyzModem_noZmodem;
+ return -1;
}
#endif
#ifdef REDBOOT
- /* Set up the I/O channel. Note: this allows for using a different port in the future */
- console_chan = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- if (info->chan >= 0) {
- CYGACC_CALL_IF_SET_CONSOLE_COMM(info->chan);
- } else {
- CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan);
+ /* Set up the I/O channel. Note: this allows for using a different port in the future */
+ console_chan =
+ CYGACC_CALL_IF_SET_CONSOLE_COMM
+ (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ if (info->chan >= 0)
+ {
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (info->chan);
}
- xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+ else
+ {
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
+ }
+ xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS ();
- CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan);
- CYGACC_COMM_IF_CONTROL(*xyz.__chan, __COMMCTL_SET_TIMEOUT, xyzModem_CHAR_TIMEOUT);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
+ CYGACC_COMM_IF_CONTROL (*xyz.__chan, __COMMCTL_SET_TIMEOUT,
+ xyzModem_CHAR_TIMEOUT);
#else
/* TODO: CHECK ! */
- int dummy;
- xyz.__chan=&dummy;
+ int dummy;
+ xyz.__chan = &dummy;
#endif
- xyz.len = 0;
- xyz.crc_mode = true;
- xyz.at_eof = false;
- xyz.tx_ack = false;
- xyz.mode = info->mode;
- xyz.total_retries = 0;
- xyz.total_SOH = 0;
- xyz.total_STX = 0;
- xyz.total_CAN = 0;
+ xyz.len = 0;
+ xyz.crc_mode = true;
+ xyz.at_eof = false;
+ xyz.tx_ack = false;
+ xyz.mode = info->mode;
+ xyz.total_retries = 0;
+ xyz.total_SOH = 0;
+ xyz.total_STX = 0;
+ xyz.total_CAN = 0;
#ifdef USE_YMODEM_LENGTH
- xyz.read_length = 0;
- xyz.file_length = 0;
+ xyz.read_length = 0;
+ xyz.file_length = 0;
#endif
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- if (xyz.mode == xyzModem_xmodem) {
- /* X-modem doesn't have an information header - exit here */
- xyz.next_blk = 1;
- return 0;
+ if (xyz.mode == xyzModem_xmodem)
+ {
+ /* X-modem doesn't have an information header - exit here */
+ xyz.next_blk = 1;
+ return 0;
}
- while (retries-- > 0) {
- stat = xyzModem_get_hdr();
- if (stat == 0) {
- /* Y-modem file information header */
- if (xyz.blk == 0) {
+ while (retries-- > 0)
+ {
+ stat = xyzModem_get_hdr ();
+ if (stat == 0)
+ {
+ /* Y-modem file information header */
+ if (xyz.blk == 0)
+ {
#ifdef USE_YMODEM_LENGTH
- /* skip filename */
- while (*xyz.bufp++);
- /* get the length */
- parse_num((char *)xyz.bufp, &xyz.file_length, NULL, " ");
+ /* skip filename */
+ while (*xyz.bufp++);
+ /* get the length */
+ parse_num ((char *) xyz.bufp, &xyz.file_length, NULL, " ");
#endif
- /* The rest of the file name data block quietly discarded */
- xyz.tx_ack = true;
- }
- xyz.next_blk = 1;
- xyz.len = 0;
- return 0;
- } else
- if (stat == xyzModem_timeout) {
- if (--crc_retries <= 0) xyz.crc_mode = false;
- CYGACC_CALL_IF_DELAY_US(5*100000); /* Extra delay for startup */
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- xyz.total_retries++;
- ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__));
- }
- if (stat == xyzModem_cancel) {
- break;
- }
+ /* The rest of the file name data block quietly discarded */
+ xyz.tx_ack = true;
+ }
+ xyz.next_blk = 1;
+ xyz.len = 0;
+ return 0;
+ }
+ else if (stat == xyzModem_timeout)
+ {
+ if (--crc_retries <= 0)
+ xyz.crc_mode = false;
+ CYGACC_CALL_IF_DELAY_US (5 * 100000); /* Extra delay for startup */
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+ xyz.total_retries++;
+ ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__));
+ }
+ if (stat == xyzModem_cancel)
+ {
+ break;
+ }
}
- *err = stat;
- ZM_DEBUG(zm_flush());
- return -1;
+ *err = stat;
+ ZM_DEBUG (zm_flush ());
+ return -1;
}
int
-xyzModem_stream_read(char *buf, int size, int *err)
+xyzModem_stream_read (char *buf, int size, int *err)
{
- int stat, total, len;
- int retries;
+ int stat, total, len;
+ int retries;
- total = 0;
- stat = xyzModem_cancel;
- /* Try and get 'size' bytes into the buffer */
- while (!xyz.at_eof && (size > 0)) {
- if (xyz.len == 0) {
- retries = xyzModem_MAX_RETRIES;
- while (retries-- > 0) {
- stat = xyzModem_get_hdr();
- if (stat == 0) {
- if (xyz.blk == xyz.next_blk) {
- xyz.tx_ack = true;
- ZM_DEBUG(zm_dprintf("ACK block %d (%d)\n", xyz.blk, __LINE__));
- xyz.next_blk = (xyz.next_blk + 1) & 0xFF;
+ total = 0;
+ stat = xyzModem_cancel;
+ /* Try and get 'size' bytes into the buffer */
+ while (!xyz.at_eof && (size > 0))
+ {
+ if (xyz.len == 0)
+ {
+ retries = xyzModem_MAX_RETRIES;
+ while (retries-- > 0)
+ {
+ stat = xyzModem_get_hdr ();
+ if (stat == 0)
+ {
+ if (xyz.blk == xyz.next_blk)
+ {
+ xyz.tx_ack = true;
+ ZM_DEBUG (zm_dprintf
+ ("ACK block %d (%d)\n", xyz.blk, __LINE__));
+ xyz.next_blk = (xyz.next_blk + 1) & 0xFF;
#if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH)
- if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0) {
+ if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0)
+ {
#else
- if (1) {
+ if (1)
+ {
#endif
- /* Data blocks can be padded with ^Z (EOF) characters */
- /* This code tries to detect and remove them */
- if ((xyz.bufp[xyz.len-1] == EOF) &&
- (xyz.bufp[xyz.len-2] == EOF) &&
- (xyz.bufp[xyz.len-3] == EOF)) {
- while (xyz.len && (xyz.bufp[xyz.len-1] == EOF)) {
- xyz.len--;
- }
- }
- }
+ /* Data blocks can be padded with ^Z (EOF) characters */
+ /* This code tries to detect and remove them */
+ if ((xyz.bufp[xyz.len - 1] == EOF) &&
+ (xyz.bufp[xyz.len - 2] == EOF) &&
+ (xyz.bufp[xyz.len - 3] == EOF))
+ {
+ while (xyz.len
+ && (xyz.bufp[xyz.len - 1] == EOF))
+ {
+ xyz.len--;
+ }
+ }
+ }
#ifdef USE_YMODEM_LENGTH
- /*
- * See if accumulated length exceeds that of the file.
- * If so, reduce size (i.e., cut out pad bytes)
- * Only do this for Y-modem (and Z-modem should it ever
- * be supported since it can fall back to Y-modem mode).
- */
- if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length) {
- xyz.read_length += xyz.len;
- if (xyz.read_length > xyz.file_length) {
- xyz.len -= (xyz.read_length - xyz.file_length);
- }
- }
+ /*
+ * See if accumulated length exceeds that of the file.
+ * If so, reduce size (i.e., cut out pad bytes)
+ * Only do this for Y-modem (and Z-modem should it ever
+ * be supported since it can fall back to Y-modem mode).
+ */
+ if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length)
+ {
+ xyz.read_length += xyz.len;
+ if (xyz.read_length > xyz.file_length)
+ {
+ xyz.len -= (xyz.read_length - xyz.file_length);
+ }
+ }
#endif
- break;
- } else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF)) {
- /* Just re-ACK this so sender will get on with it */
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- continue; /* Need new header */
- } else {
- stat = xyzModem_sequence;
- }
- }
- if (stat == xyzModem_cancel) {
- break;
- }
- if (stat == xyzModem_eof) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- ZM_DEBUG(zm_dprintf("ACK (%d)\n", __LINE__));
- if (xyz.mode == xyzModem_ymodem) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- xyz.total_retries++;
- ZM_DEBUG(zm_dprintf("Reading Final Header\n"));
- stat = xyzModem_get_hdr();
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- ZM_DEBUG(zm_dprintf("FINAL ACK (%d)\n", __LINE__));
- }
- xyz.at_eof = true;
- break;
- }
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- xyz.total_retries++;
- ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__));
- }
- if (stat < 0) {
- *err = stat;
- xyz.len = -1;
- return total;
- }
- }
- /* Don't "read" data from the EOF protocol package */
- if (!xyz.at_eof) {
- len = xyz.len;
- if (size < len) len = size;
- memcpy(buf, xyz.bufp, len);
- size -= len;
- buf += len;
- total += len;
- xyz.len -= len;
- xyz.bufp += len;
- }
+ break;
+ }
+ else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF))
+ {
+ /* Just re-ACK this so sender will get on with it */
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ continue; /* Need new header */
+ }
+ else
+ {
+ stat = xyzModem_sequence;
+ }
+ }
+ if (stat == xyzModem_cancel)
+ {
+ break;
+ }
+ if (stat == xyzModem_eof)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ ZM_DEBUG (zm_dprintf ("ACK (%d)\n", __LINE__));
+ if (xyz.mode == xyzModem_ymodem)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan,
+ (xyz.crc_mode ? 'C' : NAK));
+ xyz.total_retries++;
+ ZM_DEBUG (zm_dprintf ("Reading Final Header\n"));
+ stat = xyzModem_get_hdr ();
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ ZM_DEBUG (zm_dprintf ("FINAL ACK (%d)\n", __LINE__));
+ }
+ xyz.at_eof = true;
+ break;
+ }
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+ xyz.total_retries++;
+ ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__));
+ }
+ if (stat < 0)
+ {
+ *err = stat;
+ xyz.len = -1;
+ return total;
+ }
+ }
+ /* Don't "read" data from the EOF protocol package */
+ if (!xyz.at_eof)
+ {
+ len = xyz.len;
+ if (size < len)
+ len = size;
+ memcpy (buf, xyz.bufp, len);
+ size -= len;
+ buf += len;
+ total += len;
+ xyz.len -= len;
+ xyz.bufp += len;
+ }
}
- return total;
+ return total;
}
void
-xyzModem_stream_close(int *err)
+xyzModem_stream_close (int *err)
{
- diag_printf("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n",
- xyz.crc_mode ? "CRC" : "Cksum",
- xyz.total_SOH, xyz.total_STX, xyz.total_CAN,
- xyz.total_retries);
- ZM_DEBUG(zm_flush());
+ diag_printf
+ ("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n",
+ xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX,
+ xyz.total_CAN, xyz.total_retries);
+ ZM_DEBUG (zm_flush ());
}
/* Need to be able to clean out the input buffer, so have to take the */
/* getc */
-void xyzModem_stream_terminate(bool abort, int (*getc)(void))
+void
+xyzModem_stream_terminate (bool abort, int (*getc) (void))
{
int c;
- if (abort) {
- ZM_DEBUG(zm_dprintf("!!!! TRANSFER ABORT !!!!\n"));
- switch (xyz.mode) {
+ if (abort)
+ {
+ ZM_DEBUG (zm_dprintf ("!!!! TRANSFER ABORT !!!!\n"));
+ switch (xyz.mode)
+ {
case xyzModem_xmodem:
case xyzModem_ymodem:
/* The X/YMODEM Spec seems to suggest that multiple CAN followed by an equal */
/* number of Backspaces is a friendly way to get the other end to abort. */
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
/* Now consume the rest of what's waiting on the line. */
- ZM_DEBUG(zm_dprintf("Flushing serial line.\n"));
- xyzModem_flush();
- xyz.at_eof = true;
- break;
+ ZM_DEBUG (zm_dprintf ("Flushing serial line.\n"));
+ xyzModem_flush ();
+ xyz.at_eof = true;
+ break;
#ifdef xyzModem_zmodem
case xyzModem_zmodem:
/* Might support it some day I suppose. */
#endif
- break;
- }
- } else {
- ZM_DEBUG(zm_dprintf("Engaging cleanup mode...\n"));
+ break;
+ }
+ }
+ else
+ {
+ ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
/*
* Consume any trailing crap left in the inbuffer from
* previous recieved blocks. Since very few files are an exact multiple
* of the transfer block size, there will almost always be some gunk here.
* If we don't eat it now, RedBoot will think the user typed it.
*/
- ZM_DEBUG(zm_dprintf("Trailing gunk:\n"));
- while ((c = (*getc)()) > -1) ;
- ZM_DEBUG(zm_dprintf("\n"));
+ ZM_DEBUG (zm_dprintf ("Trailing gunk:\n"));
+ while ((c = (*getc) ()) > -1);
+ ZM_DEBUG (zm_dprintf ("\n"));
/*
* Make a small delay to give terminal programs like minicom
* time to get control again after their file transfer program
* exits.
*/
- CYGACC_CALL_IF_DELAY_US((cyg_int32)250000);
- }
+ CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);
+ }
}
char *
-xyzModem_error(int err)
+xyzModem_error (int err)
{
- switch (err) {
+ switch (err)
+ {
case xyzModem_access:
- return "Can't access file";
- break;
+ return "Can't access file";
+ break;
case xyzModem_noZmodem:
- return "Sorry, zModem not available yet";
- break;
+ return "Sorry, zModem not available yet";
+ break;
case xyzModem_timeout:
- return "Timed out";
- break;
+ return "Timed out";
+ break;
case xyzModem_eof:
- return "End of file";
- break;
+ return "End of file";
+ break;
case xyzModem_cancel:
- return "Cancelled";
- break;
+ return "Cancelled";
+ break;
case xyzModem_frame:
- return "Invalid framing";
- break;
+ return "Invalid framing";
+ break;
case xyzModem_cksum:
- return "CRC/checksum error";
- break;
+ return "CRC/checksum error";
+ break;
case xyzModem_sequence:
- return "Block sequence error";
- break;
+ return "Block sequence error";
+ break;
default:
- return "Unknown error";
- break;
+ return "Unknown error";
+ break;
}
}
/*
* RedBoot interface
*/
-#if 0 /* SB */
-GETC_IO_FUNCS(xyzModem_io, xyzModem_stream_open, xyzModem_stream_close,
- xyzModem_stream_terminate, xyzModem_stream_read, xyzModem_error);
-RedBoot_load(xmodem, xyzModem_io, false, false, xyzModem_xmodem);
-RedBoot_load(ymodem, xyzModem_io, false, false, xyzModem_ymodem);
+#if 0 /* SB */
+GETC_IO_FUNCS (xyzModem_io, xyzModem_stream_open, xyzModem_stream_close,
+ xyzModem_stream_terminate, xyzModem_stream_read,
+ xyzModem_error);
+RedBoot_load (xmodem, xyzModem_io, false, false, xyzModem_xmodem);
+RedBoot_load (ymodem, xyzModem_io, false, false, xyzModem_ymodem);
#endif
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 1c4370b..d0a7341 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -149,7 +149,7 @@
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
* after we are running a stack in RAM, we have troubles. Besides,
- * these refresh and delay values are better ? simply specified
+ * these refresh and delay values are better ? simply specified
* outright in the include/configs/{cfg} file since the HW designer
* simply dictates it.
*/
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index e1fa37a..8fc713d 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -462,7 +462,7 @@
#if defined CFG_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
- movl $DRCTMCTL, %edi
+ movl $DRCTMCTL, %edi
movb $CFG_SDRAM_DRCTMCTL,%al
movb (%edi), %al
#else
@@ -477,7 +477,7 @@
#ifdef CFG_SDRAM_CAS_LATENCY_3T
orb $0x10, %al
#endif
- movb %al, (%edi)
+ movb %al, (%edi)
#endif
#endif
movl $DRCCTL, %edi /* DRAM Control register */
@@ -537,7 +537,7 @@
movl %eax, %ebx
-done:
+done:
movl %ebx, %eax
#if CFG_SDRAM_ECC_ENABLE
@@ -547,7 +547,7 @@
movl $0x1, %edi
memtest0:
movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
+ cmpb $0xa5, (%edi)
jne out
shrl $1, %ecx
andl %ecx,%ecx
@@ -571,11 +571,11 @@
/* enable NMI mapping for ECC */
movl $ECCINT, %edi
mov $0x10, %al
- movb %al, (%edi)
+ movb %al, (%edi)
/* Turn on ECC */
movl $ECCCTL, %edi
mov $0x05, %al
- movb %al, (%edi)
+ movb %al, (%edi)
#endif
out:
movl %ebx, %eax
diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c
index 6db6214..b6540b5 100644
--- a/cpu/mcf52x2/fec.c
+++ b/cpu/mcf52x2/fec.c
@@ -267,6 +267,7 @@
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
#endif
+#endif
/* Set maximum receive buffer size.
*/
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 8a83ca5..f1f4077 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -140,6 +140,7 @@
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
+#if defined(CONFIG_M5282)
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
@@ -171,6 +172,7 @@
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif
+#endif
/* if we come from a pre-loader we have no exception table and
* therefore no VBR to set
*/
diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c
index 7bacecd..7b5cb8b 100644
--- a/cpu/mpc5xxx/interrupts.c
+++ b/cpu/mpc5xxx/interrupts.c
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2006
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de
+ *
* (C) Copyright -2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -24,18 +27,212 @@
* MA 02111-1307 USA
*/
-/*
- * interrupts.c - just enough support for the decrementer/timer
+/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the
+ * Linux 2.6 source with the following copyright.
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
*/
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
-int interrupt_init_cpu (ulong *decrementer_count)
+struct irq_action {
+ interrupt_handler_t *handler;
+ void *arg;
+ ulong count;
+};
+
+static struct irq_action irq_handlers[NR_IRQS];
+
+static struct mpc5xxx_intr *intr;
+static struct mpc5xxx_sdma *sdma;
+
+static void mpc5xxx_ic_disable(unsigned int irq)
+{
+ u32 val;
+
+ if (irq == MPC5XXX_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_IRQ1) {
+ BUG();
+ } else if (irq <= MPC5XXX_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc5xxx_ic_enable(unsigned int irq)
+{
+ u32 val;
+
+ if (irq == MPC5XXX_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_IRQ1) {
+ BUG();
+ } else if (irq <= MPC5XXX_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc5xxx_ic_ack(unsigned int irq)
+{
+ u32 val;
+
+ /*
+ * Only some irqs are reset here, others in interrupting hardware.
+ */
+
+ switch (irq) {
+ case MPC5XXX_IRQ0:
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC5XXX_CCS_IRQ:
+ val = in_be32(&intr->enc_status);
+ val |= 0x00000400;
+ out_be32(&intr->enc_status, val);
+ break;
+ case MPC5XXX_IRQ1:
+ val = in_be32(&intr->ctrl);
+ val |= 0x04000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC5XXX_IRQ2:
+ val = in_be32(&intr->ctrl);
+ val |= 0x02000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC5XXX_IRQ3:
+ val = in_be32(&intr->ctrl);
+ val |= 0x01000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ default:
+ if (irq >= MPC5XXX_SDMA_IRQ_BASE
+ && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
+ out_be32(&sdma->IntPend,
+ 1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+ }
+ break;
+ }
+}
+
+static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
+{
+ mpc5xxx_ic_disable(irq);
+ mpc5xxx_ic_ack(irq);
+}
+
+static void mpc5xxx_ic_end(unsigned int irq)
+{
+ mpc5xxx_ic_enable(irq);
+}
+
+void mpc5xxx_init_irq(void)
+{
+ u32 intr_ctrl;
+
+ /* Remap the necessary zones */
+ intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+ sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00ff0000 | /* IRQ 0-3 level sensitive low active */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+}
+
+int mpc5xxx_get_irq(struct pt_regs *regs)
+{
+ u32 status;
+ int irq = -1;
+
+ status = in_be32(&intr->enc_status);
+
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq += MPC5XXX_CRIT_IRQ_BASE;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq += MPC5XXX_MAIN_IRQ_BASE;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
+ } else
+ irq += MPC5XXX_PERP_IRQ_BASE;
+ }
+
+ return irq;
+}
+
+/****************************************************************************/
+
+int interrupt_init_cpu(ulong * decrementer_count)
{
*decrementer_count = get_tbclk() / CFG_HZ;
+ mpc5xxx_init_irq();
+
return (0);
}
@@ -44,14 +241,32 @@
/*
* Handle external interrupts
*/
-void
-external_interrupt(struct pt_regs *regs)
+void external_interrupt(struct pt_regs *regs)
{
- puts("external_interrupt (oops!)\n");
+ int irq, unmask = 1;
+
+ irq = mpc5xxx_get_irq(regs);
+
+ mpc5xxx_ic_disable_and_ack(irq);
+
+ enable_interrupts();
+
+ if (irq_handlers[irq].handler != NULL)
+ (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
+ else {
+ printf("\nBogus External Interrupt IRQ %d\n", irq);
+ /*
+ * turn off the bogus interrupt, otherwise it
+ * might repeat forever
+ */
+ unmask = 0;
+ }
+
+ if (unmask)
+ mpc5xxx_ic_end(irq);
}
-void
-timer_interrupt_cpu (struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
{
/* nothing to do here */
return;
@@ -63,22 +278,69 @@
* Install and free a interrupt handler.
*/
-void
-irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
{
+ if (irq < 0 || irq >= NR_IRQS) {
+ printf("irq_install_handler: bad irq number %d\n", irq);
+ return;
+ }
+ if (irq_handlers[irq].handler != NULL)
+ printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
+ (ulong) handler, (ulong) irq_handlers[irq].handler);
+
+ irq_handlers[irq].handler = handler;
+ irq_handlers[irq].arg = arg;
+
+ mpc5xxx_ic_enable(irq);
}
-void
-irq_free_handler(int vec)
+void irq_free_handler(int irq)
{
+ if (irq < 0 || irq >= NR_IRQS) {
+ printf("irq_free_handler: bad irq number %d\n", irq);
+ return;
+ }
+ mpc5xxx_ic_disable(irq);
+
+ irq_handlers[irq].handler = NULL;
+ irq_handlers[irq].arg = NULL;
}
/****************************************************************************/
-void
-do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
+void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
- puts("IRQ related functions are unimplemented currently.\n");
+ int irq, re_enable;
+ u32 intr_ctrl;
+ char *irq_config[] = { "level sensitive, active high",
+ "edge sensitive, rising active edge",
+ "edge sensitive, falling active edge",
+ "level sensitive, active low"
+ };
+
+ re_enable = disable_interrupts();
+
+ intr_ctrl = in_be32(&intr->ctrl);
+ printf("Interrupt configuration:\n");
+
+ for (irq = 0; irq <= 3; irq++) {
+ printf("IRQ%d: %s\n", irq,
+ irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
+ }
+
+ puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
+
+ for (irq = 0; irq < NR_IRQS; irq++)
+ if (irq_handlers[irq].handler != NULL)
+ printf("%02d %08lx %08lx %ld\n", irq,
+ (ulong) irq_handlers[irq].handler,
+ (ulong) irq_handlers[irq].arg,
+ irq_handlers[irq].count);
+
+ if (re_enable)
+ enable_interrupts();
}
+#endif
diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index 6cb523d..430d63f 100644
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -166,6 +166,25 @@
}
#if defined(CONFIG_SERIAL_MULTI)
+void serial_putc_raw_dev(unsigned long dev_base, const char c)
+#else
+void serial_putc_raw(const char c)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+ /* Wait for last character to go. */
+ while (!(psc->psc_status & PSC_SR_TXEMP))
+ ;
+
+ psc->psc_buffer_8 = c;
+}
+
+
+#if defined(CONFIG_SERIAL_MULTI)
void serial_puts_dev (unsigned long dev_base, const char *s)
#else
void serial_puts (const char *s)
@@ -240,6 +259,43 @@
}
#if defined(CONFIG_SERIAL_MULTI)
+void serial_setrts_dev (unsigned long dev_base, int s)
+#else
+void serial_setrts(int s)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+
+ if (s) {
+ /* Assert RTS (become LOW) */
+ psc->op1 = 0x1;
+ }
+ else {
+ /* Negate RTS (become HIGH) */
+ psc->op0 = 0x1;
+ }
+}
+
+#if defined(CONFIG_SERIAL_MULTI)
+int serial_getcts_dev (unsigned long dev_base)
+#else
+int serial_getcts(void)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+
+ return (psc->ip & 0x1) ? 0 : 1;
+}
+
+#if defined(CONFIG_SERIAL_MULTI)
int serial0_init(void)
{
return (serial_init_dev(PSC_BASE));
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index 2e920aa..6130cd2 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -169,7 +169,7 @@
break;
}
utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
-
+
/*
* Set buffer allocations and then assert VRB and TXE.
*/
@@ -270,7 +270,7 @@
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
udelay(3);
- while(time_out) {
+ while (time_out) {
if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
time_out--;
udelay(1);
@@ -284,6 +284,40 @@
return 0;
}
+/*
+ * Yucca board as End point and root point setup
+ * and
+ * testing inbound and out bound windows
+ *
+ * YUCCA board can be plugged into another yucca board or you can get PCI-E
+ * cable which can be used to setup loop back from one port to another port.
+ * Please rememeber that unless there is a endpoint plugged in to root port it
+ * will not initialize. It is the same in case of endpoint , unless there is
+ * root port attached it will not initialize.
+ *
+ * In this release of software all the PCI-E ports are configured as either
+ * endpoint or rootpoint.In future we will have support for selective ports
+ * setup as endpoint and root point in single board.
+ *
+ * Once your board came up as root point , you can verify by reading
+ * /proc/bus/pci/devices. Where you can see the configuration registers
+ * of end point device attached to the port.
+ *
+ * Enpoint cofiguration can be verified by connecting Yucca board to any
+ * host or another yucca board. Then try to scan the device. In case of
+ * linux use "lspci" or appripriate os command.
+ *
+ * How do I verify the inbound and out bound windows ?(yucca to yucca)
+ * in this configuration inbound and outbound windows are setup to access
+ * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
+ * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
+ * This is waere your POM(PLB out bound memory window) mapped. then
+ * read the data from other yucca board's u-boot prompt at address
+ * 0x9000 0000(SRAM). Data should match.
+ * In case of inbound , write data to u-boot command prompt at 0xb000 0000
+ * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
+ * data at 0x9000 0000(SRAM).Data should match.
+ */
int ppc440spe_init_pcie_rootport(int port)
{
static int core_init;
@@ -326,7 +360,7 @@
SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
SDR_WRITE(PESDR0_RCSSET,
- (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 1:
@@ -339,7 +373,7 @@
SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR1_RCSSET,
- (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 2:
@@ -352,7 +386,7 @@
SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR2_RCSSET,
- (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
}
/*
@@ -362,9 +396,15 @@
mdelay(100);
switch (port) {
- case 0: val = SDR_READ(PESDR0_RCSSTS); break;
- case 1: val = SDR_READ(PESDR1_RCSSTS); break;
- case 2: val = SDR_READ(PESDR2_RCSSTS); break;
+ case 0:
+ val = SDR_READ(PESDR0_RCSSTS);
+ break;
+ case 1:
+ val = SDR_READ(PESDR1_RCSSTS);
+ break;
+ case 2:
+ val = SDR_READ(PESDR2_RCSSTS);
+ break;
}
if (val & (1 << 20)) {
@@ -376,17 +416,16 @@
* Verify link is up
*/
val = 0;
- switch (port)
- {
- case 0:
- val = SDR_READ(PESDR0_LOOP);
- break;
- case 1:
- val = SDR_READ(PESDR1_LOOP);
- break;
- case 2:
- val = SDR_READ(PESDR2_LOOP);
- break;
+ switch (port) {
+ case 0:
+ val = SDR_READ(PESDR0_LOOP);
+ break;
+ case 1:
+ val = SDR_READ(PESDR1_LOOP);
+ break;
+ case 2:
+ val = SDR_READ(PESDR2_LOOP);
+ break;
}
if (!(val & 0x00001000)) {
printf("PCIE%d: link is not up.\n", port);
@@ -498,29 +537,246 @@
return 0;
}
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
+int ppc440spe_init_pcie_endport(int port)
+{
+ static int core_init;
+ volatile u32 val = 0;
+ int attempts;
+
+ if (!core_init) {
+ ++core_init;
+ if (ppc440spe_init_pcie())
+ return -1;
+ }
+
+ /*
+ * Initialize various parts of the PCI Express core for our port:
+ *
+ * - Set as a end port and enable max width
+ * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
+ * - Set up UTL configuration.
+ * - Increase SERDES drive strength to levels suggested by AMCC.
+ * - De-assert RSTPYN, RSTDL and RSTGU.
+ *
+ * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
+ * default setting 0x11310000. The register has new fields,
+ * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
+ * hang.
+ */
+ switch (port) {
+ case 0:
+ SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
+
+ SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
+ SDR_WRITE(PESDR0_RCSSET,
+ (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+
+ case 1:
+ SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
+ SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR1_RCSSET,
+ (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+
+ case 2:
+ SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
+ SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR2_RCSSET,
+ (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+ }
+ /*
+ * Notice: the following delay has critical impact on device
+ * initialization - if too short (<50ms) the link doesn't get up.
+ */
+ mdelay(100);
+
+ switch (port) {
+ case 0: val = SDR_READ(PESDR0_RCSSTS); break;
+ case 1: val = SDR_READ(PESDR1_RCSSTS); break;
+ case 2: val = SDR_READ(PESDR2_RCSSTS); break;
+ }
+
+ if (val & (1 << 20)) {
+ printf("PCIE%d: PGRST failed %08x\n", port, val);
+ return -1;
+ }
+
+ /*
+ * Verify link is up
+ */
+ val = 0;
+ switch (port)
+ {
+ case 0:
+ val = SDR_READ(PESDR0_LOOP);
+ break;
+ case 1:
+ val = SDR_READ(PESDR1_LOOP);
+ break;
+ case 2:
+ val = SDR_READ(PESDR2_LOOP);
+ break;
+ }
+ if (!(val & 0x00001000)) {
+ printf("PCIE%d: link is not up.\n", port);
+ return -1;
+ }
+
+ /*
+ * Setup UTL registers - but only on revA!
+ * We use default settings for revB chip.
+ */
+ if (!ppc440spe_revB())
+ ppc440spe_setup_utl(port);
+
+ /*
+ * We map PCI Express configuration access into the 512MB regions
+ *
+ * NOTICE: revB is very strict about PLB real addressess and ranges to
+ * be mapped for config space; it seems to only work with d_nnnn_nnnn
+ * range (hangs the core upon config transaction attempts when set
+ * otherwise) while revA uses c_nnnn_nnnn.
+ *
+ * For revA:
+ * PCIE0: 0xc_4000_0000
+ * PCIE1: 0xc_8000_0000
+ * PCIE2: 0xc_c000_0000
+ *
+ * For revB:
+ * PCIE0: 0xd_0000_0000
+ * PCIE1: 0xd_2000_0000
+ * PCIE2: 0xd_4000_0000
+ */
+ switch (port) {
+ case 0:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
+ } else {
+ /* revA */
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
+ break;
+
+ case 1:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
+ } else {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
+ break;
+
+ case 2:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
+ } else {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
+ break;
+ }
+
+ /*
+ * Check for VC0 active and assert RDY.
+ */
+ attempts = 10;
+ switch (port) {
+ case 0:
+ while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE0: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
+ break;
+ case 1:
+ while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE1: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
+ SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
+ break;
+ case 2:
+ while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE2: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
+ SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
+ break;
+ }
+ mdelay(100);
+
+ return 0;
+}
+
+void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
+ volatile void *rmbase = NULL;
pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
- switch(port) {
+ switch (port) {
case 0:
mbase = (u32 *)CFG_PCIE0_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE0_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
break;
case 1:
mbase = (u32 *)CFG_PCIE1_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE1_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
break;
case 2:
mbase = (u32 *)CFG_PCIE2_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE2_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
break;
}
@@ -528,14 +784,9 @@
/*
* Set bus numbers on our root port
*/
- if (ppc440spe_revB()) {
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
- out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
- } else {
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
- }
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+ out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
/*
* Set up outbound translation to hose->mem_space from PLB
@@ -544,8 +795,7 @@
* subregions and to enable the outbound translation.
*/
out_le32(mbase + PECFG_POM0LAH, 0x00000000);
- out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE));
+ out_le32(mbase + PECFG_POM0LAL, 0x00000000);
switch (port) {
case 0:
@@ -579,14 +829,134 @@
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
out_le32(mbase + PECFG_BAR0LMPA, 0);
+
+ out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
+ out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
out_le32(mbase + PECFG_PIM0LAL, 0);
out_le32(mbase + PECFG_PIM0LAH, 0);
+ out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ printf("PCIE:%d successfully set as rootpoint\n",port);
+}
+
+int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
+{
+ volatile void *mbase = NULL;
+ int attempts = 0;
+
+ pci_set_ops(hose,
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
+
+ switch (port) {
+ case 0:
+ mbase = (u32 *)CFG_PCIE0_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+ break;
+ case 1:
+ mbase = (u32 *)CFG_PCIE1_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+ break;
+ case 2:
+ mbase = (u32 *)CFG_PCIE2_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+ break;
+ }
+
+ /*
+ * Set up outbound translation to hose->mem_space from PLB
+ * addresses at an offset of 0xd_0000_0000. We set the low
+ * bits of the mask to 11 to turn off splitting into 8
+ * subregions and to enable the outbound translation.
+ */
+ out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
+ out_le32(mbase + PECFG_POM0LAL, 0x00001000);
+
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ case 1:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE));
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ case 2:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE));
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ }
+
+ /* Set up 16GB inbound memory window at 0 */
+ out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
+ out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
+ out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
+ out_le32(mbase + PECFG_BAR0LMPA, 0);
+ out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
+ out_le32(mbase + PECFG_PIMEN, 0x1);
+
+ /* Enable I/O, Mem, and Busmaster cycles */
+ out_le16((u16 *)(mbase + PCI_COMMAND),
+ in_le16((u16 *)(mbase + PCI_COMMAND)) |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
+ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
+ attempts = 10;
+ switch (port) {
+ case 0:
+ while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
+ if (!(attempts--)) {
+ printf("PCIE0: BMEN is not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ break;
+ case 1:
+ while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
+ if (!(attempts--)) {
+ printf("PCIE1: BMEN is not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ break;
+ case 2:
+ while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
+ if (!(attempts--)) {
+ printf("PCIE2: BMEN is not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ break;
+ }
+ printf("PCIE:%d successfully set as endpoint\n",port);
+
+ return 0;
}
#endif /* CONFIG_PCI */
#endif /* CONFIG_440SPE */
diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h
index 47df762..2becc77 100644
--- a/cpu/ppc4xx/440spe_pcie.h
+++ b/cpu/ppc4xx/440spe_pcie.h
@@ -139,9 +139,17 @@
*/
#define PECFG_BAR0LMPA 0x210
#define PECFG_BAR0HMPA 0x214
+#define PECFG_BAR1MPA 0x218
+#define PECFG_BAR2MPA 0x220
+
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
#define PECFG_PIM0LAH 0x344
+#define PECFG_PIM1LAL 0x348
+#define PECFG_PIM1LAH 0x34c
+#define PECFG_PIM01SAL 0x350
+#define PECFG_PIM01SAH 0x354
+
#define PECFG_POM0LAL 0x380
#define PECFG_POM0LAH 0x384
@@ -156,7 +164,8 @@
int ppc440spe_init_pcie(void);
int ppc440spe_init_pcie_rootport(int port);
void yucca_setup_pcie_fpga_rootpoint(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
+void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port);
+int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port);
int yucca_pcie_card_present(int port);
int pcie_hose_scan(struct pci_controller *hose, int bus);
#endif /* __440SPE_PCIE_H */
diff --git a/drivers/ns9750_serial.c b/drivers/ns9750_serial.c
index 8dff367..02c0d39 100644
--- a/drivers/ns9750_serial.c
+++ b/drivers/ns9750_serial.c
@@ -35,6 +35,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if !defined(CONFIG_CONS_INDEX)
+#error "No console index specified."
+#endif
+
#define CONSOLE CONFIG_CONS_INDEX
static unsigned int calcBitrateRegister( void );
diff --git a/drivers/serial.c b/drivers/serial.c
index 228781b..8d1ae96 100644
--- a/drivers/serial.c
+++ b/drivers/serial.c
@@ -30,10 +30,20 @@
#include <ns87308.h>
#endif
+#if defined (CONFIG_SERIAL_MULTI)
+#include <serial.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_CONS_INDEX)
+#if defined (CONFIG_SERIAL_MULTI)
+/* with CONFIG_SERIAL_MULTI we might have no console
+ * on these devices
+ */
+#else
#error "No console index specified."
+#endif /* CONFIG_SERIAL_MULTI */
#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
#error "Invalid console index value."
#endif
@@ -75,7 +85,42 @@
};
#define PORT serial_ports[port-1]
+#if defined(CONFIG_CONS_INDEX)
#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1])
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+ int eserial##port##_init (void) {\
+ int clock_divisor; \
+ clock_divisor = calc_divisor(serial_ports[port-1]); \
+ NS16550_init(serial_ports[port-1], clock_divisor); \
+ return(0);}\
+ void eserial##port##_setbrg (void) {\
+ serial_setbrg_dev(port);}\
+ int eserial##port##_getc (void) {\
+ return serial_getc_dev(port);}\
+ int eserial##port##_tstc (void) {\
+ return serial_tstc_dev(port);}\
+ void eserial##port##_putc (const char c) {\
+ serial_putc_dev(port, c);}\
+ void eserial##port##_puts (const char *s) {\
+ serial_puts_dev(port, s);}
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port,name,bus) {\
+ name,\
+ bus,\
+ eserial##port##_init,\
+ eserial##port##_setbrg,\
+ eserial##port##_getc,\
+ eserial##port##_tstc,\
+ eserial##port##_putc,\
+ eserial##port##_puts, }
+
+#endif /* CONFIG_SERIAL_MULTI */
static int calc_divisor (NS16550_t port)
{
@@ -103,6 +148,7 @@
}
+#if !defined(CONFIG_SERIAL_MULTI)
int serial_init (void)
{
int clock_divisor;
@@ -130,6 +176,7 @@
return (0);
}
+#endif
void
_serial_putc(const char c,const int port)
@@ -176,40 +223,104 @@
NS16550_reinit(PORT, clock_divisor);
}
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_putc_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc(c,dev_index);
+}
+#else
void
serial_putc(const char c)
{
_serial_putc(c,CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_putc_raw_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc_raw(c,dev_index);
+}
+#else
void
serial_putc_raw(const char c)
{
_serial_putc_raw(c,CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_puts_dev(unsigned int dev_index,const char *s)
+{
+ _serial_puts(s,dev_index);
+}
+#else
void
serial_puts(const char *s)
{
_serial_puts(s,CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int
+serial_getc_dev(unsigned int dev_index)
+{
+ return _serial_getc(dev_index);
+}
+#else
int
serial_getc(void)
{
return _serial_getc(CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int
+serial_tstc_dev(unsigned int dev_index)
+{
+ return _serial_tstc(dev_index);
+}
+#else
int
serial_tstc(void)
{
return _serial_tstc(CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_setbrg_dev(unsigned int dev_index)
+{
+ _serial_setbrg(dev_index);
+}
+#else
void
serial_setbrg(void)
{
_serial_setbrg(CONFIG_CONS_INDEX);
}
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device eserial1_device =
+ INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1");
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device eserial2_device =
+ INIT_ESERIAL_STRUCTURE(2,"eserial1","EUART2");
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device eserial3_device =
+ INIT_ESERIAL_STRUCTURE(3,"eserial2","EUART3");
+DECLARE_ESERIAL_FUNCTIONS(4);
+struct serial_device eserial4_device =
+ INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4");
+#endif /* CONFIG_SERIAL_MULTI */
#endif
diff --git a/examples/Makefile b/examples/Makefile
index 85118ea..d7cd843 100644
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -94,6 +94,12 @@
BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr
endif
+# Demo for 52xx IRQs
+ifeq ($(CPU),mpc5xxx)
+SREC += interrupt.srec
+BIN += interrupt.bin interrupt
+endif
+
# Utility for resetting i82559 EEPROM
ifeq ($(BOARD),oxc)
SREC += eepro100_eeprom.srec
diff --git a/examples/interrupt.c b/examples/interrupt.c
new file mode 100644
index 0000000..f3061d1
--- /dev/null
+++ b/examples/interrupt.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2006
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This is a very simple standalone application demonstrating
+ * catching IRQs on the MPC52xx architecture.
+ *
+ * The interrupt to be intercepted can be specified as an argument
+ * to the application. Specifying nothing will intercept IRQ1 on the
+ * MPC5200 platform. On the CR825 carrier board from MicroSys this
+ * maps to the ABORT switch :)
+ *
+ * Note that the specified vector is only a logical number specified
+ * by the respective header file.
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <config.h>
+
+#if defined(CONFIG_MPC5xxx)
+#define DFL_IRQ MPC5XXX_IRQ1
+#else
+#define DFL_IRQ 0
+#endif
+
+static void irq_handler (void *arg);
+
+int interrupt (int argc, char *argv[])
+{
+ int c, irq = -1;
+
+ app_startup (argv);
+
+ if (argc > 1)
+ irq = simple_strtoul (argv[1], NULL, 0);
+ if ((irq < 0) || (irq > NR_IRQS))
+ irq = DFL_IRQ;
+
+ printf ("Installing handler for irq vector %d and doing busy wait\n",
+ irq);
+ printf ("Press 'q' to quit\n");
+
+ /* Install interrupt handler */
+ install_hdlr (irq, irq_handler, NULL);
+ while ((c = getc ()) != 'q') {
+ printf ("Ok, ok, I am still alive!\n");
+ }
+
+ free_hdlr (irq);
+ printf ("\nInterrupt handler has been uninstalled\n");
+
+ return (0);
+}
+
+/*
+ * Handler for interrupt
+ */
+static void irq_handler (void *arg)
+{
+ /* just for demonstration */
+ printf ("+");
+}
diff --git a/include/_exports.h b/include/_exports.h
index 61dcaaf..2b8ec3d 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -12,6 +12,9 @@
EXPORT_FUNC(get_timer)
EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
+EXPORT_FUNC(getenv)
+EXPORT_FUNC(setenv)
+EXPORT_FUNC(simple_strtoul)
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)
diff --git a/include/common.h b/include/common.h
index 9a19001..bee2fb7 100644
--- a/include/common.h
+++ b/include/common.h
@@ -109,6 +109,12 @@
#define debugX(level,fmt,args...)
#endif /* DEBUG */
+#define BUG() do { \
+ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+ panic("BUG!"); \
+} while (0)
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+
typedef void (interrupt_handler_t)(void *);
#include <asm/u-boot.h> /* boot information for Linux kernel */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 7a1dada..ce969ec 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -527,7 +527,7 @@
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
-
+
/*
* Init Memory Controller:
*
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index df3d68e..0c935bf 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -37,12 +37,12 @@
#define CONFIG_MISC_INIT_R
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
@@ -72,12 +72,15 @@
*/
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
-#undef CONFIG_PSC_CONSOLE
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
+#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#endif
-#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
+#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
+ !defined(CONFIG_SERIAL_MULTI)
#error "Select only one console device!"
#endif
#define CONFIG_BAUDRATE 115200
@@ -89,7 +92,7 @@
/* USB */
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/*
@@ -115,15 +118,15 @@
#undef CONFIG_BOOTARGS
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
#ifdef CONFIG_PRS200
-# define CFG__BOARDNAME "prs200"
-# define LINUX_CONSOLE "ttyS0"
+# define CFG__BOARDNAME "prs200"
+# define CFG__LINUX_CONSOLE "ttyS0"
#else
-# define CFG__BOARDNAME "mcc200"
-# define LINUX_CONSOLE "ttyEU7"
+# define CFG__BOARDNAME "mcc200"
+# define CFG__LINUX_CONSOLE "ttyEU7"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -143,7 +146,7 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};" \
"run nfsargs addip addcons;bootm\0" \
- "console=" MK_STR(LINUX_CONSOLE) "\0" \
+ "console=" CFG__LINUX_CONSOLE "\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
@@ -164,7 +167,7 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
/*
* I2C configuration
@@ -180,9 +183,9 @@
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
+ * 0xFE000000 for 32 MB
+ * 0xFF000000 for 16 MB
+ * 0xFF800000 for 8 MB
*/
#define CFG_FLASH_BASE 0xfc000000
#define CFG_FLASH_SIZE 0x04000000
@@ -204,9 +207,9 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -236,7 +239,7 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
@@ -256,27 +259,45 @@
#define CONFIG_PHY_ADDR 1
/*
+ * LCD Splash Screen
+ */
+#if !defined(CONFIG_PRS200)
+#define CONFIG_LCD 1
+#endif
+
+#if defined(CONFIG_LCD)
+#define CONFIG_SPLASH_SCREEN 1
+#define CFG_CONSOLE_IS_IN_ENV 1
+#define LCD_BPP LCD_MONOCHROME
+#endif
+
+/*
* GPIO configuration
*/
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
+#if defined(CONFIG_LCD)
+/* set PSC2 in UART mode */
+#define CFG_GPS_PORT_CONFIG 0x00000044
+#else
#define CFG_GPS_PORT_CONFIG 0x00000004
+#endif
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
diff --git a/include/exports.h b/include/exports.h
index 0eaf66e..8f7f617 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -20,6 +20,9 @@
unsigned long get_timer(unsigned long);
void vprintf(const char *, va_list);
void do_reset (void);
+unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
+char *getenv (char *name);
+void setenv (char *varname, char *varvalue);
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
@@ -37,7 +40,7 @@
XF_MAX
};
-#define XF_VERSION 2
+#define XF_VERSION 3
#if defined(CONFIG_I386)
extern gd_t *global_data;
diff --git a/include/lcd.h b/include/lcd.h
index 7e23736..b688583 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -148,7 +148,14 @@
extern vidinfo_t panel_info;
-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
+#elif defined(CONFIG_MCC200)
+typedef struct vidinfo {
+ ushort vl_col; /* Number of columns (i.e. 160) */
+ ushort vl_row; /* Number of rows (i.e. 100) */
+
+ u_char vl_bpix; /* Bits per pixel, 0 = 1 */
+} vidinfo_t;
+#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
/* Video functions */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index daa4d5f..1d20d1d 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -232,6 +232,65 @@
#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
+#define NR_IRQS 64
+
+/* IRQ mapping - these are our logical IRQ numbers */
+#define MPC5XXX_CRIT_IRQ_NUM 4
+#define MPC5XXX_MAIN_IRQ_NUM 17
+#define MPC5XXX_SDMA_IRQ_NUM 17
+#define MPC5XXX_PERP_IRQ_NUM 23
+
+#define MPC5XXX_CRIT_IRQ_BASE 1
+#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
+#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
+#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
+
+#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
+#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
+#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
+#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
+
+#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
+#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
+#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
+#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
+#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
+#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
+#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
+#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
+#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
+#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
+#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
+#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
+#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
+#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
+#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
+
+#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
+#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
+#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
+#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
+#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
+#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
+#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
+#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
+#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
+#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
+#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
+#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
+#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
+#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
+#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
+#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
+#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
+#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
+#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
+#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
+#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
+#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
+
/* General Purpose Timers registers */
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
diff --git a/include/serial.h b/include/serial.h
index 8c7b1c2..4880059 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -26,6 +26,13 @@
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
+#if defined(CFG_NS16550_SERIAL)
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+#endif /* CFG_NS16550_SERIAL */
+
#endif