arm: zynq: Add Nand flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of memory. This configuration
has only required nand flash support.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
new file mode 100644
index 0000000..9b1dd19
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NAND board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NAND Board";
+ compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &dcc;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x400000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ slcr: slcr@f8000000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF8000000 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+&dcc {
+ status = "okay";
+};