ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 233e659..c8d59ea 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -12,7 +12,7 @@
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o dpll-ld20.o
else
@@ -24,6 +24,8 @@
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
endif
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c b/arch/arm/mach-uniphier/clk/dpll-ld20.c
new file mode 100644
index 0000000..1132313
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-ld20.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
+{
+ unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
+ unsigned int dram_freq = bd->dram_freq;
+
+ uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2);
+ uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2);
+ uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
new file mode 100644
index 0000000..a5027d2
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
+#define SC_PLLCTRL_SSC_EN BIT(31)
+#define SC_PLLCTRL2_NRSTDS BIT(28)
+#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27CTRL_WP BIT(0)
+#define SC_VPLL27CTRL3_K_LD BIT(28)
+
+/* PLL type: DSPLL */
+#define SC_DSPLLCTRL2_K_LD BIT(28)
+
+int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
+ unsigned int ssc_rate, unsigned int divn)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
+ tmp = readl(base); /* SSCPLLCTRL */
+ tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
+ tmp |= (487 * freq * ssc_rate / divn / 512) &
+ SC_PLLCTRL_SSC_DK_MASK;
+ writel(tmp, base);
+
+ tmp = readl(base + 4);
+ tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
+ tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+
+ udelay(50);
+ }
+
+ tmp = readl(base + 4); /* SSCPLLCTRL2 */
+ tmp |= SC_PLLCTRL2_NRSTDS;
+ writel(tmp, base + 4);
+
+ iounmap(base);
+
+ return 0;
+}
+
+int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ mdelay(1);
+
+ tmp = readl(base); /* SSCPLLCTRL */
+ tmp |= SC_PLLCTRL_SSC_EN;
+ writel(tmp, base);
+
+ iounmap(base);
+
+ return 0;
+}
+
+int uniphier_ld20_vpll27_init(unsigned long reg_base)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ tmp = readl(base); /* VPLL27CTRL */
+ tmp |= SC_VPLL27CTRL_WP; /* write protect off */
+ writel(tmp, base);
+
+ tmp = readl(base + 8); /* VPLL27CTRL3 */
+ tmp |= SC_VPLL27CTRL3_K_LD;
+ writel(tmp, base + 8);
+
+ tmp = readl(base); /* VPLL27CTRL */
+ tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
+ writel(tmp, base);
+
+ iounmap(base);
+
+ return 0;
+}
+
+int uniphier_ld20_dspll_init(unsigned long reg_base)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ tmp = readl(base + 8); /* DSPLLCTRL2 */
+ tmp |= SC_DSPLLCTRL2_K_LD;
+ writel(tmp, base + 8);
+
+ iounmap(base);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
new file mode 100644
index 0000000..5e545da
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
+{
+ unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
+
+ uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ /* do nothing for SPLL */
+ uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+ mdelay(1);
+
+ if (dpll_ssc_rate > 0) {
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
+ }
+
+ uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+ uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+ uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
+ uniphier_ld20_dspll_init(SC_A2PLLCTRL);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/pll.h b/arch/arm/mach-uniphier/clk/pll.h
index ef0f722..d7e9303 100644
--- a/arch/arm/mach-uniphier/clk/pll.h
+++ b/arch/arm/mach-uniphier/clk/pll.h
@@ -8,6 +8,14 @@
#ifndef MACH_PLL_H
#define MACH_PLL_H
+#define UNIPHIER_PLL_FREQ_DEFAULT (0)
+
void uniphier_ld4_dpll_ssc_en(void);
+int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
+ unsigned int ssc_rate, unsigned int divn);
+int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
+int uniphier_ld20_vpll27_init(unsigned long reg_base);
+int uniphier_ld20_dspll_init(unsigned long reg_base);
+
#endif /* MACH_PLL_H */