arm: dts: ls1088ardb: add DPMAC and PHY nodes
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.
Also, annotate the external MDIO nodes and describe the PHYs (8 x
VSC8514, AQR105). Also, add phy-handles for the dpmacs to their
associated PHY.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 0fe3519..46a5780 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -17,6 +17,108 @@
};
};
+&dpmac1 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-handle = <&mdio2_phy1>;
+ phy-connection-type = "xgmii";
+};
+
+&dpmac3 {
+ status = "okay";
+ phy-handle = <&mdio1_phy5>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&mdio1_phy6>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&mdio1_phy7>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-handle = <&mdio1_phy8>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac7 {
+ status = "okay";
+ phy-handle = <&mdio1_phy1>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac8 {
+ status = "okay";
+ phy-handle = <&mdio1_phy2>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac9 {
+ status = "okay";
+ phy-handle = <&mdio1_phy3>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac10 {
+ status = "okay";
+ phy-handle = <&mdio1_phy4>;
+ phy-connection-type = "qsgmii";
+};
+
+&emdio1 {
+ status = "okay";
+
+ /* Freescale F104 PHY1 */
+ mdio1_phy1: emdio1_phy@1 {
+ reg = <0x1c>;
+ };
+ mdio1_phy2: emdio1_phy@2 {
+ reg = <0x1d>;
+ };
+ mdio1_phy3: emdio1_phy@3 {
+ reg = <0x1e>;
+ };
+ mdio1_phy4: emdio1_phy@4 {
+ reg = <0x1f>;
+ };
+
+ /* F104 PHY2 */
+ mdio1_phy5: emdio1_phy@5 {
+ reg = <0x0c>;
+ };
+ mdio1_phy6: emdio1_phy@6 {
+ reg = <0x0d>;
+ };
+ mdio1_phy7: emdio1_phy@7 {
+ reg = <0x0e>;
+ };
+ mdio1_phy8: emdio1_phy@8 {
+ reg = <0x0f>;
+ };
+};
+
+&emdio2 {
+ status = "okay";
+
+ /* Aquantia AQR105 10G PHY */
+ mdio2_phy1: emdio2_phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>;
+ reg = <0x0>;
+ };
+};
+
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;