| commit | 6901aab8e35183115ae65362f3af0ea095b6c1b8 | [log] [tgz] |
|---|---|---|
| author | Jagan Teki <jagan@amarulasolutions.com> | Fri Jan 11 15:41:46 2019 +0530 |
| committer | Jagan Teki <jagan@amarulasolutions.com> | Fri Jan 18 22:19:09 2019 +0530 |
| tree | 771d46ec8bbb1700ff392289d9a3b2fef9fd4b6e | |
| parent | 8dcc7e69224f898272dbbbba2d9a1c5efaa28304 [diff] |
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>