clk: sunxi: Add Allwinner A80 CLK driver
Add initial clock driver for Allwinner A80.
- Implement UART bus clocks via ccu_clk_gate table for
A80, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index cb11c7c..5ff101b 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -58,6 +58,13 @@
This enables common clock driver support for platforms based
on Allwinner V3S SoC.
+config CLK_SUN9I_A80
+ bool "Clock driver for Allwinner A80"
+ default MACH_SUN9I
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner A80 SoC.
+
config CLK_SUN8I_H3
bool "Clock driver for Allwinner H3/H5"
default MACH_SUNXI_H3_H5