commit 695f6043c9d84df6feeaca46661123c9f570397d
author Jagan Teki <jagan@amarulasolutions.com> Thu Feb 28 00:26:51 2019 +0530
committer Jagan Teki <jagan@amarulasolutions.com> Tue Apr 16 16:29:01 2019 +0530
tree 787655e20903897cd0d2d6338e5f680b93a4b6a0
parent 0ed8eaf1de2074c40d9a2d4d3d829fd6acee1597

net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle

Unlike other Allwinner SoC's R40 GMAC clock control register
is locate in CCU, but rest located via syscon itself. Since
the phandle property for current code look for 'syscon' and
it will grab the respective ccu or syscon base address based
on DT property defined in respective SoC dtsi.

So, use the existing 'syscon' code even for R40 for retrieving
GMAC clock via CCU and update the register directly in
sun8i_emac_set_syscon instead of writing it separately using
ccm base.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

drivers/net/sun8i_emac.c

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index c979844..a7fb7ac 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -285,10 +285,18 @@
 	int ret;
 	u32 reg;
 
-	reg = readl(priv->sysctl_reg + 0x30);
+	if (priv->variant == R40_GMAC) {
+		/* Select RGMII for R40 */
+		reg = readl(priv->sysctl_reg + 0x164);
+		reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+		       CCM_GMAC_CTRL_GPIT_RGMII |
+		       CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
 
-	if (priv->variant == R40_GMAC)
+		writel(reg, priv->sysctl_reg + 0x164);
 		return 0;
+	}
+
+	reg = readl(priv->sysctl_reg + 0x30);
 
 	if (priv->variant == H3_EMAC) {
 		ret = sun8i_emac_set_syscon_ephy(priv, &reg);
@@ -662,13 +670,6 @@
 
 		/* De-assert EMAC */
 		setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
-
-		/* Select RGMII for R40 */
-		setbits_le32(&ccm->gmac_clk_cfg,
-			     CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
-			     CCM_GMAC_CTRL_GPIT_RGMII);
-		setbits_le32(&ccm->gmac_clk_cfg,
-			     CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
 	} else {
 		/* Set clock gating for emac */
 		setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
@@ -850,25 +851,23 @@
 		return -EINVAL;
 	}
 
-	if (priv->variant != R40_GMAC) {
-		offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
-		if (offset < 0) {
-			debug("%s: cannot find syscon node\n", __func__);
-			return -EINVAL;
-		}
-		reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
-		if (!reg) {
-			debug("%s: cannot find reg property in syscon node\n",
-			      __func__);
-			return -EINVAL;
-		}
-		priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
-							 offset, reg);
-		if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
-			debug("%s: Cannot find syscon base address\n",
-			      __func__);
-			return -EINVAL;
-		}
+	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+	if (offset < 0) {
+		debug("%s: cannot find syscon node\n", __func__);
+		return -EINVAL;
+	}
+
+	reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+	if (!reg) {
+		debug("%s: cannot find reg property in syscon node\n",
+		      __func__);
+		return -EINVAL;
+	}
+	priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+						 offset, reg);
+	if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+		debug("%s: Cannot find syscon base address\n", __func__);
+		return -EINVAL;
 	}
 
 	pdata->phy_interface = -1;