clk/qcom: sdm845: add register map for simple gate clocks
Many gate clocks can be enabled with a single register write, add support
for defining these simple gate clocks and add the ones found on SDM845.
While we're here, inline clk_init_uart() into msm_set_rate().
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index a9f895c..6d399db 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -5,6 +5,8 @@
#ifndef _CLOCK_QCOM_H
#define _CLOCK_QCOM_H
+#include <asm/io.h>
+
#define CFG_CLK_SRC_CXO (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
@@ -30,6 +32,18 @@
uintptr_t D;
};
+struct gate_clk {
+ uintptr_t reg;
+ u32 en_val;
+ const char *name;
+};
+
+#ifdef DEBUG
+#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk }
+#else
+#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL }
+#endif
+
struct qcom_reset_map {
unsigned int reg;
u8 bit;
@@ -38,6 +52,8 @@
struct msm_clk_data {
const struct qcom_reset_map *resets;
unsigned long num_resets;
+ const struct gate_clk *clks;
+ unsigned long num_clks;
};
struct msm_clk_priv {
@@ -55,4 +71,14 @@
void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
int source);
+static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+{
+ u32 val;
+ if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
+ return;
+
+ val = readl(priv->base + priv->data->clks[id].reg);
+ writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
+}
+
#endif