Merge branch 'master' of git://git.denx.de/u-boot-arm
diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c
index 0fcf354..7a1b4d3 100644
--- a/board/altera/common/AMDLV065D.c
+++ b/board/altera/common/AMDLV065D.c
@@ -122,12 +122,12 @@
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr, 0x80);
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr2, 0x30);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x80, addr);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x30, addr2);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
@@ -169,10 +169,10 @@
return (2);
}
- writeb (cmd, 0xaa);
- writeb (cmd, 0x55);
- writeb (cmd, 0xa0);
- writeb (dst, b);
+ writeb (0xaa, cmd);
+ writeb (0x55, cmd);
+ writeb (0xa0, cmd);
+ writeb (b, dst);
/* Verify write */
start = get_timer (0);
diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c
index e5e7705..d019735 100644
--- a/board/altera/common/epled.c
+++ b/board/altera/common/epled.c
@@ -39,7 +39,7 @@
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
@@ -50,7 +50,7 @@
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
@@ -58,5 +58,5 @@
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c
index 0fcf354..72b0a9f 100644
--- a/board/psyent/common/AMDLV065D.c
+++ b/board/psyent/common/AMDLV065D.c
@@ -122,12 +122,12 @@
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr, 0x80);
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr2, 0x30);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x80, addr);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x30, addr2);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
@@ -169,9 +169,9 @@
return (2);
}
- writeb (cmd, 0xaa);
- writeb (cmd, 0x55);
- writeb (cmd, 0xa0);
+ writeb (0xaa, cmd);
+ writeb (0x55, cmd);
+ writeb (0xa0, cmd);
writeb (dst, b);
/* Verify write */
diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c
index e5e7705..d019735 100644
--- a/board/psyent/pk1c20/led.c
+++ b/board/psyent/pk1c20/led.c
@@ -39,7 +39,7 @@
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
@@ -50,7 +50,7 @@
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
@@ -58,5 +58,5 @@
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile
index 75f30b4..3dfaa83 100644
--- a/cpu/nios2/Makefile
+++ b/cpu/nios2/Makefile
@@ -27,7 +27,7 @@
START = start.o
SOBJS = exceptions.o
-COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o
+COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c
index 483b249..ab7d746 100644
--- a/cpu/nios2/epcs.c
+++ b/cpu/nios2/epcs.c
@@ -85,7 +85,7 @@
if (assert) {
tmp = readl (&epcs->control);
- writel (&epcs->control, tmp | NIOS_SPI_SSO);
+ writel (tmp | NIOS_SPI_SSO, &epcs->control);
} else {
/* Let all bits shift out */
start = get_timer (0);
@@ -93,7 +93,7 @@
if (get_timer (start) > EPCS_TIMEOUT)
return (-1);
tmp = readl (&epcs->control);
- writel (&epcs->control, tmp & ~NIOS_SPI_SSO);
+ writel (tmp & ~NIOS_SPI_SSO, &epcs->control);
}
return (0);
}
@@ -106,7 +106,7 @@
while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0)
if (get_timer (start) > EPCS_TIMEOUT)
return (-1);
- writel (&epcs->txdata, c);
+ writel (c, &epcs->txdata);
return (0);
}
@@ -207,6 +207,8 @@
static struct epcs_devinfo_t devinfo[] = {
{ "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c },
{ "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c },
+ { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c },
+ { "EPCS64", 0x16, 23,128, 16, 8, 0x1c },
{ 0, 0, 0, 0, 0, 0 }
};
@@ -501,15 +503,17 @@
}
/* Sector info */
- for (i=0; i<dev->num_sects; i++) {
+ for (i=0; (i < dev->num_sects) && (argc > 1); i++) {
erased = epcs_sect_erased (i, &tmp, dev);
- printf (" %d: %06x ",
+ if ((i & 0x03) == 0) printf ("\n");
+ printf ("%4d: %07x ",
i, i*(1<<dev->sz_sect) );
if (erased)
- printf ("erased\n");
+ printf ("E ");
else
- printf ("data @ 0x%06x\n", tmp);
+ printf (" ");
}
+ printf ("\n");
return;
}
diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c
index 1c3566e..b552db4 100644
--- a/cpu/nios2/interrupts.c
+++ b/cpu/nios2/interrupts.c
@@ -56,7 +56,40 @@
void reset_timer (void)
{
+ nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
+
+ /* From Embedded Peripherals Handbook:
+ *
+ * "When the hardware is configured with Writeable period
+ * disabled, writing to one of the period_n registers causes
+ * the counter to reset to the fixed Timeout Period specified
+ * at system generation time."
+ *
+ * Here we force a reload to prevent early timeouts from
+ * get_timer() when the interrupt period is greater than
+ * than 1 msec.
+ *
+ * Simply write to periodl with its own value to force an
+ * internal counter reload, THEN reset the timestamp.
+ */
+ writel (readl (&tmr->periodl), &tmr->periodl);
timestamp = 0;
+
+ /* From Embedded Peripherals Handbook:
+ *
+ * "Writing to one of the period_n registers stops the internal
+ * counter, except when the hardware is configured with Start/Stop
+ * control bits off. If Start/Stop control bits is off, writing
+ * either register does not stop the counter."
+ *
+ * In order to accomodate either configuration, the control
+ * register is re-written. If the counter is stopped, it will
+ * be restarted. If it is running, the write is essentially
+ * a nop.
+ */
+ writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
+ &tmr->control);
+
}
ulong get_timer (ulong base)
@@ -81,7 +114,7 @@
/* Interrupt is cleared by writing anything to the
* status register.
*/
- writel (&tmr->status, 0);
+ writel (0, &tmr->status);
timestamp += CONFIG_SYS_NIOS_TMRMS;
#ifdef CONFIG_STATUS_LED
status_led_tick(timestamp);
@@ -92,16 +125,16 @@
{
nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
- writel (&tmr->status, 0);
- writel (&tmr->control, 0);
- writel (&tmr->control, NIOS_TIMER_STOP);
+ writel (0, &tmr->status);
+ writel (0, &tmr->control);
+ writel (NIOS_TIMER_STOP, &tmr->control);
#if defined(CONFIG_SYS_NIOS_TMRCNT)
- writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff);
- writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff);
+ writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl);
+ writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh);
#endif
- writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT |
- NIOS_TIMER_START );
+ writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
+ &tmr->control);
irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
}
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 3c77a7c..d2b4820 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -25,11 +25,14 @@
LIB := $(obj)libserial.a
+COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
+COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o
COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
COBJS-$(CONFIG_MCFUART) += mcfuart.o
COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
+COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c
new file mode 100644
index 0000000..fb28aa9
--- /dev/null
+++ b/drivers/serial/altera_jtag_uart.c
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*------------------------------------------------------------------
+ * JTAG acts as the serial port
+ *-----------------------------------------------------------------*/
+static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
+
+void serial_setbrg( void ){ return; }
+int serial_init( void ) { return(0);}
+
+void serial_putc (char c)
+{
+ while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
+ WATCHDOG_RESET ();
+ writel ((unsigned char)c, &jtag->data);
+}
+
+void serial_puts (const char *s)
+{
+ while (*s != 0)
+ serial_putc (*s++);
+}
+
+int serial_tstc (void)
+{
+ return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
+}
+
+int serial_getc (void)
+{
+ int c;
+ unsigned val;
+
+ while (1) {
+ WATCHDOG_RESET ();
+ val = readl (&jtag->data);
+ if (val & NIOS_JTAG_RVALID)
+ break;
+ }
+ c = val & 0x0ff;
+ return (c);
+}
diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c
new file mode 100644
index 0000000..045f119
--- /dev/null
+++ b/drivers/serial/altera_uart.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*------------------------------------------------------------------
+ * UART the serial port
+ *-----------------------------------------------------------------*/
+
+static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;
+
+#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
+
+/* Everything's already setup for fixed-baud PTF
+ * assignment
+ */
+void serial_setbrg (void){ return; }
+int serial_init (void) { return (0);}
+
+#else
+
+void serial_setbrg (void)
+{
+ unsigned div;
+
+ div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
+ writel (div, &uart->divisor);
+ return;
+}
+
+int serial_init (void)
+{
+ serial_setbrg ();
+ return (0);
+}
+
+#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
+
+/*-----------------------------------------------------------------------
+ * UART CONSOLE
+ *---------------------------------------------------------------------*/
+void serial_putc (char c)
+{
+ if (c == '\n')
+ serial_putc ('\r');
+ while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
+ WATCHDOG_RESET ();
+ writel ((unsigned char)c, &uart->txdata);
+}
+
+void serial_puts (const char *s)
+{
+ while (*s != 0) {
+ serial_putc (*s++);
+ }
+}
+
+int serial_tstc (void)
+{
+ return (readl (&uart->status) & NIOS_UART_RRDY);
+}
+
+int serial_getc (void)
+{
+ while (serial_tstc () == 0)
+ WATCHDOG_RESET ();
+ return (readl (&uart->rxdata) & 0x00ff );
+}
diff --git a/cpu/nios2/serial.c b/drivers/serial/opencores_yanu.c
similarity index 61%
rename from cpu/nios2/serial.c
rename to drivers/serial/opencores_yanu.c
index 6c835af..f18f7f4 100644
--- a/cpu/nios2/serial.c
+++ b/drivers/serial/opencores_yanu.c
@@ -1,8 +1,4 @@
/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * YANU Support:
* Copyright 2010, Renato Andreola <renato.andreola@imagos.it>
*
* See file CREDITS for list of people who contributed to this
@@ -24,61 +20,13 @@
* MA 02111-1307 USA
*/
-
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
-#include <nios2-io.h>
#include <nios2-yanu.h>
DECLARE_GLOBAL_DATA_PTR;
-/*------------------------------------------------------------------
- * JTAG acts as the serial port
- *-----------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
-
-static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
-
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
-
-void serial_putc (char c)
-{
- unsigned val;
-
- while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
- WATCHDOG_RESET ();
- writel (&jtag->data, (unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
- while (*s != 0)
- serial_putc (*s++);
-}
-
-int serial_tstc (void)
-{
- return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
-}
-
-int serial_getc (void)
-{
- int c;
- unsigned val;
-
- while (1) {
- WATCHDOG_RESET ();
- val = readl (&jtag->data);
- if (val & NIOS_JTAG_RVALID)
- break;
- }
- c = val & 0x0ff;
- return (c);
-}
-
-#elif defined(CONFIG_CONSOLE_YANU)
/*-----------------------------------------------------------------*/
/* YANU Imagos serial port */
/*-----------------------------------------------------------------*/
@@ -113,7 +61,7 @@
((unsigned)CONFIG_SYS_CLK_FREQ >> k);
baud = best_m + best_n * YANU_BAUDE;
- writel(&uart->baud, baud);
+ writel(baud, &uart->baud);
return;
}
@@ -144,7 +92,7 @@
((unsigned)CONFIG_SYS_CLK_FREQ >> k);
baud = best_m + best_n * YANU_BAUDE;
- writel(&uart->baud, baud);
+ writel(baud, &uart->baud);
return;
}
@@ -165,7 +113,7 @@
YANU_ACTION_RPE |
YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR;
- writel(&uart->action, action);
+ writel(action, &uart->action);
/* control register cleanup */
/* no interrupts enabled */
@@ -179,7 +127,7 @@
control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY;
control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR;
- writel(&uart->control, control);
+ writel(control, &uart->control);
/* to set baud rate */
serial_setbrg();
@@ -208,7 +156,7 @@
WATCHDOG_RESET ();
}
- writel(&uart->data, (unsigned char)c);
+ writel((unsigned char)c, &uart->data);
}
void serial_puts (const char *s)
@@ -234,76 +182,7 @@
WATCHDOG_RESET ();
/* first we pull the char */
- writel(&uart->action, YANU_ACTION_RFIFO_PULL);
+ writel(YANU_ACTION_RFIFO_PULL, &uart->action);
return(readl(&uart->data) & YANU_DATA_CHAR_MASK);
}
-
-#else /*CONFIG_CONSOLE_YANU*/
-
-/*------------------------------------------------------------------
- * UART the serial port
- *-----------------------------------------------------------------*/
-
-static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;
-
-#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF
- * assignment
- */
-void serial_setbrg (void){ return; }
-int serial_init (void) { return (0);}
-
-#else
-
-void serial_setbrg (void)
-{
- unsigned div;
-
- div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
- writel (&uart->divisor,div);
- return;
-}
-
-int serial_init (void)
-{
- serial_setbrg ();
- return (0);
-}
-
-#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-
-
-/*-----------------------------------------------------------------------
- * UART CONSOLE
- *---------------------------------------------------------------------*/
-void serial_putc (char c)
-{
- if (c == '\n')
- serial_putc ('\r');
- while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
- WATCHDOG_RESET ();
- writel (&uart->txdata,(unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
- while (*s != 0) {
- serial_putc (*s++);
- }
-}
-
-int serial_tstc (void)
-{
- return (readl (&uart->status) & NIOS_UART_RRDY);
-}
-
-int serial_getc (void)
-{
- while (serial_tstc () == 0)
- WATCHDOG_RESET ();
- return (readl (&uart->rxdata) & 0x00ff );
-}
-
-#endif /* CONFIG_JTAG_CONSOLE */
diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h
index 5776bda..cf48ff7 100644
--- a/include/asm-nios2/bitops.h
+++ b/include/asm-nios2/bitops.h
@@ -24,15 +24,9 @@
#ifndef __ASM_NIOS2_BITOPS_H_
#define __ASM_NIOS2_BITOPS_H_
-
-extern void set_bit(int nr, volatile void * a);
-extern void clear_bit(int nr, volatile void * a);
-extern int test_and_clear_bit(int nr, volatile void * a);
-extern void change_bit(unsigned long nr, volatile void *addr);
-extern int test_and_set_bit(int nr, volatile void * a);
-extern int test_and_change_bit(int nr, volatile void * addr);
-extern int test_bit(int nr, volatile void * a);
-extern int ffs(int i);
-#define PLATFORM_FFS
+/* copied from linux-2.6/include/asm-generic/bitops */
+#include <asm/bitops/atomic.h>
+#include <asm/bitops/non-atomic.h>
+#include <asm/bitops/ffs.h>
#endif /* __ASM_NIOS2_BITOPS_H */
diff --git a/include/asm-nios2/bitops/atomic.h b/include/asm-nios2/bitops/atomic.h
new file mode 100644
index 0000000..c894646
--- /dev/null
+++ b/include/asm-nios2/bitops/atomic.h
@@ -0,0 +1,189 @@
+#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_
+#define _ASM_GENERIC_BITOPS_ATOMIC_H_
+
+#include <asm/types.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SMP
+#include <asm/spinlock.h>
+#include <asm/cache.h> /* we use L1_CACHE_BYTES */
+
+/* Use an array of spinlocks for our atomic_ts.
+ * Hash function to index into a different SPINLOCK.
+ * Since "a" is usually an address, use one spinlock per cacheline.
+ */
+# define ATOMIC_HASH_SIZE 4
+# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
+
+extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
+
+/* Can't use raw_spin_lock_irq because of #include problems, so
+ * this is the substitute */
+#define _atomic_spin_lock_irqsave(l,f) do { \
+ raw_spinlock_t *s = ATOMIC_HASH(l); \
+ local_irq_save(f); \
+ __raw_spin_lock(s); \
+} while(0)
+
+#define _atomic_spin_unlock_irqrestore(l,f) do { \
+ raw_spinlock_t *s = ATOMIC_HASH(l); \
+ __raw_spin_unlock(s); \
+ local_irq_restore(f); \
+} while(0)
+
+
+#else
+# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
+# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
+#endif
+
+/*
+ * NMI events can occur at any time, including when interrupts have been
+ * disabled by *_irqsave(). So you can get NMI events occurring while a
+ * *_bit function is holding a spin lock. If the NMI handler also wants
+ * to do bit manipulation (and they do) then you can get a deadlock
+ * between the original caller of *_bit() and the NMI handler.
+ *
+ * by Keith Owens
+ */
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered. See __set_bit()
+ * if you do not require the atomic guarantees.
+ *
+ * Note: there are no guarantees that this function will not be reordered
+ * on non x86 architectures, so if you are writing portable code,
+ * make sure not to rely on its reordering guarantees.
+ *
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ *p |= mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered. However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ *p &= ~mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered. It may be
+ * reordered on other architectures than x86.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ *p ^= mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It may be reordered on other architectures than x86.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ old = *p;
+ *p = old | mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+
+ return (old & mask) != 0;
+}
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It can be reorderdered on other architectures other than x86.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ old = *p;
+ *p = old & ~mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+
+ return (old & mask) != 0;
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ old = *p;
+ *p = old ^ mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+
+ return (old & mask) != 0;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */
diff --git a/include/asm-nios2/bitops/ffs.h b/include/asm-nios2/bitops/ffs.h
new file mode 100644
index 0000000..fbbb43a
--- /dev/null
+++ b/include/asm-nios2/bitops/ffs.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_GENERIC_BITOPS_FFS_H_
+#define _ASM_GENERIC_BITOPS_FFS_H_
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int x)
+{
+ int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */
diff --git a/include/asm-nios2/bitops/non-atomic.h b/include/asm-nios2/bitops/non-atomic.h
new file mode 100644
index 0000000..697cc2b
--- /dev/null
+++ b/include/asm-nios2/bitops/non-atomic.h
@@ -0,0 +1,108 @@
+#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
+#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
+
+#include <asm/types.h>
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p |= mask;
+}
+
+static inline void __clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p &= ~mask;
+}
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to change
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p ^= mask;
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old | mask;
+ return (old & mask) != 0;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old & ~mask;
+ return (old & mask) != 0;
+}
+
+/* WARNING: non atomic and it can be reordered! */
+static inline int __test_and_change_bit(int nr,
+ volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old ^ mask;
+ return (old & mask) != 0;
+}
+
+/**
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static inline int test_bit(int nr, const volatile unsigned long *addr)
+{
+ return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+}
+
+#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */
diff --git a/include/asm-nios2/errno.h b/include/asm-nios2/errno.h
new file mode 100644
index 0000000..4c82b50
--- /dev/null
+++ b/include/asm-nios2/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h
index 01d11ef..121405c 100644
--- a/include/asm-nios2/io.h
+++ b/include/asm-nios2/io.h
@@ -80,19 +80,19 @@
({unsigned long val;\
asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
-#define writeb(addr,val)\
- asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val))
-#define writew(addr,val)\
- asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val))
-#define writel(addr,val)\
- asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val))
+#define writeb(val,addr)\
+ asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr))
+#define writew(val,addr)\
+ asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr))
+#define writel(val,addr)\
+ asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr))
#define inb(addr) readb(addr)
#define inw(addr) readw(addr)
#define inl(addr) readl(addr)
-#define outb(addr,val) writeb(addr,val)
-#define outw(addr,val) writew(addr,val)
-#define outl(addr,val) writel(addr,val)
+#define outb(val, addr) writeb(val,addr)
+#define outw(val, addr) writew(val,addr)
+#define outl(val, addr) writel(val,addr)
static inline void insb (unsigned long port, void *dst, unsigned long count)
{
diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h
index ec84f59..bb03ca5 100644
--- a/include/asm-nios2/system.h
+++ b/include/asm-nios2/system.h
@@ -23,4 +23,37 @@
#ifndef __ASM_NIOS2_SYSTEM_H_
#define __ASM_NIOS2_SYSTEM_H_
+#define local_irq_enable() __asm__ __volatile__ ( \
+ "rdctl r8, status\n" \
+ "ori r8, r8, 1\n" \
+ "wrctl status, r8\n" \
+ : : : "r8")
+
+#define local_irq_disable() __asm__ __volatile__ ( \
+ "rdctl r8, status\n" \
+ "andi r8, r8, 0xfffe\n" \
+ "wrctl status, r8\n" \
+ : : : "r8")
+
+#define local_save_flags(x) __asm__ __volatile__ ( \
+ "rdctl r8, status\n" \
+ "mov %0, r8\n" \
+ : "=r" (x) : : "r8", "memory")
+
+#define local_irq_restore(x) __asm__ __volatile__ ( \
+ "mov r8, %0\n" \
+ "wrctl status, r8\n" \
+ : : "r" (x) : "r8", "memory")
+
+/* For spinlocks etc */
+#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \
+ while (0)
+
+#define irqs_disabled() \
+({ \
+ unsigned long flags; \
+ local_save_flags(flags); \
+ ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \
+})
+
#endif /* __ASM_NIOS2_SYSTEM_H */
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
index 61d8e20..3920d35 100644
--- a/include/configs/EP1C20.h
+++ b/include/configs/EP1C20.h
@@ -94,7 +94,8 @@
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
@@ -123,14 +124,16 @@
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
index 41e64e6..bfbf8c1 100644
--- a/include/configs/EP1S10.h
+++ b/include/configs/EP1S10.h
@@ -92,7 +92,8 @@
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
@@ -118,14 +119,16 @@
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
index 5b332e4..4d905fe 100644
--- a/include/configs/EP1S40.h
+++ b/include/configs/EP1S40.h
@@ -92,7 +92,8 @@
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
@@ -118,14 +119,16 @@
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 831a60d..c60a9f7 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -92,7 +92,8 @@
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */
@@ -113,14 +114,16 @@
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index cf6f7a9..874c20b 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -94,7 +94,8 @@
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
@@ -123,14 +124,16 @@
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 2ce1c25..cef6369 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -68,7 +68,7 @@
#endif /* __PPC__ */
#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
- defined (__microblaze__)
+ defined (__microblaze__) || defined (__nios2__)
struct stat {
unsigned short st_dev;
diff --git a/lib_nios2/board.c b/lib_nios2/board.c
index 41d3297..8ec66a3 100644
--- a/lib_nios2/board.c
+++ b/lib_nios2/board.c
@@ -139,6 +139,13 @@
board_late_init ();
#endif
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+ puts ("Net: ");
+#endif
+ eth_initialize (bd);
+#endif
+
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c
index 675bfac..5d25edf 100644
--- a/lib_nios2/bootm.c
+++ b/lib_nios2/bootm.c
@@ -26,21 +26,26 @@
#include <asm/byteorder.h>
#include <asm/cache.h>
+#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
+
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
- void (*kernel)(void) = (void (*)(void))images->ep;
+ void (*kernel)(int, int, int, char *) = (void *)images->ep;
+ char *commandline = getenv("bootargs");
+ ulong initrd_start = images->rd_start;
+ ulong initrd_end = images->rd_end;
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
/* flushes data and instruction caches before calling the kernel */
- flush_dcache (0,CONFIG_SYS_DCACHE_SIZE);
- flush_icache (0,CONFIG_SYS_ICACHE_SIZE);
+ disable_interrupts();
+ flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE);
+ flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE);
- /* For now we assume the Microtronix linux ... which only
- * needs to be called ;-)
- */
- kernel ();
+ debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline);
+ debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end);
+ kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline);
/* does not return */
return 1;