| commit | 6aabe229f8440c4960b904baf3aa33f692eea9a1 | [log] [tgz] |
|---|---|---|
| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | Fri Jul 21 18:01:18 2023 +0200 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Mon Jul 24 13:22:24 2023 +0800 |
| tree | 5a7314ebcc2d425d78126de4cd7eed11d716b5ce | |
| parent | 90704967947817eecf6170daa3cea723e3110f8a [diff] |
riscv: define a cache line size for the generic CPU The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. Define the cache line size for QEMU on RISC-V to be 64 bytes. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng@tinylab.org>