commit 6b1e1254f326940e5b65c7029f71b964bdf28fd4
author York Sun <yorksun@freescale.com> Mon Feb 10 13:59:44 2014 -0800
committer Tom Rini <trini@ti.com> Fri Feb 21 11:06:13 2014 -0500
tree a8e596b2d01fe4a952e253b9b42972b040a4a165
parent 6b9e309a8a7f0f33252288f0ed8794a83a488301

driver/ddr: Add 256 byte interleaving support

Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>

drivers/ddr/fsl/util.c

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 450a488..ad53658 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -228,6 +228,9 @@
 		puts("       DDR Controller Interleaving Mode: ");
 
 		switch ((cs0_config >> 24) & 0xf) {
+		case FSL_DDR_256B_INTERLEAVING:
+			puts("256B");
+			break;
 		case FSL_DDR_CACHE_LINE_INTERLEAVING:
 			puts("cache line");
 			break;