siemens,am33x: add draco etamin board
In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Move BOOTDELAY into defconfig, just always be 3 now]
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index c127f6c..9cafcea 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -83,8 +83,12 @@
#ifdef CONFIG_FACTORYSET
factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
#endif
+
gpmc_init();
+#ifdef CONFIG_NAND_CS_INIT
+ board_nand_cs_init();
+#endif
#ifdef CONFIG_VIDEO
board_video_init();
#endif
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 819d187..a699c7d 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -45,3 +45,19 @@
default "rastaban"
endif
+
+if TARGET_ETAMIN
+
+config SYS_BOARD
+ default "draco"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "etamin"
+
+endif
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
index 484dd73..e9107f0 100644
--- a/board/siemens/draco/MAINTAINERS
+++ b/board/siemens/draco/MAINTAINERS
@@ -4,6 +4,7 @@
F: board/siemens/draco/
F: include/configs/draco.h
F: configs/draco_defconfig
+F: configs/etamin_defconfig
F: include/configs/thuban.h
F: configs/thuban_defconfig
F: include/configs/rastaban.h
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 41bdef0..d8869a0 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -24,6 +24,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
@@ -33,6 +34,7 @@
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"
+#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,6 +42,7 @@
static struct draco_baseboard_id __attribute__((section(".data"))) settings;
#if DDR_PLL_FREQ == 303
+#if !defined(CONFIG_TARGET_ETAMIN)
/* Default@303MHz-i0 */
const struct ddr3_data ddr3_default = {
0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
@@ -48,6 +51,16 @@
"default name @303MHz \0",
"default marking \0",
};
+#else
+/* etamin board */
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
+ 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
+ 0x0000093B, 0x0000018A,
+ "test-etamin \0",
+ "generic-8Gbit \0",
+};
+#endif
#elif DDR_PLL_FREQ == 400
/* Default@400MHz-i0 */
const struct ddr3_data ddr3_default = {
@@ -210,6 +223,7 @@
draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+ draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
@@ -251,6 +265,10 @@
nand_curr_device = 0;
omap_nand_switch_ecc(1, ecc_type);
+#ifdef CONFIG_TARGET_ETAMIN
+ nand_curr_device = 1;
+ omap_nand_switch_ecc(1, ecc_type);
+#endif
#ifdef CONFIG_FACTORYSET
/* Set ASN in environment*/
if (factory_dat.asn[0] != 0) {
@@ -326,7 +344,7 @@
}
static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
+ char *const argv[])
{
/* Reset SMSC LAN9303 switch for default configuration */
gpio_request(GPIO_LAN9303_NRST, "nRST");
@@ -346,4 +364,23 @@
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#ifdef CONFIG_NAND_CS_INIT
+/* GPMC definitions for second nand cs1 */
+static const u32 gpmc_nand_config[] = {
+ ETAMIN_NAND_GPMC_CONFIG1,
+ ETAMIN_NAND_GPMC_CONFIG2,
+ ETAMIN_NAND_GPMC_CONFIG3,
+ ETAMIN_NAND_GPMC_CONFIG4,
+ ETAMIN_NAND_GPMC_CONFIG5,
+ ETAMIN_NAND_GPMC_CONFIG6,
+ /*CONFIG7- computed as params */
+};
+
+static void board_nand_cs_init(void)
+{
+ enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
+ 0x18000000, GPMC_SIZE_16M);
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
index dbcc80b..38a484e 100644
--- a/board/siemens/draco/mux.c
+++ b/board/siemens/draco/mux.c
@@ -51,6 +51,7 @@
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN}, /* NAND_CS1 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
@@ -68,7 +69,6 @@
{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
/* Triacs initial HW Rev */
- {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */