Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.
Signed-off-by: York Sun <yorksun@freescale.com>
diff --git a/README b/README
index 413d682..355e898 100644
--- a/README
+++ b/README
@@ -492,6 +492,11 @@
CONFIG_SYS_FSL_DDR_LE
Defines the DDR controller register space as Little Endian
+ CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+ Physical address from the view of DDR controllers. It is the
+ same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
+ it could be different for ARM SoCs.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO