clk: sandbox: Adjust clk-divider to emulate reading its value from HW
The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.
The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3348d97..6921c76 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -74,7 +74,12 @@
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned int val;
- val = readl(divider->reg) >> divider->shift;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ val = divider->io_divider_val;
+#else
+ val = readl(divider->reg);
+#endif
+ val >>= divider->shift;
val &= clk_div_mask(divider->width);
return divider_recalc_rate(clk, parent_rate, val, divider->table,
@@ -112,6 +117,9 @@
div->width = width;
div->flags = clk_divider_flags;
div->table = table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ div->io_divider_val = *(u32 *)reg;
+#endif
/* register the clock */
clk = &div->clk;