| commit | e4916e2c66801c2dad95dc553841f126ee2a81f9 | [log] [tgz] |
|---|---|---|
| author | Elaine Zhang <zhangqing@rock-chips.com> | Thu Oct 12 18:18:12 2023 +0800 |
| committer | Kever Yang <kever.yang@rock-chips.com> | Mon Oct 23 18:21:55 2023 +0800 |
| tree | 76a89a18838a4d5c275540b68c04704a138841c4 | |
| parent | cdf21a8696a4ce6cb3103b175665fdc458b04d57 [diff] |
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent Optimize setting process. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>