NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index a694083..a11a9b8 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -150,7 +150,6 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index a44f3e1..1e36660 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -219,7 +219,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index d0e2464..eebce38 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -157,7 +157,6 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index 729153c..85c0e61 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -411,7 +411,6 @@
* NAND FLASH
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index d299044..b445fae 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -205,7 +205,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 80e59bb..e5de8ef 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -209,7 +209,6 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index b3c7046..1106b0d 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -149,7 +149,6 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index a610ac9..fbcbddb 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -275,7 +275,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define NAND_DISABLE_CE(nand) do \
{ \
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index c207947..1f1586a 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -215,7 +215,6 @@
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-# define NAND_MAX_CHIPS 1
# define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index a1bc32a..1991687 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -215,7 +215,6 @@
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-# define NAND_MAX_CHIPS 1
# define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index fc3fa13..58a26e1 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -232,7 +232,6 @@
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 48043c4..e4ada65 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -223,7 +223,6 @@
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index a4f2862..c20f86a 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -211,7 +211,6 @@
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index d49155f..dbffb71 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -271,7 +271,6 @@
#define CONFIG_CMD_NAND 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 532c3df..505c48b 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -248,7 +248,6 @@
CONFIG_SYS_NAND_BASE + 0x80000, \
CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 6c7a364..f84cc7e 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -267,7 +267,6 @@
CONFIG_SYS_NAND_BASE + 0x80000,\
CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 423ca71..0b97f0c 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -250,7 +250,6 @@
* NAND flash support
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 34de947..2d04d89 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -514,7 +514,6 @@
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 004b3c8..34fdba5 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -633,7 +633,6 @@
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
#define NAND_DISABLE_CE(nand) \
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index 70995fa..4a27027 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -515,7 +515,6 @@
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index 87c920f..f97bdcb 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -411,7 +411,6 @@
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define NAND_DISABLE_CE(nand) \
do { \
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 11ce008..e9f1646 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -173,7 +173,6 @@
* NAND-FLASH stuff
*/
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index f9f1002..fc48bc1 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -505,7 +505,6 @@
* NAND FLASH
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_QUIET_TEST 1
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 09a9641..d4322b6 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -224,8 +224,6 @@
#define NAND_BIG_DELAY_US 25
#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
-
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index 7fc455b..9857bf6 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -206,7 +206,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
/* DFBUSY is available on Port C, bit 12; 0 if busy */
#define NAND_WAIT_READY(nand) \
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 1915a73..9cac696 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -424,7 +424,6 @@
#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
CONFIG_SYS_NAND1_BASE, \
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 6d205a7..f5831eb 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -363,7 +363,6 @@
#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
#if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 0bc2f68..83d0d56 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -264,7 +264,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB()
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 10ef620..f173bcc 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -159,7 +159,6 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index 01cdf3a..de6e12f 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -147,7 +147,6 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 52ccdb5..9ffd86b 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -262,7 +262,6 @@
* NAND FLASH
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index d63a1a0..e996bbd 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -97,7 +97,6 @@
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 7ce8205..e6248e9 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -335,7 +335,6 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index b2baf1b..f1c5526 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -118,7 +118,6 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* NAND flash */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index c7e83cc..5a980d3 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -129,7 +129,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 1538929..4501cae 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -100,7 +100,6 @@
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 0016b4f..668fe3b 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -111,7 +111,6 @@
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index d9ebc87..c6603ff 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -123,7 +123,6 @@
#endif
/* NAND flash */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 35fefc4..5bef1fe 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -104,7 +104,6 @@
#define CONFIG_SYS_NO_FLASH 1
/* NAND flash */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index f3ffe1c..8c4127d 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -197,7 +197,6 @@
* NAND FLASH
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 1b54d3b..ac5aaa5 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -278,7 +278,6 @@
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define BFIN_NAND_READY PF3
#define NAND_WAIT_READY(nand) \
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index faf6304..d814012 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -234,7 +234,6 @@
* NAND-FLASH related
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 2df77cf..761c0dc 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -131,7 +131,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 6885b2c..a727f56 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -127,7 +127,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 8d7bcf5..22d3808 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -89,7 +89,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/*=====================*/
/* Board related stuff */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index e9cd5a6..875bab6 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -85,7 +85,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 381eeb7..47ab27a 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -122,7 +122,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 08b28ca..fd97b74 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -258,7 +258,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NO_FLASH 1
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index b943f31..4d3ccf5 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -214,7 +214,6 @@
* NAND FLASH
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index dda6597..fab22d1 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -120,7 +120,6 @@
* NAND flash
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
#define NAND_ALLOW_ERASE_ALL 1
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index d11868e..92df0b4 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -163,7 +163,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 8b7890e..f8aac1a 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -264,7 +264,6 @@
* NAND-FLASH stuff
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
#endif
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 0f7fca3..3ea854b 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -224,7 +224,6 @@
#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index d7a6ae4..bf4a14e 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -209,7 +209,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB()
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index d152a96..515b097 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -424,7 +424,6 @@
* NAND-FLASH stuff
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x77D00000
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 9321bdc..a3e2fce 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -373,7 +373,6 @@
* NAND FLASH
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 1784cc6..57c82d1 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -227,7 +227,6 @@
/* NAND configuration */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x70200010
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_S3C_NAND_HWECC
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index cbf04e3..becd13e 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -186,7 +186,6 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_CMD_NAND
/* LIME GDC */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index bc078cf..5a5f772 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -464,7 +464,6 @@
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
#define NAND_DISABLE_CE(nand) \
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 53397d8..f30eca1 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -227,7 +227,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NO_FLASH 1
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index abf8f1a..7db2546 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -18,8 +18,8 @@
#define __LINUX_MTD_BBM_H
/* The maximum number of NAND chips in an array */
-#ifndef NAND_MAX_CHIPS
-#define NAND_MAX_CHIPS 8
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
#endif
/**
@@ -48,10 +48,10 @@
*/
struct nand_bbt_descr {
int options;
- int pages[NAND_MAX_CHIPS];
+ int pages[CONFIG_SYS_NAND_MAX_CHIPS];
int offs;
int veroffs;
- uint8_t version[NAND_MAX_CHIPS];
+ uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS];
int len;
int maxblocks;
int reserved_block_code;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 24ad2bd..a4ad571 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -46,11 +46,6 @@
/* Internal helper for board drivers which need to override command function */
extern void nand_wait_ready(struct mtd_info *mtd);
-/* The maximum number of NAND chips in an array */
-#ifndef NAND_MAX_CHIPS
-#define NAND_MAX_CHIPS 8
-#endif
-
/* This constant declares the max. oobsize / page, which
* is supported now. If you add a chip with bigger oobsize/page
* adjust this accordingly.
@@ -477,10 +472,6 @@
extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];
-#ifndef NAND_MAX_CHIPS
-#define NAND_MAX_CHIPS 8
-#endif
-
extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
extern int nand_default_bbt(struct mtd_info *mtd);
diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
index 99eafbb..4334448 100644
--- a/include/linux/mtd/nand_legacy.h
+++ b/include/linux/mtd/nand_legacy.h
@@ -40,6 +40,11 @@
#error This module is for the legacy NAND support
#endif
+/* The maximum number of NAND chips in an array */
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#endif
+
/*
* Standard NAND flash commands
*/