pinctrl: sunxi: Add P2WI and RSB pinmuxes
P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 061104b..c4fbda7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -338,6 +338,7 @@
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL0-PL1 */
+ { "s_p2wi", 3 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -404,6 +405,7 @@
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -469,6 +471,7 @@
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -574,6 +577,7 @@
{ "gpio_out", 1 },
{ "s_i2c0", 2 }, /* PN0-PN1 */
{ "s_i2c1", 3 }, /* PM8-PM9 */
+ { "s_rsb", 3 }, /* PN0-PN1 */
{ "s_uart", 3 }, /* PL0-PL1 */
};
@@ -615,6 +619,7 @@
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -680,6 +685,7 @@
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -717,6 +723,7 @@
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};