rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
index 5f86de5..db54bc4 100644
--- a/board/freescale/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
@@ -27,8 +27,8 @@
/*
* CADMUS Board System Registers
*/
-#ifndef CFG_CADMUS_BASE_REG
-#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
+#ifndef CONFIG_SYS_CADMUS_BASE_REG
+#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
#endif
typedef struct cadmus_reg {
@@ -47,7 +47,7 @@
unsigned int
get_board_version(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
return cadmus->cm_ver;
}
@@ -56,7 +56,7 @@
unsigned long
get_clock_freq(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
@@ -74,7 +74,7 @@
unsigned int
get_pci_slot(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
/*
* PCI slot in USER bits CSR[6:7] by convention.
@@ -86,7 +86,7 @@
unsigned int
get_pci_dual(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
/*
* PCI DUAL in CM_PCI[3]
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index 4d4b0a1..2fc878b 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -205,7 +205,7 @@
unsigned int i, j;
debug("Enter fsl_diu_init\n");
- dr.diu_reg = (struct diu *) (CFG_DIU_ADDR);
+ dr.diu_reg = (struct diu *) (CONFIG_SYS_DIU_ADDR);
hw = (struct diu *) dr.diu_reg;
disable_lcdc();
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index b5a0e84..348696e 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -207,8 +207,8 @@
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}
-#ifndef CFG_PIXIS_VBOOT_MASK
-#define CFG_PIXIS_VBOOT_MASK (0x40)
+#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
+#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif
void clear_altbank(void)
@@ -216,7 +216,7 @@
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
- tmp &= ~CFG_PIXIS_VBOOT_MASK;
+ tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}
@@ -227,7 +227,7 @@
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
- tmp |= CFG_PIXIS_VBOOT_MASK;
+ tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}
@@ -327,7 +327,7 @@
}
U_BOOT_CMD(
- pixis_set_sgmii, CFG_MAXARGS, 1, pixis_set_sgmii,
+ pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
"pixis_set_sgmii"
" - Enable or disable SGMII mode for a given TSEC \n",
"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
@@ -518,7 +518,7 @@
U_BOOT_CMD(
- pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
"pixis_reset - Reset the board using the FPGA sequencer\n",
" pixis_reset\n"
" pixis_reset [altbank]\n"
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 9bef92e..eb58c7f 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -30,8 +30,8 @@
#include "../common/eeprom.h"
-#if !defined(CFG_I2C_EEPROM_CCID) && !defined(CFG_I2C_EEPROM_NXID)
-#error "Please define either CFG_I2C_EEPROM_CCID or CFG_I2C_EEPROM_NXID"
+#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID)
+#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID"
#endif
/**
@@ -40,7 +40,7 @@
* See application note AN3638 for details.
*/
static struct __attribute__ ((__packed__)) eeprom {
-#ifdef CFG_I2C_EEPROM_CCID
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'CCID' */
u8 major; /* 0x04 Board revision, major */
u8 minor; /* 0x05 Board revision, minor */
@@ -53,7 +53,7 @@
u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72 CRC32 checksum */
#endif
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
u8 sn[12]; /* 0x04 - 0x0F Serial Number */
u8 errata[5]; /* 0x10 - 0x14 Errata Level */
@@ -74,12 +74,12 @@
/* Set to 1 if we've read EEPROM into memory */
static int has_been_read = 0;
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
/* Is this a valid NXID EEPROM? */
#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D'))
#endif
-#ifdef CFG_I2C_EEPROM_CCID
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
/* Is this a valid CCID EEPROM? */
#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
#endif
@@ -93,7 +93,7 @@
unsigned int crc;
/* EEPROM tag ID, either CCID or NXID */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
be32_to_cpu(e.version));
#else
@@ -104,7 +104,7 @@
printf("SN: %s\n", e.sn);
/* Errata level. */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("Errata: %s\n", e.errata);
#else
printf("Errata: %c%c\n",
@@ -152,22 +152,22 @@
static int read_eeprom(void)
{
int ret;
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
if (has_been_read)
return 0;
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
- i2c_set_bus_num(CFG_EEPROM_BUS_NUM);
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
- ret = i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN,
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e, sizeof(e));
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
@@ -188,12 +188,12 @@
int ret, i, length;
unsigned int crc;
void *p;
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
/* Set the reserved values to 0xFF */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
e.res_0 = 0xFF;
memset(e.res_1, 0xFF, sizeof(e.res_1));
#else
@@ -204,20 +204,20 @@
crc = crc32(0, (void *)&e, length - 4);
e.crc = cpu_to_be32(crc);
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
- i2c_set_bus_num(CFG_EEPROM_BUS_NUM);
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
for (i = 0, p = &e; i < length; i += 8, p += 8) {
- ret = i2c_write(CFG_I2C_EEPROM_ADDR, i, CFG_I2C_EEPROM_ADDR_LEN,
+ ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((length - i), 8));
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
}
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
@@ -343,7 +343,7 @@
strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
break;
case 'e': /* errata */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
memset(e.errata, 0, 5);
strncpy((char *)e.errata, argv[2], 4);
#else
@@ -429,7 +429,7 @@
return 0;
}
-#ifdef CFG_I2C_EEPROM_CCID
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
/**
* get_cpu_board_revision - get the CPU board revision on 85xx boards
@@ -439,11 +439,11 @@
* This function is called before relocation, so we need to read a private
* copy of the EEPROM into a local variable on the stack.
*
- * Also, we assume that CFG_EEPROM_BUS_NUM == CFG_SPD_BUS_NUM. The global
- * variable i2c_bus_num must be compile-time initialized to CFG_SPD_BUS_NUM,
+ * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM. The global
+ * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM,
* so that the SPD code will work. This means that all pre-relocation I2C
- * operations can only occur on the CFG_SPD_BUS_NUM bus. So if
- * CFG_EEPROM_BUS_NUM != CFG_SPD_BUS_NUM, then we can't read the EEPROM when
+ * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus. So if
+ * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when
* this function is called. Oh well.
*/
unsigned int get_cpu_board_revision(void)
@@ -454,7 +454,7 @@
u8 minor; /* 0x05 Board revision, minor */
} be;
- i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN,
+ i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&be, sizeof(be));
if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index e5f47d2..838a6de 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -41,7 +41,7 @@
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -49,28 +49,28 @@
}
i--;
- sdram->sdcs0 = (CFG_SDRAM_BASE | i);
+ sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CFG_SDRAM_CFG1;
- sdram->sdcfg2 = CFG_SDRAM_CFG2;
+ sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
- sdram->sdcr = CFG_SDRAM_CTRL | 2;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
- /*sdram->sdmr = CFG_SDRAM_EMOD; */
- sdram->sdmr = CFG_SDRAM_MODE;
+ /*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
+ sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
udelay(1000);
/* Issue PALL */
- sdram->sdcr = CFG_SDRAM_CTRL | 2;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
/* Perform two refresh cycles */
- sdram->sdcr = CFG_SDRAM_CTRL | 4;
- sdram->sdcr = CFG_SDRAM_CTRL | 4;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index bd8a4e5..b9e6126 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -57,7 +57,7 @@
GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -65,7 +65,7 @@
i--;
if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
- dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
@@ -73,7 +73,7 @@
/* Initialize DACR0 */
sdram->dacr0 =
- SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
+ SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
asm("nop");
@@ -90,7 +90,7 @@
}
/* Write to this block to initiate precharge */
- *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_RE;
@@ -105,7 +105,7 @@
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c
index 1fd4d99..5fbbd66 100644
--- a/board/freescale/m5235evb/mii.c
+++ b/board/freescale/m5235evb/mii.c
@@ -49,7 +49,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -135,9 +135,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -202,7 +202,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index c9ed341..b1ccbeb 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -42,7 +42,7 @@
/*
* Set LED on
*/
- val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0;
@@ -57,13 +57,13 @@
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
*/
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
/*
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
*/
mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CFG_PLL_BYPASS
+#elif CONFIG_SYS_PLL_BYPASS
/*
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
@@ -101,7 +101,7 @@
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 1bf1e97..08f767d 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -28,7 +28,7 @@
#include <asm/immap.h>
-#ifndef CFG_FLASH_CFI
+#ifndef CONFIG_SYS_FLASH_CFI
typedef unsigned short FLASH_PORT_WIDTH;
typedef volatile unsigned short FLASH_PORT_WIDTHV;
@@ -49,14 +49,14 @@
int write_word(flash_info_t * info, FPWV * dest, u16 data);
void inline spin_wheel(void);
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
ulong flash_init(void)
{
ulong size = 0;
ulong fbase = 0;
- fbase = (ulong) CFG_FLASH_BASE;
+ fbase = (ulong) CONFIG_SYS_FLASH_BASE;
flash_get_size((FPWV *) fbase, &flash_info[0]);
flash_get_offsets((ulong) fbase, &flash_info[0]);
fbase += flash_info[0].size;
@@ -64,8 +64,8 @@
/* Protect monitor and environment sectors */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
return size;
}
@@ -77,8 +77,8 @@
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
info->start[0] = base;
- for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) {
- info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ;
+ for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
+ info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
info->protect[k] = 0;
}
}
@@ -174,16 +174,16 @@
info->sector_count = 0;
info->size = 0;
- info->sector_count = CFG_SST_SECT;
- info->size = CFG_SST_SECT * CFG_SST_SECTSZ;
+ info->sector_count = CONFIG_SYS_SST_SECT;
+ info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
/* reset ID mode */
*addr = (FPWV) 0x00F000F0;
- if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CFG_MAX_FLASH_SECT);
- info->sector_count = CFG_MAX_FLASH_SECT;
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
return (info->size);
@@ -235,7 +235,7 @@
start = get_timer(0);
last = start;
- if ((s_last - s_first) == (CFG_SST_SECT - 1)) {
+ if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
if (prot == 0) {
addr = (FPWV *) info->start[0];
@@ -255,7 +255,7 @@
count = 0;
}
- if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = 0x00F0; /* reset to read mode */
@@ -271,7 +271,7 @@
enable_interrupts();
return 0;
- } else if (prot == CFG_SST_SECT) {
+ } else if (prot == CONFIG_SYS_SST_SECT) {
return 1;
}
}
@@ -294,7 +294,7 @@
flag = disable_interrupts();
- base = (FPWV *) (CFG_FLASH_BASE); /* First sector */
+ base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */
base[FLASH_CYCLE1] = 0x00AA; /* unlock */
base[FLASH_CYCLE2] = 0x0055; /* unlock */
@@ -308,7 +308,7 @@
while ((*addr & 0x0080) != 0x0080) {
if (get_timer(start) >
- CFG_FLASH_ERASE_TOUT) {
+ CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = 0x00F0; /* reset to read mode */
@@ -424,7 +424,7 @@
return (2);
}
- base = (FPWV *) (CFG_FLASH_BASE);
+ base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -444,7 +444,7 @@
/* data polling for D7 */
while (res == 0
&& (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (u8) 0x00F000F0; /* reset bank */
res = 1;
}
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 2eb6a04..b39cd4d 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -45,7 +45,7 @@
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
u32 RC, temp;
- RC = (CFG_CLK / 1000000) >> 1;
+ RC = (CONFIG_SYS_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */
@@ -56,7 +56,7 @@
__asm__("nop");
/* Initialize DMR0 */
- dramsize = (CFG_SDRAM_SIZE << 20);
+ dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
temp = (dramsize - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, temp | 1);
__asm__("nop");
@@ -65,7 +65,7 @@
__asm__("nop");
/* Write to this block to initiate precharge */
- *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
__asm__("nop");
/* Set RE bit in DACR */
@@ -81,7 +81,7 @@
mbar_readLong(MCFSIM_DACR0) | 0x0040);
__asm__("nop");
- *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
}
return dramsize;
@@ -104,7 +104,7 @@
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+ volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
@@ -121,7 +121,7 @@
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period
- period = 1000000000 / (CFG_CLK / 2); /* period in ns */
+ period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index f3b1efd..ae69f67 100644
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -43,7 +43,7 @@
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
u32 RC, dramsize;
- RC = (CFG_CLK / 1000000) >> 1;
+ RC = (CONFIG_SYS_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */
@@ -54,7 +54,7 @@
asm("nop");
/* Initialize DMR0 */
- dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
+ dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
asm("nop");
@@ -62,7 +62,7 @@
asm("nop");
/* Write to this block to initiate precharge */
- *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
asm("nop");
/* Set RE bit in DACR */
@@ -78,10 +78,10 @@
mbar_readLong(MCFSIM_DACR0) | 0x0040);
asm("nop");
- *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
}
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
int testdram(void)
@@ -101,7 +101,7 @@
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+ volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
@@ -118,7 +118,7 @@
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period
- period = 1000000000 / (CFG_CLK / 2); /* period in ns */
+ period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c
index e089d5f..5505cc4 100644
--- a/board/freescale/m5271evb/m5271evb.c
+++ b/board/freescale/m5271evb/m5271evb.c
@@ -66,7 +66,7 @@
* PS: 32bit port size
*/
mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
+ MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
| MCF_SDRAMC_DACRn_CASL(1)
| MCF_SDRAMC_DACRn_CBM(3)
| MCF_SDRAMC_DACRn_PS(0));
@@ -85,7 +85,7 @@
asm(" nop");
/* Write to this block to initiate precharge */
- *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
/* Set RE bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
@@ -108,10 +108,10 @@
* Burst Type = Sequential
* Burst Length = 1
*/
- *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
}
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
diff --git a/board/freescale/m5271evb/mii.c b/board/freescale/m5271evb/mii.c
index 78a7028..e79fa19 100644
--- a/board/freescale/m5271evb/mii.c
+++ b/board/freescale/m5271evb/mii.c
@@ -38,14 +38,14 @@
{
if (setclear) {
/* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
} else {
}
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -131,9 +131,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -198,7 +198,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m5272c3/flash.c b/board/freescale/m5272c3/flash.c
index ea0b1fd..586a2cf 100644
--- a/board/freescale/m5272c3/flash.c
+++ b/board/freescale/m5272c3/flash.c
@@ -23,10 +23,10 @@
#include <common.h>
-#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
@@ -74,15 +74,15 @@
int i, j;
ulong size = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_PL160CB & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
- memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
else
@@ -113,8 +113,8 @@
}
flash_protect (FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE + 0x3ffff, &flash_info[0]);
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
return size;
}
@@ -128,8 +128,8 @@
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
-#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
@@ -211,7 +211,7 @@
result = *addr;
/* check timeout */
- if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
@@ -299,7 +299,7 @@
result = *addr;
/* check timeout */
- if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip1 = ERR | TMO;
break;
}
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index d17cb2e..902ca3a 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -40,7 +40,7 @@
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
diff --git a/board/freescale/m5272c3/mii.c b/board/freescale/m5272c3/mii.c
index b30ba80..161c694 100644
--- a/board/freescale/m5272c3/mii.c
+++ b/board/freescale/m5272c3/mii.c
@@ -45,7 +45,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -131,9 +131,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -198,7 +198,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index be19e02..35c9b20 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -44,7 +44,7 @@
gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
/* Set up chip select */
- sdp->sdbar0 = CFG_SDRAM_BASE;
+ sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
/* Set up timing */
@@ -58,34 +58,34 @@
sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
/* Dummy write to start SDRAM */
- *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
| MCF_SDRAMC_SDMR_AD(0x0)
| MCF_SDRAMC_SDMR_CMD;
- *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
sdp->sdmr = 0x058d0000;
- *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
- *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
- *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
- *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Write mode register, clear reset DLL */
sdp->sdmr = 0x018d0000;
- *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
@@ -100,7 +100,7 @@
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3);
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram(void)
diff --git a/board/freescale/m5275evb/mii.c b/board/freescale/m5275evb/mii.c
index 6c7ace9..706d8d6 100644
--- a/board/freescale/m5275evb/mii.c
+++ b/board/freescale/m5275evb/mii.c
@@ -41,7 +41,7 @@
if (setclear) {
/* Enable Ethernet pins */
- if (info->iobase == CFG_FEC0_IOBASE) {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_feci2c |= 0x0F00;
gpio->par_fec0hl |= 0xC0;
} else {
@@ -49,7 +49,7 @@
gpio->par_fec1hl |= 0xC0;
}
} else {
- if (info->iobase == CFG_FEC0_IOBASE) {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_feci2c &= ~0x0F00;
gpio->par_fec0hl &= ~0xC0;
} else {
@@ -61,7 +61,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -147,9 +147,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -214,7 +214,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index 31d6923..b0c9fc8 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -36,7 +36,7 @@
{
u32 dramsize, i, dramclk;
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -45,7 +45,7 @@
if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
{
- dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
MCFSDRAMC_DCR = (0
@@ -55,7 +55,7 @@
/* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0
- | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
+ | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32);
@@ -77,7 +77,7 @@
}
/* Write to this block to initiate precharge */
- *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */
@@ -94,7 +94,7 @@
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
}
diff --git a/board/freescale/m5282evb/mii.c b/board/freescale/m5282evb/mii.c
index 8ae2ec6..7f92514 100644
--- a/board/freescale/m5282evb/mii.c
+++ b/board/freescale/m5282evb/mii.c
@@ -38,15 +38,15 @@
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
- MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+ MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
- MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
+ MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
}
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -132,9 +132,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -199,7 +199,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index f9fa9fb..b4df22f 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -42,7 +42,7 @@
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -50,29 +50,29 @@
}
i--;
- sdram->cs0 = (CFG_SDRAM_BASE | i);
- sdram->cfg1 = CFG_SDRAM_CFG1;
- sdram->cfg2 = CFG_SDRAM_CFG2;
+ sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
- sdram->ctrl = CFG_SDRAM_CTRL | 2;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
- sdram->mode = CFG_SDRAM_EMOD;
- sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+ sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->mode = CFG_SDRAM_MODE;
+ sdram->mode = CONFIG_SYS_SDRAM_MODE;
- sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c
index 8f6abf3..c0f5817 100644
--- a/board/freescale/m5329evb/mii.c
+++ b/board/freescale/m5329evb/mii.c
@@ -50,7 +50,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -134,9 +134,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -201,7 +201,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index f84912e..82492f6 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -83,7 +83,7 @@
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+ *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
/* set up pin configuration */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index a269ee6..376de4b 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -42,7 +42,7 @@
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -50,29 +50,29 @@
}
i--;
- sdram->cs0 = (CFG_SDRAM_BASE | i);
- sdram->cfg1 = CFG_SDRAM_CFG1;
- sdram->cfg2 = CFG_SDRAM_CFG2;
+ sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
- sdram->ctrl = CFG_SDRAM_CTRL | 2;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
- sdram->mode = CFG_SDRAM_EMOD;
- sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+ sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->mode = CFG_SDRAM_MODE;
+ sdram->mode = CONFIG_SYS_SDRAM_MODE;
- sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
diff --git a/board/freescale/m5373evb/mii.c b/board/freescale/m5373evb/mii.c
index 8f6abf3..c0f5817 100644
--- a/board/freescale/m5373evb/mii.c
+++ b/board/freescale/m5373evb/mii.c
@@ -50,7 +50,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -134,9 +134,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -201,7 +201,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 404a9c3..d01b819 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -67,7 +67,7 @@
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+ *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
fbcs->csmr2 &= ~FBCS_CSMR_WP;
/* set up pin configuration */
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 768f40b..088c8c4 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -49,16 +49,16 @@
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 i;
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
- if ((sdram->sdcfg1 == CFG_SDRAM_CFG1) &&
- (sdram->sdcfg2 == CFG_SDRAM_CFG2))
+ if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
+ (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
return dramsize;
for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +67,32 @@
}
i--;
- gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
+ gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
- sdram->sdcs0 = (CFG_SDRAM_BASE | i);
+ sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CFG_SDRAM_CFG1;
- sdram->sdcfg2 = CFG_SDRAM_CFG2;
+ sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
udelay(200);
/* Issue PALL */
- sdram->sdcr = CFG_SDRAM_CTRL | 2;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CFG_SDRAM_CTRL | 4;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
- sdram->sdcr = CFG_SDRAM_CTRL | 4;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CFG_SDRAM_MODE;
+ sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
__asm__("nop");
- sdram->sdmr = CFG_SDRAM_EMOD;
+ sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
__asm__("nop");
- sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+ sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
udelay(100);
#endif
diff --git a/board/freescale/m54451evb/mii.c b/board/freescale/m54451evb/mii.c
index 5a4330c..6e24736 100644
--- a/board/freescale/m54451evb/mii.c
+++ b/board/freescale/m54451evb/mii.c
@@ -43,7 +43,7 @@
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
else
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
@@ -51,7 +51,7 @@
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
@@ -59,7 +59,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -135,9 +135,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -202,7 +202,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 100682a..293b5b0 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -45,13 +45,13 @@
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
- dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 i;
- dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -59,33 +59,33 @@
}
i--;
- gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
+ gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
- sdram->sdcs0 = (CFG_SDRAM_BASE | i);
- sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
+ sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
- sdram->sdcfg1 = CFG_SDRAM_CFG1;
- sdram->sdcfg2 = CFG_SDRAM_CFG2;
+ sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
- sdram->sdcr = CFG_SDRAM_CTRL | 2;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
- sdram->sdmr = CFG_SDRAM_EMOD | 0x408;
- sdram->sdmr = CFG_SDRAM_MODE | 0x300;
+ sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
+ sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
udelay(500);
/* Issue PALL */
- sdram->sdcr = CFG_SDRAM_CTRL | 2;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
/* Perform two refresh cycles */
- sdram->sdcr = CFG_SDRAM_CTRL | 4;
- sdram->sdcr = CFG_SDRAM_CTRL | 4;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->sdmr = CFG_SDRAM_MODE | 0x200;
+ sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
- sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
#endif
@@ -175,11 +175,11 @@
#include <flash.h>
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
{
- int sect[] = CFG_ATMEL_SECT;
- int sectsz[] = CFG_ATMEL_SECTSZ;
+ int sect[] = CONFIG_SYS_ATMEL_SECT;
+ int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
int i, j, k;
- if (base != CFG_ATMEL_BASE)
+ if (base != CONFIG_SYS_ATMEL_BASE)
return 0;
info->flash_id = 0x01000000;
@@ -205,9 +205,9 @@
info->name = "CFI conformant";
info->size = 0;
- info->sector_count = CFG_ATMEL_TOTALSECT;
+ info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
info->start[0] = base;
- for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
+ for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
info->size += sect[i] * sectsz[i];
for (j = 0; j < sect[i]; j++, k++) {
@@ -218,4 +218,4 @@
return 1;
}
-#endif /* CFG_FLASH_CFI */
+#endif /* CONFIG_SYS_FLASH_CFI */
diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c
index 0be5439..c195191 100644
--- a/board/freescale/m54455evb/mii.c
+++ b/board/freescale/m54455evb/mii.c
@@ -43,7 +43,7 @@
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
else
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
@@ -51,7 +51,7 @@
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
@@ -59,7 +59,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -152,9 +152,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -219,7 +219,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 6d7d270..9f1ec38 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -43,53 +43,53 @@
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
-#ifdef CFG_DRAMSZ1
+#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
- siu->drv = CFG_SDRAM_DRVSTRENGTH;
+ siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
- dramsize = CFG_DRAMSZ * 0x100000;
+ dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
- siu->cs0cfg = (CFG_SDRAM_BASE | i);
+ siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CFG_DRAMSZ1
- temp = CFG_DRAMSZ1 * 0x100000;
+#ifdef CONFIG_SYS_DRAMSZ1
+ temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (temp == (1 << i))
break;
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i);
+ siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CFG_SDRAM_CFG1;
- sdram->cfg2 = CFG_SDRAM_CFG2;
+ sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
- sdram->ctrl = CFG_SDRAM_CTRL | 2;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
- sdram->mode = CFG_SDRAM_EMOD;
- sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+ sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->mode = CFG_SDRAM_MODE;
+ sdram->mode = CONFIG_SYS_SDRAM_MODE;
- sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
udelay(100);
diff --git a/board/freescale/m547xevb/mii.c b/board/freescale/m547xevb/mii.c
index 5b2683b..4d11506 100644
--- a/board/freescale/m547xevb/mii.c
+++ b/board/freescale/m547xevb/mii.c
@@ -41,12 +41,12 @@
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
if (setclear) {
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq |= 0xF000;
else
gpio->par_feci2cirq |= 0x0FC0;
} else {
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq &= 0x0FFF;
else
gpio->par_feci2cirq &= 0xF03F;
@@ -54,7 +54,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -140,9 +140,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -217,7 +217,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
index e6510c9..4a2a5c7 100644
--- a/board/freescale/m548xevb/m548xevb.c
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -44,49 +44,49 @@
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- siu->drv = CFG_SDRAM_DRVSTRENGTH;
+ siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
- dramsize = CFG_DRAMSZ * 0x100000;
+ dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
- siu->cs0cfg = (CFG_SDRAM_BASE | i);
+ siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CFG_DRAMSZ1
- temp = CFG_DRAMSZ1 * 0x100000;
+#ifdef CONFIG_SYS_DRAMSZ1
+ temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (temp == (1 << i))
break;
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i);
+ siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CFG_SDRAM_CFG1;
- sdram->cfg2 = CFG_SDRAM_CFG2;
+ sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
- sdram->ctrl = CFG_SDRAM_CTRL | 2;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
- sdram->mode = CFG_SDRAM_EMOD;
- sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+ sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
- sdram->ctrl = CFG_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->mode = CFG_SDRAM_MODE;
+ sdram->mode = CONFIG_SYS_SDRAM_MODE;
- sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
udelay(100);
diff --git a/board/freescale/m548xevb/mii.c b/board/freescale/m548xevb/mii.c
index 5b2683b..4d11506 100644
--- a/board/freescale/m548xevb/mii.c
+++ b/board/freescale/m548xevb/mii.c
@@ -41,12 +41,12 @@
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
if (setclear) {
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq |= 0xF000;
else
gpio->par_feci2cirq |= 0x0FC0;
} else {
- if (info->iobase == CFG_FEC0_IOBASE)
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq &= 0x0FFF;
else
gpio->par_feci2cirq &= 0xF03F;
@@ -54,7 +54,7 @@
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -140,9 +140,9 @@
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -217,7 +217,7 @@
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S
index 521301f..b9495fd 100644
--- a/board/freescale/mpc7448hpc2/asm_init.S
+++ b/board/freescale/mpc7448hpc2/asm_init.S
@@ -123,7 +123,7 @@
/* Initialize pointer to Tsi108 register space */
- LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
+ LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
ori r4,r29,TSI108_PB_REG_OFFSET
/* Check Processor Version Number */
@@ -214,12 +214,12 @@
ori r4,r29,TSI108_PB_REG_OFFSET
-#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
+#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE)
/* Relocate (if required) Tsi108 registers. Set new value for
* PB_REG_BAR:
* Note we are in the 32-bit address mode.
*/
- LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
+ LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
stw r5,PB_REG_BAR(r4)
andis. r29,r5,0xFFFF
sync
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
index cfdbed5..117b951 100644
--- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c
+++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -60,7 +60,7 @@
{
int l_type = 0;
- printf ("BOARD: %s\n", CFG_BOARD_NAME);
+ printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
return (l_type);
}
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
index 9c40b72..74bb564 100644
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ b/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -88,7 +88,7 @@
{0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
};
-#ifdef CFG_CLK_SPREAD
+#ifdef CONFIG_SYS_CLK_SPREAD
typedef struct {
ulong ctrl0;
ulong ctrl1;
@@ -111,7 +111,7 @@
{0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
{0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
};
-#endif /* CFG_CLK_SPREAD */
+#endif /* CONFIG_SYS_CLK_SPREAD */
/*
* Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
@@ -129,7 +129,7 @@
ulong i;
/* Detect PB clock freq. */
- i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+ i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
return pb_clk_sel[i] * 1000000;
@@ -146,7 +146,7 @@
ulong i;
gd->mem_clk = 0;
- i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
+ i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
CG_PWRUP_STATUS);
i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
switch (i) {
@@ -182,7 +182,7 @@
volatile ulong *reg_ptr;
reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
for (i = 0; i < 32; i++) {
*reg_ptr++ = 0x00000201; /* SWAP ENABLED */
@@ -194,7 +194,7 @@
/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
- out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
0x80000001);
__asm__ __volatile__ ("sync");
@@ -202,7 +202,7 @@
* read from SDRAM)
*/
- temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
+ temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
__asm__ __volatile__ ("sync");
/*
@@ -221,7 +221,7 @@
* initialize pointer to LUT associated with PB_OCN_BAR1
*/
reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
for (i = 0; i < 32; i++) {
*reg_ptr++ = pb2ocn_lut1[i].lower;
@@ -232,73 +232,73 @@
/* Base addresses for CS0, CS1, CS2, CS3 */
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
0x00100000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
0x00200000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
0x00300000);
__asm__ __volatile__ ("sync");
/* Masks for HLP banks */
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
/* Set CTRL0 values for banks */
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
/* Set banks to latched mode, enabled, and other default settings */
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
@@ -306,7 +306,7 @@
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
*/
- out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
0xE0000011);
__asm__ __volatile__ ("sync");
@@ -314,7 +314,7 @@
* immediate read from SDRAM)
*/
- temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
+ temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
__asm__ __volatile__ ("sync");
/*
@@ -341,7 +341,7 @@
temp = get_cpu_type ();
if ((CPU_750FX == temp) || (CPU_750GX == temp))
- out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
0x00009955);
#endif /* DISABLE_PBM */
@@ -351,27 +351,27 @@
*/
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_PFAB_BAR0_UPPER, 0);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
0xFB000001);
__asm__ __volatile__ ("sync");
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
- temp = in32(CFG_TSI108_CSR_BASE +
+ temp = in32(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp &= ~0xFF00; /* Clear the BUS_NUM field */
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
temp);
/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
0);
__asm__ __volatile__ ("sync");
@@ -379,7 +379,7 @@
* and maps it as a IO address.
*/
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
0x00000001);
__asm__ __volatile__ ("sync");
@@ -405,7 +405,7 @@
*/
reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
#ifdef DISABLE_PBM
@@ -442,7 +442,7 @@
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
@@ -450,9 +450,9 @@
* ( 0 is the best choice for easy mapping)
*/
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
0x00000000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
0x00000000);
__asm__ __volatile__ ("sync");
@@ -470,7 +470,7 @@
* set pointer to LUT associated with PCI P2O_BAR3
*/
reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
reg_val = 0x00000004; /* Destination port = SDC */
@@ -490,19 +490,19 @@
/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
reg_val =
- in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+ in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_P2O_PAGE_SIZES);
reg_val &= ~0x00FF;
reg_val |= 0x0071;
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
/* Set 64-bit base PCI bus address for window (0x20000000) */
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
0x00000000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
0x20000000);
__asm__ __volatile__ ("sync");
@@ -511,17 +511,17 @@
#ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */
- reg_val = in32(CFG_TSI108_CSR_BASE +
+ reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val |= 0x02;
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
reg_val);
__asm__ __volatile__ ("sync");
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
0x00000000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
- CFG_TSI108_CSR_BASE);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
+ CONFIG_SYS_TSI108_CSR_BASE);
__asm__ __volatile__ ("sync");
#endif
@@ -530,9 +530,9 @@
* Finally enable PCI/X Bus Master and Memory Space access
*/
- reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
+ reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
reg_val |= 0x06;
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
__asm__ __volatile__ ("sync");
#endif /* CONFIG_PCI */
@@ -546,10 +546,10 @@
* PB_INT[3] -> MCP (CPU1)
* Set interrupt controller outputs as Level_Sensitive/Active_Low
*/
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
__asm__ __volatile__ ("sync");
/*
@@ -584,42 +584,42 @@
int misc_init_r (void)
{
-#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
+#ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;
/* Ensure that Spread-Spectrum is disabled */
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
*/
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x002e0044); /* D = 0.25% */
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
0x00000039); /* BWADJ */
/* Initialize PLL0: CG_PB_CLKO */
/* Detect PB clock freq. */
- i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+ i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
- out32 (CFG_TSI108_CSR_BASE +
+ out32 (CONFIG_SYS_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
- out32 (CFG_TSI108_CSR_BASE +
+ out32 (CONFIG_SYS_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
/* Wait and set SSEN for both PLL0 and 1 */
udelay (1000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x802e0044); /* D=0.25% */
- out32 (CFG_TSI108_CSR_BASE +
+ out32 (CONFIG_SYS_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
0x80000000 | pll0_config[i].ctrl0);
-#endif /* CFG_CLK_SPREAD */
+#endif /* CONFIG_SYS_CLK_SPREAD */
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
diff --git a/board/freescale/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c
index 7fcc874..e03852f 100644
--- a/board/freescale/mpc8260ads/flash.c
+++ b/board/freescale/mpc8260ads/flash.c
@@ -52,7 +52,7 @@
#define INTEL_FINISHED 0x80808080
#define INTEL_OK 0x80808080
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
@@ -66,8 +66,8 @@
ulong size = 0, sect_start, sect_size = 0, bank_size;
ushort sect_count = 0;
int i, j, nbanks;
- vu_long *addr = (vu_long *)CFG_FLASH_BASE;
- vu_long *bcsr = (vu_long *)CFG_BCSR;
+ vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
+ vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
switch (bcsr[2] & 0xF) {
case 0:
@@ -80,11 +80,11 @@
nbanks = 1;
break;
default: /* Unsupported configurations */
- nbanks = CFG_MAX_FLASH_BANKS;
+ nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
}
- if (nbanks > CFG_MAX_FLASH_BANKS)
- nbanks = CFG_MAX_FLASH_BANKS;
+ if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
+ nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
for (i = 0; i < nbanks; i++) {
*addr = INTEL_READID; /* Read Intelligent Identifier */
@@ -98,9 +98,9 @@
break;
default:
flash_info[i].flash_id = FLASH_UNKNOWN;
- sect_count = CFG_MAX_FLASH_SECT;
+ sect_count = CONFIG_SYS_MAX_FLASH_SECT;
sect_size =
- CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
+ CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
}
}
else
@@ -127,10 +127,10 @@
}
if (size == 0) { /* Unknown flash, fill with hard-coded values */
- sect_start = CFG_FLASH_BASE;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ sect_start = CONFIG_SYS_FLASH_BASE;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
+ flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
flash_info[i].sector_count = sect_count;
for (j = 0; j < sect_count; j++) {
flash_info[i].start[j] = sect_start;
@@ -138,20 +138,20 @@
sect_start += sect_size;
}
}
- size = CFG_FLASH_SIZE;
+ size = CONFIG_SYS_FLASH_SIZE;
}
else
- for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].size = 0;
flash_info[i].sector_count = 0;
}
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@@ -274,7 +274,7 @@
enable_interrupts();
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = INTEL_RESET; /* reset bank */
return 1;
@@ -338,7 +338,7 @@
/* data polling for D7 */
start = get_timer (0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
printf("Write timed out\n");
rc = 1;
break;
@@ -454,7 +454,7 @@
start = get_timer(0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
printf("Flash lock bit operation timed out\n");
rc = 1;
break;
@@ -480,7 +480,7 @@
addr = (vu_long *)(info->start[i]);
*addr = INTEL_LOCKBIT; /* Sector lock bit */
*addr = INTEL_PROTECT; /* set */
- udelay(CFG_FLASH_LOCK_TOUT * 1000);
+ udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
}
if (flag)
diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c
index 8ab7d35..49a88bb 100644
--- a/board/freescale/mpc8260ads/mpc8260ads.c
+++ b/board/freescale/mpc8260ads/mpc8260ads.c
@@ -58,32 +58,32 @@
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
-#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
+ /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
+ /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
+ /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
+ /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
+ /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
+ /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
+ /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
+ /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
+ /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
+ /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
+ /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
+ /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
+ /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
+ /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
@@ -102,34 +102,34 @@
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
@@ -147,32 +147,32 @@
/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
- /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
+ /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
+ /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
/* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
- /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
+ /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
+ /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
#else
- /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
- /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
+ /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
+ /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
#else
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
@@ -223,10 +223,10 @@
void reset_phy (void)
{
- vu_long *bcsr = (vu_long *)CFG_BCSR;
+ vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
/* Reset the PHY */
-#if CFG_PHY_ADDR == 0
+#if CONFIG_SYS_PHY_ADDR == 0
bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
udelay(2);
bcsr[1] |= FETH1_RST;
@@ -234,16 +234,16 @@
bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
udelay(2);
bcsr[3] |= FETH2_RST;
-#endif /* CFG_PHY_ADDR == 0 */
+#endif /* CONFIG_SYS_PHY_ADDR == 0 */
udelay(1000);
#ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
/*
* Do not bypass Rx/Tx (de)scrambler (fix configuration error)
* Enable autonegotiation.
*/
- bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+ bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
+ bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#else
/*
@@ -254,14 +254,14 @@
*/
/* Advertise all capabilities */
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
+ bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_ANAR, 0x01E1);
/* Do not bypass Rx/Tx (de)scrambler */
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
+ bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_DCR, 0x0000);
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+ bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
#endif /* CONFIG_MII */
}
@@ -274,10 +274,10 @@
int board_early_init_f (void)
{
- vu_long *bcsr = (vu_long *)CFG_BCSR;
+ vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
#ifdef CONFIG_PCI
- volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
+ volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
/* mask alll the PCI interrupts */
pci_ic->pci_int_mask |= 0xfff00000;
@@ -289,19 +289,19 @@
bcsr[1] &= ~RS232EN_2;
#endif
-#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
immap->im_siu_conf.sc_siumcr =
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
}
-#endif /* CONFIG_ADSTYPE != CFG_8260ADS */
+#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
return 0;
}
@@ -310,16 +310,16 @@
phys_size_t initdram (int board_type)
{
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
long int msize = 32;
-#elif CONFIG_ADSTYPE == CFG_8272ADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
long int msize = 64;
#else
long int msize = 16;
#endif
-#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *ramaddr, c = 0xff;
uint or;
@@ -332,33 +332,33 @@
immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
immap->im_siu_conf.sc_tescr1 = 0x00004000;
- memctl->memc_mptpr = CFG_MPTPR;
-#ifdef CFG_LSDRAM_BASE
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+#ifdef CONFIG_SYS_LSDRAM_BASE
/*
Initialise local bus SDRAM only if the pins
are configured as local bus pins and not as PCI.
The configuration is determined by the HRCW.
*/
if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
- memctl->memc_lsrt = CFG_LSRT;
-#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
+ memctl->memc_lsrt = CONFIG_SYS_LSRT;
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
memctl->memc_or3 = 0xFF803280;
- memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
+ memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
#else /* CS4 */
memctl->memc_or4 = 0xFFC01480;
- memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
- memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
- ramaddr = (uchar *) CFG_LSDRAM_BASE;
+ memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
+ memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
+ ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
*ramaddr = c;
- memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
+ memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
for (i = 0; i < 8; i++)
*ramaddr = c;
- memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
+ memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
*ramaddr = c;
- memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+ memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
}
-#endif /* CFG_LSDRAM_BASE */
+#endif /* CONFIG_SYS_LSDRAM_BASE */
/* Init 60x bus SDRAM */
#ifdef CONFIG_SPD_EEPROM
@@ -498,14 +498,14 @@
#endif /* SPD_DEBUG */
}
#else /* !CONFIG_SPD_EEPROM */
- or = CFG_OR2;
- psdmr = CFG_PSDMR;
- psrt = CFG_PSRT;
+ or = CONFIG_SYS_OR2;
+ psdmr = CONFIG_SYS_PSDMR;
+ psrt = CONFIG_SYS_PSRT;
#endif /* CONFIG_SPD_EEPROM */
memctl->memc_psrt = psrt;
memctl->memc_or2 = or;
- memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
- ramaddr = (uchar *) CFG_SDRAM_BASE;
+ memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
+ ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
*ramaddr = c;
memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
@@ -516,7 +516,7 @@
*ramaddr = c;
memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
*ramaddr = c;
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
/* return total 60x bus SDRAM size */
return (msize * 1024 * 1024);
@@ -524,13 +524,13 @@
int checkboard (void)
{
-#if CONFIG_ADSTYPE == CFG_8260ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CFG_8266ADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CFG_PQ2FADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CFG_8272ADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
puts ("Board: Motorola MPC8272ADS\n");
#else
puts ("Board: unknown\n");
diff --git a/board/freescale/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c
index b4cdcd9..06dde36 100644
--- a/board/freescale/mpc8266ads/flash.c
+++ b/board/freescale/mpc8266ads/flash.c
@@ -29,11 +29,11 @@
#include <common.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
@@ -56,7 +56,7 @@
unsigned long flash_init (void)
{
#ifndef CONFIG_MPC8266ADS
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
#endif
@@ -71,7 +71,7 @@
#endif
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
/* set the default sector offset */
@@ -88,20 +88,20 @@
#ifndef CONFIG_MPC8266ADS
/* Remap FLASH according to real size */
- memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+ memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
(memctl->memc_br1 & ~(BR_BA_MSK));
#endif
/* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+ size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size;
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@@ -336,7 +336,7 @@
*addr = 0xFFFFFFFF; /* reset bank */
return 1;
}
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
return 1;
@@ -461,7 +461,7 @@
start = get_timer (0);
flag = 0;
while (((csr = *addr) & 0x80808080) != 0x80808080) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
@@ -499,7 +499,7 @@
start = get_timer (0);
while(*addr != 0x80808080){
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout on clearing Block Lock Bit\n");
*addr = 0xFFFFFFFF; /* reset bank */
return 1;
diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c
index 090a534..66acc41 100644
--- a/board/freescale/mpc8266ads/mpc8266ads.c
+++ b/board/freescale/mpc8266ads/mpc8266ads.c
@@ -224,7 +224,7 @@
void reset_phy(void)
{
- volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
+ volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
/* reset the FEC port */
bcsr->bcsr1 &= ~FETH_RST;
@@ -234,8 +234,8 @@
int board_early_init_f (void)
{
- volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
- volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT;
+ volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
+ volatile pci_ic_t *pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
@@ -254,17 +254,17 @@
phys_size_t initdram(int board_type)
{
/* Autoinit part stolen from board/sacsng/sacsng.c */
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0xff;
- volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
- uint psdmr = CFG_PSDMR;
+ volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+ uint psdmr = CONFIG_SYS_PSDMR;
int i;
uint psrt = 0x21; /* for no SPD */
uint chipselects = 1; /* for no SPD */
- uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
- uint or = CFG_OR2_PRELIM; /* for no SPD */
+ uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
+ uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
uint data_width;
uint rows;
uint banks;
@@ -286,7 +286,7 @@
/*
* Read the SDRAM SPD EEPROM via I2C.
*/
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
spd_size = data;
@@ -506,13 +506,13 @@
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_psrt = psrt;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
memctl->memc_or2 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
@@ -536,7 +536,7 @@
{
ramaddr += sdram_size;
- memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
memctl->memc_or3 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index ebb703d..9ffd4bf 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -36,8 +36,8 @@
int board_early_init_f(void)
{
-#ifndef CFG_8313ERDB_BROKEN_PMC
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
gd->flags |= GD_FLG_SILENT;
@@ -55,28 +55,28 @@
#ifndef CONFIG_NAND_SPL
static struct pci_region pci_regions[] = {
{
- bus_start: CFG_PCI1_MEM_BASE,
- phys_start: CFG_PCI1_MEM_PHYS,
- size: CFG_PCI1_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI1_MMIO_BASE,
- phys_start: CFG_PCI1_MMIO_PHYS,
- size: CFG_PCI1_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
- bus_start: CFG_PCI1_IO_BASE,
- phys_start: CFG_PCI1_IO_PHYS,
- size: CFG_PCI1_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
@@ -88,14 +88,14 @@
/*
* Configure PCI Local Access Windows
*/
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
#endif
@@ -135,13 +135,13 @@
void board_init_f(ulong bootflag)
{
board_early_init_f();
- NS16550_init((NS16550_t)(CFG_IMMR + 0x4500),
- CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
- relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
- CFG_NAND_U_BOOT_RELOC);
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
@@ -155,8 +155,8 @@
return;
if (c == '\n')
- NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r');
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
- NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c);
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 128cd40..99e8a43 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -35,7 +35,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
static void resume_from_sleep(void)
{
u32 magic = *(u32 *)0;
@@ -58,15 +58,15 @@
*/
static long fixed_sdram(void)
{
- u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-#ifndef CFG_RAMBOOT
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
/*
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
@@ -75,29 +75,29 @@
udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
- im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
/* Currently we use only one CS, so disable the other bank. */
im->ddr.cs_config[1] = 0;
- im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI;
+ im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
else
#endif
- im->ddr.sdram_cfg = CFG_SDRAM_CFG;
+ im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE_2;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
sync();
/* enable DDR controller */
@@ -109,7 +109,7 @@
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile lbus83xx_t *lbc = &im->lbus;
u32 msize;
@@ -120,11 +120,11 @@
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
- lbc->lbcr = CFG_LBC_LBCR;
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
sync();
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
resume_from_sleep();
#endif
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index 0330218..ea4b04f 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -35,7 +35,7 @@
int board_early_init_f(void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
gd->flags |= GD_FLG_SILENT;
@@ -48,7 +48,7 @@
u8 val8;
i2c_set_bus_num(0);
- if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+ if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
return val8;
else
return 0;
@@ -76,28 +76,28 @@
static struct pci_region pci_regions[] = {
{
- bus_start: CFG_PCI_MEM_BASE,
- phys_start: CFG_PCI_MEM_PHYS,
- size: CFG_PCI_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+ size: CONFIG_SYS_PCI_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI_MMIO_BASE,
- phys_start: CFG_PCI_MMIO_PHYS,
- size: CFG_PCI_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+ size: CONFIG_SYS_PCI_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
- bus_start: CFG_PCI_IO_BASE,
- phys_start: CFG_PCI_IO_PHYS,
- size: CFG_PCI_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI_IO_BASE,
+ phys_start: CONFIG_SYS_PCI_IO_PHYS,
+ size: CONFIG_SYS_PCI_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
@@ -109,10 +109,10 @@
/*
* Configure PCI Local Access Windows
*/
- pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
- pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index 3714c2c..ead7b1e 100644
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -56,13 +56,13 @@
*/
static long fixed_sdram(void)
{
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
- u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
/*
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
@@ -71,27 +71,27 @@
udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
/* Currently we use only one CS, so disable the other bank. */
im->ddr.cs_config[1] = 0;
- im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
else
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
sync();
/* enable DDR controller */
@@ -103,7 +103,7 @@
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index f5220ab..8680a19 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -75,14 +75,14 @@
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
@@ -95,12 +95,12 @@
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
- msize = CFG_DDR_SIZE;
+ msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1) {
@@ -109,18 +109,18 @@
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
__asm__ __volatile__ ("sync");
udelay(200);
@@ -137,28 +137,28 @@
static struct pci_region pci_regions[] = {
{
- bus_start: CFG_PCI1_MEM_BASE,
- phys_start: CFG_PCI1_MEM_PHYS,
- size: CFG_PCI1_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI1_MMIO_BASE,
- phys_start: CFG_PCI1_MMIO_PHYS,
- size: CFG_PCI1_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
- bus_start: CFG_PCI1_IO_BASE,
- phys_start: CFG_PCI1_IO_PHYS,
- size: CFG_PCI1_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
@@ -167,10 +167,10 @@
clk->occr |= 0xe0000000;
/* Configure PCI Local Access Windows */
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg, 0);
@@ -186,7 +186,7 @@
}
#endif
-#if defined(CFG_I2C_MAC_OFFSET)
+#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
int mac_read_from_eeprom(void)
{
uchar buf[28];
@@ -196,9 +196,9 @@
unsigned char enetvar[32];
/* Read MAC addresses from EEPROM */
- if (eeprom_read(CFG_I2C_EEPROM_ADDR, CFG_I2C_MAC_OFFSET, buf, 28)) {
+ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
- CFG_I2C_EEPROM_ADDR);
+ CONFIG_SYS_I2C_EEPROM_ADDR);
} else {
if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
printf("Reading MAC from EEPROM\n");
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index 4ad6e9d..d4d4479 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -76,7 +76,7 @@
int board_early_init_f(void)
{
- volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
+ volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
/* Enable flash write */
bcsr[9] &= ~0x08;
@@ -96,14 +96,14 @@
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
@@ -116,12 +116,12 @@
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
- msize = CFG_DDR_SIZE;
+ msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1) {
@@ -130,21 +130,21 @@
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CFG_DDR_SIZE != 128)
+#if (CONFIG_SYS_DDR_SIZE != 128)
#warning Currenly any ddr size other than 128 is not supported
#endif
- im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
__asm__ __volatile__ ("sync");
udelay(200);
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index b030422..2a48dd2 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -67,7 +67,7 @@
volatile pcictrl83xx_t *pci_ctrl;
volatile pciconf83xx_t *pci_conf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
@@ -93,7 +93,7 @@
hose[0].first_busno = 0;
hose[0].last_busno = 0xff;
pci_setup_indirect(&hose[0],
- (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+ (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
reg16 = 0xff;
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
@@ -134,7 +134,7 @@
u32 val32;
u32 dev;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
clk = (clk83xx_t *) & immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
@@ -161,10 +161,10 @@
/*
* Configure PCI Local Access Windows
*/
- pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
- pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
/*
@@ -172,26 +172,26 @@
*/
/* PCI mem space - prefetch */
- pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr =
POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
/* PCI mmio - non-prefetch mem space */
- pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
/* PCI IO space */
- pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
/*
* Configure PCI Inbound Translation Windows
*/
- pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
- pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
+ pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
+ pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 =
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
@@ -209,31 +209,31 @@
/* PCI memory prefetch space */
pci_set_region(hose[0].regions + 0,
- CFG_PCI_MEM_BASE,
- CFG_PCI_MEM_PHYS,
- CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+ CONFIG_SYS_PCI_MEM_BASE,
+ CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
/* PCI memory space */
pci_set_region(hose[0].regions + 1,
- CFG_PCI_MMIO_BASE,
- CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI_MMIO_BASE,
+ CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose[0].regions + 2,
- CFG_PCI_IO_BASE,
- CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI_IO_BASE,
+ CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
/* System memory space */
pci_set_region(hose[0].regions + 3,
- CFG_PCI_SLV_MEM_LOCAL,
- CFG_PCI_SLV_MEM_BUS,
- CFG_PCI_SLV_MEM_SIZE,
+ CONFIG_SYS_PCI_SLV_MEM_LOCAL,
+ CONFIG_SYS_PCI_SLV_MEM_BUS,
+ CONFIG_SYS_PCI_SLV_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose[0].region_count = 4;
pci_setup_indirect(&hose[0],
- (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+ (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
pci_register_hose(hose);
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ef947fe..fa44360 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -44,12 +44,12 @@
int board_early_init_f (void)
{
- volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+ volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
/* Enable flash write */
bcsr[1] &= ~0x01;
-#ifdef CFG_USE_MPC834XSYS_USB_PHY
+#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
/* Use USB PHY on SYS board */
bcsr[5] |= 0x02;
#endif
@@ -61,14 +61,14 @@
phys_size_t initdram (int board_type)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
@@ -96,12 +96,12 @@
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
- msize = CFG_DDR_SIZE;
+ msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size>>1, ddr_size_log2++) {
@@ -109,36 +109,36 @@
return -1;
}
}
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CFG_DDR_SIZE != 256)
+#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
- im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS;
- im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+ im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
im->ddr.cs_config[1] = 0;
im->ddr.cs_config[3] = 0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.sdram_cfg =
SDRAM_CFG_SREN
@@ -150,9 +150,9 @@
/* for 32-bit mode burst length is 8 */
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
#endif
- im->ddr.sdram_mode = CFG_DDR_MODE;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
udelay(200);
@@ -160,7 +160,7 @@
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
-#endif/*!CFG_SPD_EEPROM*/
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
int checkboard (void)
@@ -181,41 +181,41 @@
/*
* if MPC8349EMDS is soldered with SDRAM
*/
-#if defined(CFG_BR2_PRELIM) \
- && defined(CFG_OR2_PRELIM) \
- && defined(CFG_LBLAWBAR2_PRELIM) \
- && defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CONFIG_SYS_BR2_PRELIM) \
+ && defined(CONFIG_SYS_OR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
/*
* Initialize SDRAM memory on the Local Bus.
*/
void sdram_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile lbus83xx_t *lbc= &immap->lbus;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CFG_LBC_LBCR;
- lbc->mrtpr = CFG_LBC_MRTPR;
- lbc->lsrt = CFG_LBC_LSRT;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
@@ -243,12 +243,12 @@
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CFG_LBC_LSDMR_4;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
asm("sync");
*sdram_addr = 0xff;
udelay(100);
@@ -273,14 +273,14 @@
void spi_cs_activate(struct spi_slave *slave)
{
- volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+ volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat &= ~SPI_CS_MASK;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+ volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat |= SPI_CS_MASK;
}
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 9c19e30..ad7bf5d 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -33,21 +33,21 @@
static struct pci_region pci1_regions[] = {
{
- bus_start: CFG_PCI1_MEM_BASE,
- phys_start: CFG_PCI1_MEM_PHYS,
- size: CFG_PCI1_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI1_IO_BASE,
- phys_start: CFG_PCI1_IO_PHYS,
- size: CFG_PCI1_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
},
{
- bus_start: CFG_PCI1_MMIO_BASE,
- phys_start: CFG_PCI1_MMIO_PHYS,
- size: CFG_PCI1_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
@@ -55,21 +55,21 @@
#ifdef CONFIG_MPC83XX_PCI2
static struct pci_region pci2_regions[] = {
{
- bus_start: CFG_PCI2_MEM_BASE,
- phys_start: CFG_PCI2_MEM_PHYS,
- size: CFG_PCI2_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI2_IO_BASE,
- phys_start: CFG_PCI2_IO_PHYS,
- size: CFG_PCI2_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
flags: PCI_REGION_IO
},
{
- bus_start: CFG_PCI2_MMIO_BASE,
- phys_start: CFG_PCI2_MMIO_PHYS,
- size: CFG_PCI2_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
@@ -135,7 +135,7 @@
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
#ifndef CONFIG_MPC83XX_PCI2
@@ -152,10 +152,10 @@
udelay(2000);
/* Configure PCI Local Access Windows */
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
udelay(2000);
@@ -170,7 +170,7 @@
#else
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
@@ -181,10 +181,10 @@
udelay(2000);
/* Configure PCI Local Access Windows */
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
udelay(2000);
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 0a20e2b..3169536 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -42,11 +42,11 @@
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 ddr_size; /* The size of RAM, in bytes */
u32 ddr_size_log2 = 0;
- for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
+ for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
if (ddr_size & 1) {
return -1;
}
@@ -55,11 +55,11 @@
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
/* Only one CS0 for DDR */
im->ddr.csbnds[0].csbnds = 0x0000000f;
- im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
@@ -67,15 +67,15 @@
debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
im->ddr.sdram_mode =
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
im->ddr.sdram_interval =
(0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
SDRAM_INTERVAL_BSTOPRE_SHIFT);
- im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
udelay(200);
@@ -87,7 +87,7 @@
debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
- return CFG_DDR_SIZE;
+ return CONFIG_SYS_DDR_SIZE;
}
#endif
@@ -130,7 +130,7 @@
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#ifdef CONFIG_DDR_ECC
volatile ddr83xx_t *ddr = &im->ddr;
@@ -140,7 +140,7 @@
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#ifdef CONFIG_SPD_EEPROM
msize = spd_sdram();
#else
@@ -196,7 +196,7 @@
don't enable compact flash for U-Boot.
*/
- vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0);
+ vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
*vsc7385_cpuctrl |= 0x0c;
#endif
@@ -220,11 +220,11 @@
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
};
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile lbus83xx_t *lbus = &immap->lbus;
- lbus->bank[3].br = CFG_BR3_PRELIM;
- lbus->bank[3].or = CFG_OR3_PRELIM;
+ lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
+ lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
@@ -265,26 +265,26 @@
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
-#ifdef CFG_I2C_RTC_ADDR
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
u8 ds1339_data[17];
#endif
-#ifdef CFG_I2C_EEPROM_ADDR
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
static u8 eeprom_data[] = /* HRCW data */
{
0xAA, 0x55, 0xAA, /* Preamble */
0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
0x02, 0x40, /* RCWL ADDR=0x0_0900 */
- (CFG_HRCW_LOW >> 24) & 0xFF,
- (CFG_HRCW_LOW >> 16) & 0xFF,
- (CFG_HRCW_LOW >> 8) & 0xFF,
- CFG_HRCW_LOW & 0xFF,
+ (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
+ (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
+ (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
+ CONFIG_SYS_HRCW_LOW & 0xFF,
0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
0x02, 0x41, /* RCWH ADDR=0x0_0904 */
- (CFG_HRCW_HIGH >> 24) & 0xFF,
- (CFG_HRCW_HIGH >> 16) & 0xFF,
- (CFG_HRCW_HIGH >> 8) & 0xFF,
- CFG_HRCW_HIGH & 0xFF
+ (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
+ (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
+ (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
+ CONFIG_SYS_HRCW_HIGH & 0xFF
};
u8 data[sizeof(eeprom_data)];
@@ -292,22 +292,22 @@
printf("Board revision: ");
i2c_set_bus_num(1);
- if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
- else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
else {
printf("Unknown\n");
rc = 1;
}
-#ifdef CFG_I2C_EEPROM_ADDR
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
i2c_set_bus_num(0);
- if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
if (i2c_write
- (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
+ (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
sizeof(eeprom_data)) != 0) {
puts("Failure writing the HRCW to EEPROM via I2C.\n");
rc = 1;
@@ -319,10 +319,10 @@
}
#endif
-#ifdef CFG_I2C_RTC_ADDR
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
i2c_set_bus_num(1);
- if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
+ if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
== 0) {
/* Work-around for MPC8349E-mITX bug #13601.
@@ -366,7 +366,7 @@
*/
if (i2c_write
- (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data,
+ (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
sizeof(ds1339_data))) {
puts("Failure writing to the RTC via I2C.\n");
rc = 1;
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
index d33edf3..fd2c172 100644
--- a/board/freescale/mpc8349itx/pci.c
+++ b/board/freescale/mpc8349itx/pci.c
@@ -37,8 +37,8 @@
DECLARE_GLOBAL_DATA_PTR;
/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8349itx_config_table[] = {
@@ -92,7 +92,7 @@
u32 dev;
struct pci_controller *hose;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
clk = (clk83xx_t *) & immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
@@ -111,8 +111,8 @@
#ifdef CONFIG_HARD_I2C
i2c_set_bus_num(1);
/* Read the PCI_M66EN jumper setting */
- if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
- (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
+ if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
+ (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
if (reg8 & I2C_8574_PCI66)
clk->occr = 0xff000000; /* 66 MHz PCI */
else
@@ -150,10 +150,10 @@
/*
* Configure PCI Local Access Windows
*/
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
/*
@@ -161,18 +161,18 @@
*/
/* PCI1 mem space - prefetch */
- pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
/* PCI1 IO space */
- pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
/* PCI1 mmio - non-prefetch mem space */
- pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
/*
@@ -192,19 +192,19 @@
/* PCI memory prefetch space */
pci_set_region(hose->regions + 0,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
/* PCI memory space */
pci_set_region(hose->regions + 1,
- CFG_PCI1_MMIO_BASE,
- CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI1_MMIO_BASE,
+ CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
/* System memory space */
pci_set_region(hose->regions + 3,
@@ -215,7 +215,7 @@
hose->region_count = 4;
pci_setup_indirect(hose,
- (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+ (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
pci_register_hose(hose);
@@ -251,18 +251,18 @@
*/
/* PCI2 mem space - prefetch */
- pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
/* PCI2 IO space */
- pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
/* PCI2 mmio - non-prefetch mem space */
- pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
/*
@@ -283,19 +283,19 @@
/* PCI memory prefetch space */
pci_set_region(hose->regions + 0,
- CFG_PCI2_MEM_BASE,
- CFG_PCI2_MEM_PHYS,
- CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+ CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_PHYS,
+ CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
/* PCI memory space */
pci_set_region(hose->regions + 1,
- CFG_PCI2_MMIO_BASE,
- CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI2_MMIO_BASE,
+ CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 2,
- CFG_PCI2_IO_BASE,
- CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO);
/* System memory space */
pci_set_region(hose->regions + 3,
@@ -306,7 +306,7 @@
hose->region_count = 4;
pci_setup_indirect(hose,
- (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
+ (CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384));
pci_register_hose(hose);
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 5c3b5db..fc0a0e5 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -92,8 +92,8 @@
int board_early_init_f(void)
{
- u8 *bcsr = (u8 *)CFG_BCSR;
- const immap_t *immr = (immap_t *)CFG_IMMR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+ const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* Enable flash write */
bcsr[0xa] &= ~0x04;
@@ -124,14 +124,14 @@
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
@@ -159,12 +159,12 @@
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
- msize = CFG_DDR_SIZE;
+ msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1) {
@@ -173,42 +173,42 @@
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CFG_DDR_SIZE != 256)
+#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
- im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
im->ddr.csbnds[0].csbnds = 0x00000007;
im->ddr.csbnds[1].csbnds = 0x0008000f;
- im->ddr.cs_config[0] = CFG_DDR_CONFIG;
- im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+ im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.sdram_cfg = CFG_DDR_CONTROL;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
udelay(200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
-#endif /*!CFG_SPD_EEPROM */
+#endif /*!CONFIG_SYS_SPD_EEPROM */
int checkboard(void)
{
@@ -219,34 +219,34 @@
/*
* if MPC8360EMDS is soldered with SDRAM
*/
-#if defined(CFG_BR2_PRELIM) \
- && defined(CFG_OR2_PRELIM) \
- && defined(CFG_LBLAWBAR2_PRELIM) \
- && defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CONFIG_SYS_BR2_PRELIM) \
+ && defined(CONFIG_SYS_OR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
/*
* Initialize SDRAM memory on the Local Bus.
*/
void sdram_init(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile lbus83xx_t *lbc = &immap->lbus;
- uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
+ uint *sdram_addr = (uint *) CONFIG_SYS_LBC_SDRAM_BASE;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/*setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CFG_LBC_LBCR;
- lbc->mrtpr = CFG_LBC_MRTPR;
- lbc->lsrt = CFG_LBC_LSRT;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
- lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
asm("sync");
*sdram_addr = 0xff;
udelay(100);
@@ -254,7 +254,7 @@
/*
* We need do 8 times auto refresh operation.
*/
- lbc->lsdmr = CFG_LBC_LSDMR_2;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
asm("sync");
*sdram_addr = 0xff; /* 1 times */
udelay(100);
@@ -274,13 +274,13 @@
udelay(100);
/* Mode register write operation */
- lbc->lsdmr = CFG_LBC_LSDMR_4;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
asm("sync");
*(sdram_addr + 0xcc) = 0xff;
udelay(100);
/* Normal operation */
- lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
@@ -294,7 +294,7 @@
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
- const immap_t *immr = (immap_t *)CFG_IMMR;
+ const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index 4a0d460..935aca26 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -67,7 +67,7 @@
volatile pcictrl83xx_t *pci_ctrl;
volatile pciconf83xx_t *pci_conf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
@@ -93,7 +93,7 @@
hose[0].first_busno = 0;
hose[0].last_busno = 0xff;
pci_setup_indirect(&hose[0],
- (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+ (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
reg16 = 0xff;
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
@@ -134,7 +134,7 @@
u32 val32;
u32 dev;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
clk = (clk83xx_t *) & immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
@@ -161,10 +161,10 @@
/*
* Configure PCI Local Access Windows
*/
- pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
- pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
/*
@@ -172,26 +172,26 @@
*/
/* PCI mem space - prefetch */
- pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr =
POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
/* PCI mmio - non-prefetch mem space */
- pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
/* PCI IO space */
- pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
/*
* Configure PCI Inbound Translation Windows
*/
- pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
- pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
+ pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
+ pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 =
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
@@ -209,31 +209,31 @@
/* PCI memory prefetch space */
pci_set_region(hose[0].regions + 0,
- CFG_PCI_MEM_BASE,
- CFG_PCI_MEM_PHYS,
- CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+ CONFIG_SYS_PCI_MEM_BASE,
+ CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
/* PCI memory space */
pci_set_region(hose[0].regions + 1,
- CFG_PCI_MMIO_BASE,
- CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI_MMIO_BASE,
+ CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose[0].regions + 2,
- CFG_PCI_IO_BASE,
- CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI_IO_BASE,
+ CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
/* System memory space */
pci_set_region(hose[0].regions + 3,
- CFG_PCI_SLV_MEM_LOCAL,
- CFG_PCI_SLV_MEM_BUS,
- CFG_PCI_SLV_MEM_SIZE,
+ CONFIG_SYS_PCI_SLV_MEM_LOCAL,
+ CONFIG_SYS_PCI_SLV_MEM_BUS,
+ CONFIG_SYS_PCI_SLV_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose[0].region_count = 4;
pci_setup_indirect(&hose[0],
- (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+ (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
pci_register_hose(hose);
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
index 61d7000..af3b8ce 100644
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c
+++ b/board/freescale/mpc8360erdk/mpc8360erdk.c
@@ -214,7 +214,7 @@
int board_early_init_r(void)
{
- void *reg = (void *)(CFG_IMMR + 0x14a8);
+ void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
u32 val;
/*
@@ -233,12 +233,12 @@
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
- msize = CFG_DDR_SIZE;
+ msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1)
@@ -248,18 +248,18 @@
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
udelay(200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
@@ -271,14 +271,14 @@
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
@@ -300,28 +300,28 @@
static struct pci_region pci_regions[] = {
{
- .bus_start = CFG_PCI1_MEM_BASE,
- .phys_start = CFG_PCI1_MEM_PHYS,
- .size = CFG_PCI1_MEM_SIZE,
+ .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+ .size = CONFIG_SYS_PCI1_MEM_SIZE,
.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
},
{
- .bus_start = CFG_PCI1_MMIO_BASE,
- .phys_start = CFG_PCI1_MMIO_PHYS,
- .size = CFG_PCI1_MMIO_SIZE,
+ .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+ .size = CONFIG_SYS_PCI1_MMIO_SIZE,
.flags = PCI_REGION_MEM,
},
{
- .bus_start = CFG_PCI1_IO_BASE,
- .phys_start = CFG_PCI1_IO_PHYS,
- .size = CFG_PCI1_IO_SIZE,
+ .bus_start = CONFIG_SYS_PCI1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+ .size = CONFIG_SYS_PCI1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions, };
@@ -338,10 +338,10 @@
udelay(2000);
/* Configure PCI Local Access Windows */
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg, 0);
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
index 8b44a0f..8e22e13 100644
--- a/board/freescale/mpc8360erdk/nand.c
+++ b/board/freescale/mpc8360erdk/nand.c
@@ -18,7 +18,7 @@
#include <linux/mtd/fsl_upm.h>
#include <nand.h>
-static struct immap *im = (struct immap *)CFG_IMMR;
+static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
static const u32 upm_array[] = {
0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
@@ -70,7 +70,7 @@
static struct fsl_upm_nand fun = {
.upm = {
- .io_addr = (void *)CFG_NAND_BASE,
+ .io_addr = (void *)CONFIG_SYS_NAND_BASE,
},
.width = 8,
.upm_cmd_offset = 8,
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 8003ec1..6c537e2 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -24,7 +24,7 @@
int board_early_init_f(void)
{
- u8 *bcsr = (u8 *)CFG_BCSR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
/* Enable flash write */
bcsr[0x9] &= ~0x04;
@@ -32,7 +32,7 @@
bcsr[0xe] = 0xff;
#ifdef CONFIG_FSL_SERDES
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
u32 spridr = in_be32(&immr->sysconf.spridr);
/* we check only part num, and don't look for CPU revisions */
@@ -77,7 +77,7 @@
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
@@ -104,43 +104,43 @@
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
- u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-#if (CFG_DDR_SIZE != 512)
+#if (CONFIG_SYS_DDR_SIZE != 512)
#warning Currenly any ddr size other than 512 is not supported
#endif
- im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
udelay(50000);
- im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
udelay(1000);
- im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
udelay(1000);
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
__asm__ __volatile__("sync");
udelay(1000);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
- return CFG_DDR_SIZE;
+ return CONFIG_SYS_DDR_SIZE;
}
-#endif /*!CFG_SPD_EEPROM */
+#endif /*!CONFIG_SYS_SPD_EEPROM */
int checkboard(void)
{
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
index ab90979..24cc130 100644
--- a/board/freescale/mpc837xemds/pci.c
+++ b/board/freescale/mpc837xemds/pci.c
@@ -21,28 +21,28 @@
#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
{
- bus_start: CFG_PCI_MEM_BASE,
- phys_start: CFG_PCI_MEM_PHYS,
- size: CFG_PCI_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+ size: CONFIG_SYS_PCI_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI_MMIO_BASE,
- phys_start: CFG_PCI_MMIO_PHYS,
- size: CFG_PCI_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+ size: CONFIG_SYS_PCI_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
- bus_start: CFG_PCI_IO_BASE,
- phys_start: CFG_PCI_IO_PHYS,
- size: CFG_PCI_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI_IO_BASE,
+ phys_start: CONFIG_SYS_PCI_IO_PHYS,
+ size: CONFIG_SYS_PCI_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
@@ -52,10 +52,10 @@
udelay(2000);
/* Configure PCI Local Access Windows */
- pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
- pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
udelay(2000);
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index e547b51..18a21a1 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -20,17 +20,17 @@
#include <spd_sdram.h>
#include <vsc7385.h>
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CFG_MEMTEST_START,
- CFG_MEMTEST_END);
+ CONFIG_SYS_MEMTEST_START,
+ CONFIG_SYS_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
@@ -66,7 +66,7 @@
phys_size_t initdram(int board_type)
{
- immap_t *im = (immap_t *) CFG_IMMR;
+ immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
@@ -92,40 +92,40 @@
************************************************************************/
int fixed_sdram(void)
{
- immap_t *im = (immap_t *) CFG_IMMR;
- u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+ immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
udelay(50000);
- im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
udelay(1000);
- im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
udelay(1000);
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
sync();
udelay(1000);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
- return CFG_DDR_SIZE;
+ return CONFIG_SYS_DDR_SIZE;
}
-#endif /*!CFG_SPD_EEPROM */
+#endif /*!CONFIG_SYS_SPD_EEPROM */
int checkboard(void)
{
@@ -136,7 +136,7 @@
int board_early_init_f(void)
{
#ifdef CONFIG_FSL_SERDES
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
u32 spridr = in_be32(&immr->sysconf.spridr);
/* we check only part num, and don't look for CPU revisions */
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
index 26e7320..8bb31fc 100644
--- a/board/freescale/mpc837xerdb/pci.c
+++ b/board/freescale/mpc837xerdb/pci.c
@@ -17,28 +17,28 @@
#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
{
- bus_start: CFG_PCI_MEM_BASE,
- phys_start: CFG_PCI_MEM_PHYS,
- size: CFG_PCI_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+ size: CONFIG_SYS_PCI_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI_MMIO_BASE,
- phys_start: CFG_PCI_MMIO_PHYS,
- size: CFG_PCI_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+ size: CONFIG_SYS_PCI_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
- bus_start: CFG_PCI_IO_BASE,
- phys_start: CFG_PCI_IO_PHYS,
- size: CFG_PCI_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI_IO_BASE,
+ phys_start: CONFIG_SYS_PCI_IO_PHYS,
+ size: CONFIG_SYS_PCI_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
@@ -48,10 +48,10 @@
udelay(2000);
/* Configure PCI Local Access Windows */
- pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
- pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg, 0);
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index cdf5215..8013d41 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -28,15 +28,15 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
- SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 3066b24..f634e17 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -86,34 +86,34 @@
phys_size_t fixed_sdram (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
uint d_init;
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
- ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE_1;
- ddr->sdram_mode_2 = CFG_DDR_MODE_2;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->sdram_data_init = CFG_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
#if defined (CONFIG_DDR_ECC)
- ddr->err_int_en = CFG_DDR_ERR_INT_EN;
- ddr->err_disable = CFG_DDR_ERR_DIS;
- ddr->err_sbe = CFG_DDR_SBE;
+ ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+ ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+ ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
asm("sync;isync");
udelay(500);
- ddr->sdram_cfg = CFG_DDR_CONTROL;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
d_init = 1;
@@ -156,7 +156,7 @@
void
pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint sdrs2_io_sel =
(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
@@ -176,7 +176,7 @@
#ifdef CONFIG_PCIE3
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
@@ -194,23 +194,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE3_MEM_BASE,
- CFG_PCIE3_MEM_PHYS,
- CFG_PCIE3_MEM_SIZE,
+ CONFIG_SYS_PCIE3_MEM_BASE,
+ CONFIG_SYS_PCIE3_MEM_PHYS,
+ CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE3_IO_BASE,
- CFG_PCIE3_IO_PHYS,
- CFG_PCIE3_IO_SIZE,
+ CONFIG_SYS_PCIE3_IO_BASE,
+ CONFIG_SYS_PCIE3_IO_PHYS,
+ CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -234,7 +234,7 @@
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
@@ -253,32 +253,32 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
-#ifdef CFG_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
pci_set_region(hose->regions + 3,
- CFG_PCIE1_MEM_BASE2,
- CFG_PCIE1_MEM_PHYS2,
- CFG_PCIE1_MEM_SIZE2,
+ CONFIG_SYS_PCIE1_MEM_BASE2,
+ CONFIG_SYS_PCIE1_MEM_PHYS2,
+ CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
hose->region_count++;
#endif
@@ -303,7 +303,7 @@
#ifdef CONFIG_PCIE2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
@@ -321,32 +321,32 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE2_MEM_BASE,
- CFG_PCIE2_MEM_PHYS,
- CFG_PCIE2_MEM_SIZE,
+ CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE2_IO_BASE,
- CFG_PCIE2_IO_PHYS,
- CFG_PCIE2_IO_SIZE,
+ CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
-#ifdef CFG_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
/* outbound memory */
pci_set_region(hose->regions + 3,
- CFG_PCIE2_MEM_BASE2,
- CFG_PCIE2_MEM_PHYS2,
- CFG_PCIE2_MEM_SIZE2,
+ CONFIG_SYS_PCIE2_MEM_BASE2,
+ CONFIG_SYS_PCIE2_MEM_PHYS2,
+ CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
hose->region_count++;
#endif
@@ -370,7 +370,7 @@
#ifdef CONFIG_PCI1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
@@ -394,31 +394,31 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
-#ifdef CFG_PCI1_MEM_BASE2
+#ifdef CONFIG_SYS_PCI1_MEM_BASE2
/* outbound memory */
pci_set_region(hose->regions + 3,
- CFG_PCI1_MEM_BASE2,
- CFG_PCI1_MEM_PHYS2,
- CFG_PCI1_MEM_SIZE2,
+ CONFIG_SYS_PCI1_MEM_BASE2,
+ CONFIG_SYS_PCI1_MEM_PHYS2,
+ CONFIG_SYS_PCI1_MEM_SIZE2,
PCI_REGION_MEM);
hose->region_count++;
#endif
@@ -442,7 +442,7 @@
int board_early_init_r(void)
{
unsigned int i;
- const unsigned int flashbase = CFG_FLASH_BASE;
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = 1;
/*
@@ -610,7 +610,7 @@
int is_sata_supported(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint sdrs2_io_sel =
(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 28a9fa8..7ccc150 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -47,23 +47,23 @@
/* TLB 1 */
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
};
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index 3b8bd05..7dd8f29 100644
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -46,13 +46,13 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
/* This is not so much the SDRAM map as it is the whole localbus map. */
- SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 005e4d9..7dccd37 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -71,7 +71,7 @@
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/*
@@ -116,8 +116,8 @@
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -137,10 +137,10 @@
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
} else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
} else {
/*
@@ -155,7 +155,7 @@
lbc->lcrr = 0x10000004;
}
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
udelay(200);
/*
@@ -176,52 +176,52 @@
void
sdram_init(void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CFG_OR2_PRELIM;
- lbc->br2 = CFG_BR2_PRELIM;
- lbc->lbcr = CFG_LBC_LBCR;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM;
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("sync");
/*
* Configure the SDRAM controller.
*/
- lbc->lsdmr = CFG_LBC_LSDMR_1;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_2;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_3;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_4;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_5;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -234,15 +234,15 @@
************************************************************************/
long int fixed_sdram (void)
{
- #ifndef CFG_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+ #ifndef CONFIG_SYS_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
@@ -251,14 +251,14 @@
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
index 4fe2862..2ec3ccc 100644
--- a/board/freescale/mpc8540ads/tlb.c
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -46,7 +46,7 @@
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@ -54,7 +54,7 @@
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@ -87,7 +87,7 @@
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
@@ -95,7 +95,7 @@
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_64M, 1),
@@ -103,7 +103,7 @@
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
- SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
@@ -117,11 +117,11 @@
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_64M, 1),
#endif
diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c
index fbf2bdc..8e3de22 100644
--- a/board/freescale/mpc8541cds/law.c
+++ b/board/freescale/mpc8541cds/law.c
@@ -47,12 +47,12 @@
*/
struct law_entry law_table[] = {
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index de3a791..7c35c35 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -200,7 +200,7 @@
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
@@ -258,7 +258,7 @@
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -290,8 +290,8 @@
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -337,56 +337,56 @@
void
sdram_init(void)
{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CFG_OR2_PRELIM;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
- lbc->br2 = CFG_BR2_PRELIM;
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
- lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
/*
* Determine which address lines to use baed on CPU board rev.
*/
cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
} else {
/*
* Assume something unable to identify itself is
* really old, and likely has lines 16/17 mapped.
*/
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
}
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -396,7 +396,7 @@
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -406,7 +406,7 @@
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -415,7 +415,7 @@
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
index c5434a0..bf957c0 100644
--- a/board/freescale/mpc8541cds/tlb.c
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -46,7 +46,7 @@
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@ -54,7 +54,7 @@
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
- SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@ -88,7 +88,7 @@
* 0xe200_0000 16M PCI1 IO
* 0xe300_0000 16M PCI2 IO
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
@@ -96,7 +96,7 @@
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_64M, 1),
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
index 54cf36b..317ba26 100644
--- a/board/freescale/mpc8544ds/law.c
+++ b/board/freescale/mpc8544ds/law.c
@@ -28,15 +28,15 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
/* contains both PCIE3 MEM & IO space */
- SET_LAW(CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index eaf6fa3..826180c 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -44,9 +44,9 @@
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %lx\n",(ulong)&gur->porpllsr);
@@ -108,7 +108,7 @@
void
pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -125,7 +125,7 @@
#ifdef CONFIG_PCIE3
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
@@ -143,32 +143,32 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE3_MEM_BASE,
- CFG_PCIE3_MEM_PHYS,
- CFG_PCIE3_MEM_SIZE,
+ CONFIG_SYS_PCIE3_MEM_BASE,
+ CONFIG_SYS_PCIE3_MEM_PHYS,
+ CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE3_IO_BASE,
- CFG_PCIE3_IO_PHYS,
- CFG_PCIE3_IO_SIZE,
+ CONFIG_SYS_PCIE3_IO_BASE,
+ CONFIG_SYS_PCIE3_IO_PHYS,
+ CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
-#ifdef CFG_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
/* outbound memory */
pci_set_region(hose->regions + 3,
- CFG_PCIE3_MEM_BASE2,
- CFG_PCIE3_MEM_PHYS2,
- CFG_PCIE3_MEM_SIZE2,
+ CONFIG_SYS_PCIE3_MEM_BASE2,
+ CONFIG_SYS_PCIE3_MEM_PHYS2,
+ CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
hose->region_count++;
#endif
@@ -185,7 +185,7 @@
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((u32 *)CFG_PCIE3_MEM_BASE);
+ in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
} else {
printf (" PCIE3: disabled\n");
}
@@ -197,7 +197,7 @@
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
@@ -215,32 +215,32 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
-#ifdef CFG_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
pci_set_region(hose->regions + 3,
- CFG_PCIE1_MEM_BASE2,
- CFG_PCIE1_MEM_PHYS2,
- CFG_PCIE1_MEM_SIZE2,
+ CONFIG_SYS_PCIE1_MEM_BASE2,
+ CONFIG_SYS_PCIE1_MEM_PHYS2,
+ CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
hose->region_count++;
#endif
@@ -265,7 +265,7 @@
#ifdef CONFIG_PCIE2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
@@ -283,32 +283,32 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE2_MEM_BASE,
- CFG_PCIE2_MEM_PHYS,
- CFG_PCIE2_MEM_SIZE,
+ CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE2_IO_BASE,
- CFG_PCIE2_IO_PHYS,
- CFG_PCIE2_IO_SIZE,
+ CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
-#ifdef CFG_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
/* outbound memory */
pci_set_region(hose->regions + 3,
- CFG_PCIE2_MEM_BASE2,
- CFG_PCIE2_MEM_PHYS2,
- CFG_PCIE2_MEM_SIZE2,
+ CONFIG_SYS_PCIE2_MEM_BASE2,
+ CONFIG_SYS_PCIE2_MEM_PHYS2,
+ CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
hose->region_count++;
#endif
@@ -332,7 +332,7 @@
#ifdef CONFIG_PCI1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
@@ -356,31 +356,31 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
-#ifdef CFG_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
/* outbound memory */
pci_set_region(hose->regions + 3,
- CFG_PCIE3_MEM_BASE2,
- CFG_PCIE3_MEM_PHYS2,
- CFG_PCIE3_MEM_SIZE2,
+ CONFIG_SYS_PCIE3_MEM_BASE2,
+ CONFIG_SYS_PCIE3_MEM_PHYS2,
+ CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
hose->region_count++;
#endif
@@ -470,7 +470,7 @@
{
#ifdef CONFIG_TSEC_ENET
struct tsec_info_struct tsec_info[2];
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
int num = 0;
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
index 40e0499..c7442b2 100644
--- a/board/freescale/mpc8544ds/tlb.c
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
@@ -45,28 +45,28 @@
* 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCIE 8,9,a,b
*/
- SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -75,7 +75,7 @@
* 0xe000_0000 1M CCSRBAR
* 0xe100_0000 255M PCI IO range
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
@@ -83,7 +83,7 @@
* TLB 5: 64M Non-cacheable, guarded
* 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
*/
- SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
};
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 34b9d1c..98748aa 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -51,22 +51,22 @@
*/
struct law_entry law_table[] = {
-#ifdef CFG_PCI1_MEM_PHYS
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
#endif
-#ifdef CFG_PCI2_MEM_PHYS
- SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
#endif
-#ifdef CFG_PCIE1_MEM_PHYS
- SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
#endif
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CFG_RIO_MEM_PHYS
- SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
};
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 84d3850..875628d 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -49,8 +49,8 @@
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
@@ -106,7 +106,7 @@
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -140,8 +140,8 @@
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -174,46 +174,46 @@
void
sdram_init(void)
{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CFG_OR2_PRELIM;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
- lbc->br2 = CFG_BR2_PRELIM;
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
- lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
/*
* MPC8548 uses "new" 15-16 style addressing.
*/
cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -223,7 +223,7 @@
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -233,7 +233,7 @@
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -242,7 +242,7 @@
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -290,14 +290,14 @@
void
pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
#ifdef CONFIG_PCI1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
@@ -323,24 +323,24 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -392,7 +392,7 @@
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
@@ -412,23 +412,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index ab99af7..eab212a 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -46,7 +46,7 @@
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@ -54,22 +54,22 @@
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCI1/PCIE 8,9,a,b
*/
- SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
-#ifdef CFG_RIO_MEM_PHYS
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
#endif
@@ -80,7 +80,7 @@
* 0xe210_0000 1M PCI2 IO
* 0xe300_0000 1M PCIe IO
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
@@ -88,7 +88,7 @@
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_64M, 1),
@@ -96,7 +96,7 @@
* TLB 7: 64M Non-cacheable, guarded
* 0xf8000000 64M CADMUS registers, relocated L2SRAM
*/
- SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
};
diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c
index fbf2bdc..8e3de22 100644
--- a/board/freescale/mpc8555cds/law.c
+++ b/board/freescale/mpc8555cds/law.c
@@ -47,12 +47,12 @@
*/
struct law_entry law_table[] = {
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 826056a..4cd25b6 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -198,7 +198,7 @@
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
@@ -256,7 +256,7 @@
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -290,8 +290,8 @@
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -337,55 +337,55 @@
void
sdram_init(void)
{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CFG_OR2_PRELIM;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
- lbc->br2 = CFG_BR2_PRELIM;
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
- lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
/*
* Determine which address lines to use baed on CPU board rev.
*/
cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
} else {
/*
* Assume something unable to identify itself is
* really old, and likely has lines 16/17 mapped.
*/
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
}
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -395,7 +395,7 @@
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -405,7 +405,7 @@
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -414,7 +414,7 @@
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
index c5434a0..bf957c0 100644
--- a/board/freescale/mpc8555cds/tlb.c
+++ b/board/freescale/mpc8555cds/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -46,7 +46,7 @@
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@ -54,7 +54,7 @@
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
- SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@ -88,7 +88,7 @@
* 0xe200_0000 16M PCI1 IO
* 0xe300_0000 16M PCI2 IO
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
@@ -96,7 +96,7 @@
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_64M, 1),
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
index 3b8bd05..7dd8f29 100644
--- a/board/freescale/mpc8560ads/law.c
+++ b/board/freescale/mpc8560ads/law.c
@@ -46,13 +46,13 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
/* This is not so much the SDRAM map as it is the whole localbus map. */
- SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 851fc57..4fe1d85 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -217,7 +217,7 @@
void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
- volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+ volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
#endif
/* reset Giga bit Ethernet port if needed here */
@@ -275,7 +275,7 @@
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/*
@@ -320,8 +320,8 @@
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -341,10 +341,10 @@
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
} else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
} else {
/*
@@ -359,7 +359,7 @@
lbc->lcrr = 0x10000004;
}
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
udelay(200);
/*
@@ -380,52 +380,52 @@
void
sdram_init(void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CFG_OR2_PRELIM;
- lbc->br2 = CFG_BR2_PRELIM;
- lbc->lbcr = CFG_LBC_LBCR;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM;
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("sync");
/*
* Configure the SDRAM controller.
*/
- lbc->lsdmr = CFG_LBC_LSDMR_1;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_2;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_3;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_4;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
- lbc->lsdmr = CFG_LBC_LSDMR_5;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
asm("sync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -438,15 +438,15 @@
************************************************************************/
long int fixed_sdram (void)
{
- #ifndef CFG_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+ #ifndef CONFIG_SYS_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
@@ -455,14 +455,14 @@
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
index 4fe2862..2ec3ccc 100644
--- a/board/freescale/mpc8560ads/tlb.c
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -46,7 +46,7 @@
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@ -54,7 +54,7 @@
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@ -87,7 +87,7 @@
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
@@ -95,7 +95,7 @@
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_64M, 1),
@@ -103,7 +103,7 @@
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
- SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
@@ -117,11 +117,11 @@
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_64M, 1),
#endif
diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
index 791a50f..30676e1 100644
--- a/board/freescale/mpc8568mds/bcsr.c
+++ b/board/freescale/mpc8568mds/bcsr.c
@@ -27,9 +27,9 @@
void enable_8568mds_duart()
{
- volatile uint* duart_mux = (uint *)(CFG_CCSRBAR + 0xe0060);
- volatile uint* devices = (uint *)(CFG_CCSRBAR + 0xe0070);
- volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+ volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
+ volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
*duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
*devices = 0; /* Enable all peripheral devices */
@@ -38,21 +38,21 @@
void enable_8568mds_flash_write()
{
- volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
bcsr[9] |= 0x01;
}
void disable_8568mds_flash_write()
{
- volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
bcsr[9] &= ~(0x01);
}
void enable_8568mds_qe_mdio()
{
- u8 *bcsr = (u8 *)(CFG_BCSR);
+ u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
bcsr[7] |= 0x01;
}
@@ -60,7 +60,7 @@
#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
void reset_8568mds_uccs(void)
{
- volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
/* Turn off UCC1 & UCC2 */
out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index 3bc24c5..da7b6dc 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -50,13 +50,13 @@
*/
struct law_entry law_table[] = {
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
- SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index f9e35cc..eab1900 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -123,10 +123,10 @@
enable_8568mds_qe_mdio();
#endif
-#ifdef CFG_I2C2_OFFSET
+#ifdef CONFIG_SYS_I2C2_OFFSET
/* Enable I2C2_SCL and I2C2_SDA */
volatile struct par_io *port_c;
- port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
+ port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
port_c->cpdir2 |= 0x0f000000;
port_c->cppar2 &= ~0x0f000000;
port_c->cppar2 |= 0x0a000000;
@@ -158,7 +158,7 @@
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -192,8 +192,8 @@
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -223,44 +223,44 @@
void
sdram_init(void)
{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CFG_OR2_PRELIM;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
- lbc->br2 = CFG_BR2_PRELIM;
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
- lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
/*
* MPC8568 uses "new" 15-16 style addressing.
*/
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+ lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -270,7 +270,7 @@
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -280,7 +280,7 @@
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -289,7 +289,7 @@
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -371,7 +371,7 @@
void
pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -379,7 +379,7 @@
{
pib_init();
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
@@ -403,23 +403,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -440,7 +440,7 @@
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
@@ -460,23 +460,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
index 7565176..1077552 100644
--- a/board/freescale/mpc8568mds/tlb.c
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -47,7 +47,7 @@
* 0xff000000 16M FLASH (upper half)
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@ -55,7 +55,7 @@
* TLBe 1: 16M Non-cacheable, guarded
* 0xfe000000 16M FLASH (lower half)
*/
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
@@ -64,7 +64,7 @@
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
@@ -74,7 +74,7 @@
* 0xe200_0000 8M PCI1 IO
* 0xe280_0000 8M PCIe IO
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
@@ -82,7 +82,7 @@
* TLBe 4: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
@@ -92,7 +92,7 @@
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
- SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256K, 1),
};
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index d69b593..9f11902 100644
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -28,13 +28,13 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
- SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 70b548b..b6eb28e 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -83,34 +83,34 @@
phys_size_t fixed_sdram (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
uint d_init;
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
- ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE_1;
- ddr->sdram_mode_2 = CFG_DDR_MODE_2;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->sdram_data_init = CFG_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
#if defined (CONFIG_DDR_ECC)
- ddr->err_int_en = CFG_DDR_ERR_INT_EN;
- ddr->err_disable = CFG_DDR_ERR_DIS;
- ddr->err_sbe = CFG_DDR_SBE;
+ ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+ ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+ ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
asm("sync;isync");
udelay(500);
- ddr->sdram_cfg = CFG_DDR_CONTROL;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
d_init = 1;
@@ -148,7 +148,7 @@
#ifdef CONFIG_PCI
void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -168,7 +168,7 @@
#ifdef CONFIG_PCIE3
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
@@ -188,23 +188,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE3_MEM_BASE,
- CFG_PCIE3_MEM_PHYS,
- CFG_PCIE3_MEM_SIZE,
+ CONFIG_SYS_PCIE3_MEM_BASE,
+ CONFIG_SYS_PCIE3_MEM_PHYS,
+ CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE3_IO_BASE,
- CFG_PCIE3_IO_PHYS,
- CFG_PCIE3_IO_SIZE,
+ CONFIG_SYS_PCIE3_IO_BASE,
+ CONFIG_SYS_PCIE3_IO_PHYS,
+ CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -225,7 +225,7 @@
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
PCI_BASE_ADDRESS_1, &temp32);
- if (temp32 >= CFG_PCIE3_MEM_PHYS) {
+ if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
debug(" uli1572 read to %x\n", temp32);
in_be32((unsigned *)temp32);
}
@@ -240,7 +240,7 @@
#ifdef CONFIG_PCIE2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
@@ -259,23 +259,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE2_MEM_BASE,
- CFG_PCIE2_MEM_PHYS,
- CFG_PCIE2_MEM_SIZE,
+ CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE2_IO_BASE,
- CFG_PCIE2_IO_PHYS,
- CFG_PCIE2_IO_SIZE,
+ CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -297,7 +297,7 @@
#endif
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 1) || (host_agent == 4) ||
@@ -316,23 +316,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -360,7 +360,7 @@
int board_early_init_r(void)
{
unsigned int i;
- const unsigned int flashbase = CFG_FLASH_BASE;
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = 2;
/*
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 965356a..46d9e4a 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -28,16 +28,16 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -52,32 +52,32 @@
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS, CFG_PCIE3_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x40000000, CFG_PCIE3_MEM_PHYS + 0x40000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x50000000, CFG_PCIE3_MEM_PHYS + 0x50000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
};
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index 91b922b..2aad28a 100644
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -29,16 +29,16 @@
struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
#endif
- SET_LAW(CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 130f7aa..5faeca1 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -48,7 +48,7 @@
/* called before any console output */
int board_early_init_f(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
@@ -98,7 +98,7 @@
int checkboard(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
@@ -129,7 +129,7 @@
dram_size = fixed_sdram();
#endif
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
puts(" DDR: ");
return dram_size;
#endif
@@ -153,8 +153,8 @@
long int fixed_sdram(void)
{
-#if !defined(CFG_RAMBOOT)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_SYS_RAMBOOT)
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
uint d_init;
@@ -201,7 +201,7 @@
return 512 * 1024 * 1024;
#endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif
@@ -242,7 +242,7 @@
void pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
@@ -255,7 +255,7 @@
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_configured = (io_sel == 1) || (io_sel == 4);
@@ -271,23 +271,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -312,7 +312,7 @@
#ifdef CONFIG_PCIE2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
@@ -330,23 +330,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCIE2_MEM_BASE,
- CFG_PCIE2_MEM_PHYS,
- CFG_PCIE2_MEM_SIZE,
+ CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCIE2_IO_BASE,
- CFG_PCIE2_IO_PHYS,
- CFG_PCIE2_IO_SIZE,
+ CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -370,7 +370,7 @@
#ifdef CONFIG_PCI1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
@@ -383,23 +383,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 4db941c..cd25d4a 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -43,7 +43,7 @@
void diu_set_pixel_clock(unsigned int pixclock)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
unsigned long speed_ccb, temp, pixval;
@@ -137,7 +137,7 @@
}
U_BOOT_CMD(
- diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp,
+ diufb, CONFIG_SYS_MAXARGS, 1, mpc8610diu_init_show_bmp,
"diufb init | addr - Init or Display BMP file\n",
"init\n - initialize DIU\n"
"addr\n - display bmp at address 'addr'\n"
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 2d6c3c1..182b4c5 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -47,18 +47,18 @@
struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
- SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
- SET_LAW((CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
#endif
- SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 97f7f49..fcaaacb 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -65,7 +65,7 @@
dram_size = fixed_sdram();
#endif
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
puts(" DDR: ");
return dram_size;
#endif
@@ -89,23 +89,23 @@
long int
fixed_sdram(void)
{
-#if !defined(CFG_RAMBOOT)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#if !defined(CONFIG_SYS_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
- ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode_1 = CFG_DDR_MODE_1;
- ddr->sdram_mode_2 = CFG_DDR_MODE_2;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->sdram_data_init = CFG_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
- ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
- ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
+ ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000008D;
@@ -117,16 +117,16 @@
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
- ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
+ ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
- ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
- ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+ ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
#endif
asm("sync; isync");
udelay(500);
#endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
@@ -164,7 +164,7 @@
void pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
@@ -172,7 +172,7 @@
#ifdef CONFIG_PCI1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
#ifdef DEBUG
@@ -194,23 +194,23 @@
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
@@ -228,8 +228,8 @@
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
- + CFG_PCI1_MEM_SIZE - 0x1000000)));
+ in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE
+ + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
} else {
puts("PCI-EXPRESS 1: Disabled\n");
@@ -241,30 +241,30 @@
#ifdef CONFIG_PCI2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
/* inbound */
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- CFG_PCI2_MEM_BASE,
- CFG_PCI2_MEM_PHYS,
- CFG_PCI2_MEM_SIZE,
+ CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_PHYS,
+ CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- CFG_PCI2_IO_BASE,
- CFG_PCI2_IO_PHYS,
- CFG_PCI2_IO_SIZE,
+ CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_PHYS,
+ CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;