rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
index 90e3637..a0904d4 100644
--- a/include/configs/EP1C20.h
+++ b/include/configs/EP1C20.h
@@ -30,29 +30,29 @@
#define CONFIG_EP1C20 1 /* EP1C20 board */
#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
-#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
-#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
+#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
+#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
* CACHE -- the following will support II/s and II/f. The II/s does not
* have dcache, so the cache instructions will behave as NOPs.
*----------------------------------------------------------------------*/
-#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */
-#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */
-#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
-#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
+#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
+#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
+#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
+#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
/*------------------------------------------------------------------------
* MEMORY BASE ADDRESSES
*----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */
-#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
-#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
-#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
-#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
+#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
+#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
+#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
+#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
+#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
+#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION
@@ -61,27 +61,27 @@
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */
-#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
-#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
+#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
/*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
- * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
* reset address, no? This will keep the environment in user region
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
@@ -89,30 +89,30 @@
#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
+#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
-#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
+#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
#endif
-#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
+#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
-#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
+#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
-#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
/*------------------------------------------------------------------------
- * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
* epcs device access is enabled. The base address is the epcs
* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
* The register base is currently at offset 0x600 from the memory base.
*----------------------------------------------------------------------*/
-#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
+#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
/*------------------------------------------------------------------------
* DEBUG
@@ -126,23 +126,23 @@
* registers, we can slow it down to 10 msec using TMRCNT. If the default
* period is acceptable, TMRCNT can be left undefined.
*----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
+#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
* must implement its own led routines -- leds are, after all,
* board-specific, no?
*----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
+#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
#define CONFIG_STATUS_LED /* Enable status driver */
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
#define STATUS_LED_STATE 1 /* Blinking */
-#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */
+#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
/*------------------------------------------------------------------------
* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
@@ -194,17 +194,17 @@
/*------------------------------------------------------------------------
* MISC
*----------------------------------------------------------------------*/
-#define CFG_LONGHELP /* Provide extended help*/
-#define CFG_PROMPT "==> " /* Command prompt */
-#define CFG_CBSIZE 256 /* Console I/O buf size */
-#define CFG_MAXARGS 16 /* Max command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
-#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
-#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
-#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
+#define CONFIG_SYS_LONGHELP /* Provide extended help*/
+#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS 16 /* Max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
+#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif /* __CONFIG_H */