rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 1627344..a399d22 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -64,7 +64,7 @@
/*
* Set allowable console baud rates
*/
-#define CFG_BAUDRATE_TABLE { 9600, \
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, \
19200, \
38400, \
57600, \
@@ -74,7 +74,7 @@
/*
* Print console information
*/
-#undef CFG_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
/*
* Set the autoboot delay in seconds. A delay of -1 disables autoboot
@@ -101,12 +101,12 @@
* for downloads
*/
#undef CONFIG_LOADS_ECHO
-#define CFG_LOADS_BAUD_CHANGE
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
/*
* Set default load address for tftp network downloads
*/
-#define CFG_TFTP_LOADADDR 0x01000000
+#define CONFIG_SYS_TFTP_LOADADDR 0x01000000
/*
* Turn off the watchdog timer
@@ -127,7 +127,7 @@
* Reset address. We pick an address such that when an instruction
* is executed at that address, a machine check exception occurs
*/
-#define CFG_RESET_ADDRESS ((ulong) -1)
+#define CONFIG_SYS_RESET_ADDRESS ((ulong) -1)
/*
* BOOTP options
@@ -145,7 +145,7 @@
* MII address is hardwired on the board to zero.
*/
#define CONFIG_FEC_ENET
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_MII
#define CONFIG_MII_INIT 1
#define CONFIG_PHY_ADDR 0
@@ -162,10 +162,10 @@
* This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
* the MPC860T I2C interface.
*/
-#define CFG_I2C_EEPROM_ADDR 0x50
-#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
-#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
#define CONFIG_ENV_EEPROM_SIZE (32 * 1024)
/*
@@ -175,8 +175,8 @@
#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
#ifdef CONFIG_HARD_I2C
-#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
-#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
+#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */
+#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */
#endif
#ifdef CONFIG_SOFT_I2C
@@ -208,7 +208,7 @@
* length of time, so we use an external RTC on the I2C bus instead.
*/
#define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#else
/*
@@ -220,11 +220,11 @@
/*
* Power On Self Test support
*/
-#define CONFIG_POST ( CFG_POST_CACHE | \
- CFG_POST_MEMORY | \
- CFG_POST_CPU | \
- CFG_POST_UART | \
- CFG_POST_SPR )
+#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_UART | \
+ CONFIG_SYS_POST_SPR )
/*
@@ -277,7 +277,7 @@
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_VIRTEX2
-#define CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_NAND_LEGACY
@@ -285,64 +285,64 @@
/*
* Verbose help from command monitor.
*/
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
#if !defined(CONFIG_SC)
-#define CFG_PROMPT "B2> "
+#define CONFIG_SYS_PROMPT "B2> "
#else
-#define CFG_PROMPT "SC> "
+#define CONFIG_SYS_PROMPT "SC> "
#endif
/*
* Use the "hush" command parser
*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Set buffer size for console I/O
*/
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024
+#define CONFIG_SYS_CBSIZE 1024
#else
-#define CFG_CBSIZE 256
+#define CONFIG_SYS_CBSIZE 256
#endif
/*
* Print buffer size
*/
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/*
* Maximum number of arguments that a command can accept
*/
-#define CFG_MAXARGS 16
+#define CONFIG_SYS_MAXARGS 16
/*
* Boot argument buffer size
*/
-#define CFG_BARGSIZE CFG_CBSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* Default memory test range
*/
-#define CFG_MEMTEST_START 0x0100000
-#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
+#define CONFIG_SYS_MEMTEST_START 0x0100000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (128 * 1024))
/*
* Select the more full-featured memory test
*/
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
/*
* Default load address
*/
-#define CFG_LOAD_ADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR 0x01000000
/*
* Set decrementer frequency (1 ms ticks)
*/
-#define CFG_HZ 1000
+#define CONFIG_SYS_HZ 1000
/*
* Device memory map (after SDRAM remap to 0x0):
@@ -363,7 +363,7 @@
/*
* Base addresses and block sizes
*/
-#define CFG_IMMR 0xFF000000
+#define CONFIG_SYS_IMMR 0xFF000000
#define SDRAM_BASE 0x00000000
#define SDRAM_SIZE (64 * 1024 * 1024)
@@ -386,27 +386,27 @@
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE SDRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE SDRAM_BASE
/*
* FLASH organization
*/
-#define CFG_FLASH_BASE FLASH_BASE
-#define CFG_FLASH_SIZE FLASH_SIZE
-#define CFG_FLASH_SECT_SIZE (128 * 1024)
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_MAX_FLASH_SECT 128
+#define CONFIG_SYS_FLASH_BASE FLASH_BASE
+#define CONFIG_SYS_FLASH_SIZE FLASH_SIZE
+#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
/*
* The timeout values are for an entire chip and are in milliseconds.
@@ -415,20 +415,20 @@
* case VCC and temp after 100K programming cycles. It works out
* to 280 minutes (might as well be forever).
*/
-#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
-#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
+#define CONFIG_SYS_FLASH_ERASE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 5000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
/*
* Allow direct writes to FLASH from tftp transfers (** dangerous **)
*/
-#define CFG_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
/*
* Reserve memory for U-Boot.
*/
-#define CFG_MAX_UBOOT_SECTS 4
-#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CONFIG_SYS_MAX_UBOOT_SECTS 4
+#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/*
* Select environment placement. NOTE that u-boot.lds must
@@ -442,7 +442,7 @@
#define CONFIG_ENV_OFFSET (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
#else
#define CONFIG_ENV_SIZE 0x1000
-#define CONFIG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
/*
* This ultimately gets passed right into the linker script, so we have to
@@ -454,21 +454,21 @@
/*
* Reserve memory for malloc()
*/
-#define CFG_MALLOC_LEN (128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/*
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
+#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of above value */
#endif
/*------------------------------------------------------------------------
@@ -479,7 +479,7 @@
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR ( SYPCR_SWTC | \
+#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \
SYPCR_BMT | \
SYPCR_BME | \
SYPCR_SWF | \
@@ -488,7 +488,7 @@
SYPCR_SWP \
)
#else
-#define CFG_SYPCR ( SYPCR_SWTC | \
+#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \
SYPCR_BMT | \
SYPCR_BME | \
SYPCR_SWF | \
@@ -501,7 +501,7 @@
*-----------------------------------------------------------------------
* Set debug pin mux, enable SPKROUT and GPLB5*.
*/
-#define CFG_SIUMCR ( SIUMCR_DBGC11 | \
+#define CONFIG_SYS_SIUMCR ( SIUMCR_DBGC11 | \
SIUMCR_DBPC11 | \
SIUMCR_MLRC11 | \
SIUMCR_GB5E \
@@ -512,7 +512,7 @@
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freeze enabled
*/
-#define CFG_TBSCR ( TBSCR_REFA | \
+#define CONFIG_SYS_TBSCR ( TBSCR_REFA | \
TBSCR_REFB | \
TBSCR_TBF \
)
@@ -521,7 +521,7 @@
* RTCSC - Real-Time Clock Status and Control Register UM 11-27
*-----------------------------------------------------------------------
*/
-#define CFG_RTCSC ( RTCSC_SEC | \
+#define CONFIG_SYS_RTCSC ( RTCSC_SEC | \
RTCSC_ALR | \
RTCSC_RTF | \
RTCSC_RTE \
@@ -532,7 +532,7 @@
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
-#define CFG_PISCR ( PISCR_PS | \
+#define CONFIG_SYS_PISCR ( PISCR_PS | \
PISCR_PITF \
)
@@ -542,7 +542,7 @@
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit. Set MF for 1:2:1 mode.
*/
-#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
+#define CONFIG_SYS_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
PLPRCR_SPLSS | \
PLPRCR_TEXPS | \
PLPRCR_TMIST \
@@ -557,7 +557,7 @@
#define SCCR_MASK SCCR_EBDF11
#if !defined(CONFIG_SC)
-#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
+#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
SCCR_COM00 | /* full strength CLKOUT */ \
SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
@@ -565,7 +565,7 @@
SCCR_DFNH000 \
)
#else
-#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
+#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
SCCR_COM00 | /* full strength CLKOUT */ \
SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
@@ -581,7 +581,7 @@
*-----------------------------------------------------------------------
* Mask all events that can cause entry into debug mode
*/
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
/*
* Initialize Memory Controller:
@@ -593,13 +593,13 @@
/*
* Flash address mask
*/
-#define CFG_PRELIM_OR_AM 0xfe000000
+#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
/*
* FLASH timing:
* 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
*/
-#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | \
OR_ACS_DIV2 | \
OR_BI | \
OR_SCY_2_CLK | \
@@ -607,11 +607,11 @@
OR_EHTR \
)
-#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \
- CFG_OR_TIMING_FLASH \
+#define CONFIG_SYS_OR0_PRELIM ( CONFIG_SYS_PRELIM_OR_AM | \
+ CONFIG_SYS_OR_TIMING_FLASH \
)
-#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
+#define CONFIG_SYS_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
BR_MS_GPCM | \
BR_PS_8 | \
BR_V \
@@ -620,12 +620,12 @@
/*
* SDRAM configuration
*/
-#define CFG_OR1_AM 0xfc000000
-#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \
+#define CONFIG_SYS_OR1_AM 0xfc000000
+#define CONFIG_SYS_OR1 ( (CONFIG_SYS_OR1_AM & OR_AM_MSK) | \
OR_CSNT_SAM \
)
-#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
BR_MS_UPMA | \
BR_PS_32 | \
BR_V \
@@ -635,17 +635,17 @@
* Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
* of 256 MBit SDRAM
*/
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
+#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
/*
* Periodic timer for refresh @ 33 MHz system clock
*/
-#define CFG_MAMR_PTA 64
+#define CONFIG_SYS_MAMR_PTA 64
/*
* MAMR settings for SDRAM
*/
-#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
+#define CONFIG_SYS_MAMR_8COL ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
MAMR_PTAE | \
MAMR_AMA_TYPE_1 | \
MAMR_DSA_1_CYCL | \
@@ -660,7 +660,7 @@
* 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
* no burst.
*/
-#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
+#define CONFIG_SYS_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_CSNT_SAM | \
OR_ACS_DIV2 | \
OR_BI | \
@@ -669,7 +669,7 @@
OR_EHTR \
)
-#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
BR_PS_8 | \
BR_MS_GPCM | \
BR_V \
@@ -683,12 +683,12 @@
* the cycle will still complete even if there is a configuration
* error that prevents TA from asserting on FPGA accesss.
*/
-#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
+#define CONFIG_SYS_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
OR_SCY_15_CLK | \
OR_BI \
)
-#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
BR_PS_32 | \
BR_MS_GPCM | \
BR_V \
@@ -698,12 +698,12 @@
* 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
* of GCLK1_50
*/
-#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
+#define CONFIG_SYS_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_G5LS | \
OR_BI \
)
-#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
BR_PS_8 | \
BR_MS_UPMB | \
BR_V \
@@ -717,7 +717,7 @@
* the cycle will still complete even if there is a configuration
* error that prevents TA from asserting on FPGA accesss.
*/
-#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
+#define CONFIG_SYS_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_SCY_15_CLK | \
OR_EHTR | \
OR_TRLX | \
@@ -725,7 +725,7 @@
OR_BI \
)
-#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
BR_PS_16 | \
BR_MS_GPCM | \
BR_V \
@@ -741,10 +741,10 @@
* Disk On Chip (millenium) configuration
*/
#if !defined(CONFIG_SC)
-#define CFG_MAX_DOC_DEVICE 1
-#undef CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#undef CFG_DOC_PASSIVE_PROBE
+#define CONFIG_SYS_MAX_DOC_DEVICE 1
+#undef CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+#undef CONFIG_SYS_DOC_PASSIVE_PROBE
#endif
/*