commit 6d0f6bcf337c5261c08fabe12982178c2c489d76
author Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Thu Oct 16 15:01:15 2008 +0200
committer Wolfgang Denk <wd@denx.de> Sat Oct 18 21:54:03 2008 +0200
tree ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f
parent 71edc271816ec82cf0550dd6980be2da3cc2ad9e

rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

post/board/lwmon5/fpga.c

diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c
index ef641d7..2b84290 100644
--- a/post/board/lwmon5/fpga.c
+++ b/post/board/lwmon5/fpga.c
@@ -39,7 +39,7 @@
 #define FPGA_RAM_END		0xC4203FFF
 #define FPGA_STAT		0xC400000C
 
-#if CONFIG_POST & CFG_POST_BSPEC3
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
 
 /* Testpattern for fpga memorytest */
 static uint pattern[] = {
@@ -127,7 +127,7 @@
 	/* Enable write to FPGA RAM */
 	out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
 
-	read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
+	read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000);
 	post_log("FPGA RAM size: %d bytes\n", read_value);
 
 	for (address = 0; address < 0x1000; address++) {
@@ -141,4 +141,4 @@
 	return ret;
 }
 
-#endif /* CONFIG_POST & CFG_POST_BSPEC3 */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC3 */