Fix a bug in the slave serial programming mode for the Xilinx
Spartan2/3 FPGAs. The old code used "< 0" on a "char" type to test if
the most significant bit was set, which did not work on any
architecture where "char" defaulted to be an unsigned type.
Based on a patch by Angelos Manousaridis <amanous@inaccessnetworks.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/common/spartan2.c b/common/spartan2.c
index 0fb23b6..06550b9 100644
--- a/common/spartan2.c
+++ b/common/spartan2.c
@@ -516,7 +516,7 @@
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
- (*fn->wr) ((val < 0), TRUE, cookie);
+ (*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);
diff --git a/common/spartan3.c b/common/spartan3.c
index c0f2b05..f7c4f8c 100644
--- a/common/spartan3.c
+++ b/common/spartan3.c
@@ -521,7 +521,7 @@
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
- (*fn->wr) ((val < 0), TRUE, cookie);
+ (*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);