| commit | 4ce1e23b5e12283579828b3d23e8fd6e1328a7aa | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Thu May 15 15:26:27 2008 -0500 |
| committer | Wolfgang Denk <wd@denx.de> | Mon May 19 23:04:24 2008 +0200 |
| tree | 4b05bf37a8b0993bdc0d4b2b87bd6b652978179e | |
| parent | 180a90abdae72587c0f679edf8991455e559440d [diff] |
Fix 8313ERDB board configuration Change LCRR clock ratio from 2 to 4 to commodate VSC7385. Correct TSEC1 vs TSEC2 assignment. Define ETHADDR and ETH1ADDR always. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com>