| commit | 8651593a8ce0c0599c993d76d2a927b125175cef | [log] [tgz] |
|---|---|---|
| author | Vignesh Raghavendra <vigneshr@ti.com> | Fri Oct 11 13:28:19 2019 +0530 |
| committer | Jagan Teki <jagan@amarulasolutions.com> | Fri Oct 25 00:48:32 2019 +0530 |
| tree | 44f33fa7505061b547d8ee317dd673b9ec691509 | |
| parent | d66e07cdf9ab6f84ce121009b08860261bca7df2 [diff] |
spi-nor: spi-nor-ids: Add entries for mt25q variants mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>