commit 743a77373bfa22ca099b30d4ac88d95a2f98d1b6
author David Wu <david.wu@rock-chips.com> Tue Apr 16 21:57:05 2019 +0800
committer Kever Yang <kever.yang@rock-chips.com> Wed May 08 17:34:12 2019 +0800
tree 18a6da958eeb1a7d8edcff07feb57fc29e568e93
parent 956362c84b0422ea99da947feca2878193c26ade

pinctrl: rockchip: Split the common set_pull() func into per Soc

As the common set_mux func(), implement the feature at the own file
for each Soc.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

drivers/pinctrl/rockchip/pinctrl-rk322x.c

diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
index 10200ff..b69d979 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
@@ -191,6 +191,33 @@
 	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 }
 
+static int rk3228_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3228_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3228_DRV_GRF_OFFSET		0x200
 
 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
@@ -247,7 +274,7 @@
 	.iomux_routes		= rk3228_mux_route_data,
 	.niomux_routes		= ARRAY_SIZE(rk3228_mux_route_data),
 	.set_mux		= rk3228_set_mux,
-	.pull_calc_reg		= rk3228_calc_pull_reg_and_bit,
+	.set_pull		= rk3228_set_pull,
 	.set_drive		= rk3228_set_drive,
 };