riscv: Add support for AMD/Xilinx MicroBlaze V
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
The patch contains initial wiring and configuration for initial HW design
with memory, cpu, interrupt controller, timers and uartlite console
(interrupt controller is listed but U-Boot is not using it).
Provided DT is just describing one configuration and should be taken only
as example.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 4f0776e..843198f 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -51,10 +51,11 @@
config BOOT_SCRIPT_OFFSET
hex "Boot script offset"
- depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV
default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
default 0x3E80000 if ARCH_ZYNQMP
default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0 if TARGET_XILINX_MBV
help
Specifies distro boot script offset in NAND/QSPI/NOR flash.