Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Clearfog: Add run-time board detection with TLV EEPROM support
(Baruch)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d2729d..9ececd4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -394,7 +394,7 @@
F: arch/arm/include/asm/arch-tegra*/
ARM TI
-M: Tom Rini <trini@konsulko.com>
+M: Lokesh Vutla <lokeshvutla@ti.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git
F: arch/arm/mach-davinci/
@@ -848,6 +848,8 @@
F: configs/k2l_hs_evm_defconfig
F: configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig
+F: configs/j721e_hs_evm_r5_defconfig
+F: configs/j721e_hs_evm_a72_defconfig
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 04a8ccc..44f7420 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -353,6 +353,7 @@
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am57xx-beagle-x15-revb1.dtb \
am57xx-beagle-x15-revc.dtb \
+ am5729-beagleboneai.dtb \
am574x-idk.dtb \
am572x-idk.dtb \
am571x-idk.dtb
@@ -676,6 +677,7 @@
imx6ull-colibri.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
+ imx6ull-somlabs-visionsom.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_ARCH_MX6) += \
@@ -862,7 +864,7 @@
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
-dtb-$(CONFIG_TARGET_STM32MP1) += \
+dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157c-dk2.dtb \
diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts
new file mode 100644
index 0000000..3429303
--- /dev/null
+++ b/arch/arm/dts/am5729-beagleboneai.dts
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+#include "dra74x.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/dra.h>
+
+/ {
+ model = "BeagleBoard.org BeagleBone AI";
+ compatible = "beagle,am5729-beagleboneai", "ti,am5728",
+ "ti,dra742", "ti,dra74", "ti,dra7";
+
+ aliases {
+ rtc0 = &tps659038_rtc;
+ rtc1 = &rtc;
+ display0 = &hdmi_conn;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ vdd_adc: gpioregulator-vdd_adc {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_adc";
+ vin-supply = <&vdd_5v>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0
+ 3300000 1>;
+ };
+
+ vdd_5v: fixedregulator-vdd_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vtt_fixed: fixedregulator-vtt {
+ /* TPS51200 */
+ compatible = "regulator-fixed";
+ regulator-name = "vtt_fixed";
+ vin-supply = <&vdd_ddr>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "beaglebone:green:usr0";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led1 {
+ label = "beaglebone:green:usr1";
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "beaglebone:green:usr4";
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ };
+
+ hdmi_conn: connector@0 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_encoder_out>;
+ };
+ };
+ };
+
+ hdmi_enc: encoder@0 {
+ /* "ti,tpd12s016" software compatible with "ti,tpd12s015"
+ * no need for individual driver
+ */
+ compatible = "ti,tpd12s015";
+ gpios = <0>,
+ <0>,
+ <&gpio7 12 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ hdmi_encoder_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ hdmi_encoder_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ };
+
+ brcmf_pwrseq: brcmf_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */
+ <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ ti,enable-id-detection;
+ id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ compatible = "ti,tps659038";
+ reg = <0x58>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+ ti,palmas-override-powerhold;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+
+ smps12-in-supply = <&vdd_5v>;
+ smps3-in-supply = <&vdd_5v>;
+ smps45-in-supply = <&vdd_5v>;
+ smps6-in-supply = <&vdd_5v>;
+ smps7-in-supply = <&vdd_5v>;
+ mps3-in-supply = <&vdd_5v>;
+ smps8-in-supply = <&vdd_5v>;
+ smps9-in-supply = <&vdd_5v>;
+ ldo1-in-supply = <&vdd_5v>;
+ ldo2-in-supply = <&vdd_5v>;
+ ldo3-in-supply = <&vdd_5v>;
+ ldo4-in-supply = <&vdd_5v>;
+ ldo9-in-supply = <&vdd_5v>;
+ ldoln-in-supply = <&vdd_5v>;
+ ldousb-in-supply = <&vdd_5v>;
+ ldortc-in-supply = <&vdd_5v>;
+
+ regulators {
+ vdd_mpu: smps12 {
+ /* VDD_MPU */
+ regulator-name = "smps12";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ddr: smps3 {
+ /* VDD_DDR EMIF1 EMIF2 */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_dspeve: smps45 {
+ /* VDD_DSPEVE on AM572 */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_gpu: smps6 {
+ /* VDD_GPU */
+ regulator-name = "smps6";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_core: smps7 {
+ /* VDD_CORE */
+ regulator-name = "smps7";
+ regulator-min-microvolt = < 850000>; /*** 1.15V */
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_iva: smps8 {
+ /* VDD_IVAHD */ /*** 1.06V */
+ regulator-name = "smps8";
+ };
+
+ vdd_3v3: smps9 {
+ /* VDD_3V3 */
+ regulator-name = "smps9";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_sd: ldo1 {
+ /* VDDSHV8 - VSDMMC */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_1v8: ldo2 {
+ /* VDDSH18V */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_phy_ldo3: ldo3 {
+ /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_phy_ldo4: ldo4 {
+ /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* LDO5-8 unused */
+
+ vdd_rtc: ldo9 {
+ /* VDD_RTC */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = < 840000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_pll: ldoln {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldortc_reg: ldortc {
+ /* VDDA_RTC */
+ regulator-name = "ldortc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ regen1: regen1 {
+ /* VDD_3V3_ON */
+ regulator-name = "regen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ regen2: regen2 {
+ /* Needed for PMIC internal resource */
+ regulator-name = "regen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659038_rtc: tps659038_rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&tps659038>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+
+ tps659038_pwr_button: tps659038_pwr_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps659038>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <12>;
+ };
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
+
+&mcspi3 {
+ status = "okay";
+ ti,pindir-d0-out-d1-in;
+
+ sn65hvs882: sn65hvs882@0 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+};
+
+&cpu0 {
+ vdd-supply = <&vdd_mpu>;
+ voltage-tolerance = <1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&davinci_mdio {
+ reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ reg = <4>;
+ eee-broken-100tx;
+ eee-broken-1000t;
+ };
+};
+
+&mac {
+ slaves = <1>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii";
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_sd>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vdd_1v8>;
+ vqmmc-supply = <&vdd_1v8>;
+ bus-width = <8>;
+ ti,non-removable;
+ non-removable;
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ ti,needs-special-reset;
+ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
+ dma-names = "tx", "rx";
+
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+ pinctrl-3 = <&mmc2_pins_hs200>;
+
+};
+
+&mmc4 {
+ /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
+ /* HS: High speed up to 50 MHz (3.3 V signaling). */
+ /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
+ /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
+ /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
+ /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
+ /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
+ status = "okay";
+
+ ti,needs-special-reset;
+ vmmc-supply = <&vdd_3v3>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ ti,non-removable;
+ non-removable;
+ no-1-8-v;
+ max-frequency = <24000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmc-pwrseq = <&brcmf_pwrseq>;
+
+ brcmf: wifi@1 {
+ status = "okay";
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+
+ brcm,sd-head-align = <4>;
+ brcm,sd_head_align = <4>;
+ brcm,sd_sgentry_align = <512>;
+
+ interrupt-parent = <&gpio3>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&usb2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&dss {
+ status = "okay";
+ vdda_video-supply = <&vdd_1v8_pll>;
+};
+
+&hdmi {
+ status = "okay";
+ vdda-supply = <&vdd_1v8_phy_ldo4>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_encoder_in>;
+ };
+ };
+};
+
+&bandgap {
+ status = "okay";
+};
+
+&cpu_alert0 {
+ temperature = <55000>; /* milliCelsius */
+};
+
+&cpu_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&gpu_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&core_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&iva_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&sata {
+ status = "disabled";
+};
+
+&sata_phy {
+ status = "disabled";
+};
+
+/* bluetooth */
+&uart6 {
+ status = "okay";
+};
+
+/* cape header stuff */
+&i2c4 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi
index 541f4ca..b372d06 100644
--- a/arch/arm/dts/da850-lcdk-u-boot.dtsi
+++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi
@@ -8,9 +8,23 @@
/ {
aliases {
i2c0 = &i2c0;
+ mmc0 = &mmc0;
+ serial2 = &serial2;
+ };
+
+ soc@1c00000 {
+ u-boot,dm-spl;
};
nand {
compatible = "ti,davinci-nand";
};
};
+
+&mmc0 {
+ u-boot,dm-spl;
+};
+
+&serial2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts
index 0177e3e..db8ae56 100644
--- a/arch/arm/dts/da850-lcdk.dts
+++ b/arch/arm/dts/da850-lcdk.dts
@@ -18,7 +18,7 @@
};
chosen {
- stdout-path = "serial2:115200n8";
+ stdout-path = &serial2;
};
memory@c0000000 {
diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi
index 28bc32c..9af8b15 100644
--- a/arch/arm/dts/fsl-imx8-ca35.dtsi
+++ b/arch/arm/dts/fsl-imx8-ca35.dtsi
@@ -18,6 +18,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_1: cpu@1 {
@@ -26,6 +27,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_2: cpu@2 {
@@ -34,6 +36,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_3: cpu@3 {
@@ -42,6 +45,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_L2: l2-cache0 {
diff --git a/arch/arm/dts/imx6ull-somlabs-visionsom.dts b/arch/arm/dts/imx6ull-somlabs-visionsom.dts
new file mode 100644
index 0000000..868f3f8
--- /dev/null
+++ b/arch/arm/dts/imx6ull-somlabs-visionsom.dts
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2019 SoMLabs
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+ model = "SoMLabs VisionSOM-6ULL";
+ compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ usr0 {
+ label = "usr0";
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ usr1 {
+ label = "usr1";
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ usr2 {
+ label = "usr2";
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ };
+
+ usr3 {
+ label = "usr3";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg2_vbus: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ };
+};
+
+&cpu0 {
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <786432000>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+
+};
+
+&gpc {
+ fsl,cpu_pupscr_sw2iso = <0x1>;
+ fsl,cpu_pupscr_sw = <0x0>;
+ fsl,cpu_pdnscr_iso2sw = <0x1>;
+ fsl,cpu_pdnscr_iso = <0x1>;
+ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_1>;
+
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ /* 32kHz low power reference clock for WiFi */
+ MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099
+ /* LED 0..3 */
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099
+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829
+
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0
+ >;
+ };
+
+ pinctrl_usb_otg2: usbotg2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0
+ >;
+ };
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xfff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ tx-d-cal = <0x5>;
+};
+
+&usbphy2 {
+ tx-d-cal = <0x5>;
+};
+
+&usdhc2 {
+ non-removable;
+ disable-wp;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,wdog_b;
+};
diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts
index 08a682f..8f6a935 100644
--- a/arch/arm/dts/imx7ulp-evk.dts
+++ b/arch/arm/dts/imx7ulp-evk.dts
@@ -156,7 +156,7 @@
pinctrl_backlight: backlight_grp {
fsl,pins = <
- IMX7ULP_PAD_PTF2__PTF2 0x20100
+ IMX7ULP_PAD_PTF2__PTF2 0x20000
>;
};
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 0f5da9a..ab40daf 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -251,4 +251,82 @@
interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
};
};
+
+ dwc3_0: dwc3@4000000 {
+ compatible = "ti,am654-dwc3";
+ reg = <0x0 0x4000000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x4000000 0x20000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
+
+ usb0: usb@10000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ phys = <&usb0_phy>;
+ phy-names = "usb2-phy";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ usb0_phy: phy@4100000 {
+ compatible = "ti,am654-usb2", "ti,omap-usb2";
+ reg = <0x0 0x4100000 0x0 0x54>;
+ syscon-phy-power = <&scm_conf 0x4000>;
+ clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
+ clock-names = "wkupclk", "refclk";
+ #phy-cells = <0>;
+ ti,dis-chg-det-quirk;
+ };
+
+ dwc3_1: dwc3@4020000 {
+ compatible = "ti,am654-dwc3";
+ reg = <0x0 0x4020000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x4020000 0x20000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 152 2>;
+ assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+
+ usb1: usb@10000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ phys = <&usb1_phy>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ usb1_phy: phy@4110000 {
+ compatible = "ti,am654-usb2", "ti,omap-usb2";
+ reg = <0x0 0x4110000 0x0 0x54>;
+ syscon-phy-power = <&scm_conf 0x4020>;
+ clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
+ clock-names = "wkupclk", "refclk";
+ #phy-cells = <0>;
+ ti,dis-chg-det-quirk;
+ };
};
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index bea80c5..a349edc 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -25,7 +25,8 @@
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4FA0000 0x0 0x1000>,
<0x0 0x4FB0000 0x0 0x400>;
- clocks = <&k3_clks 48 1>;
+ clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
+ clock-names = "clk_ahb", "clk_xin";
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
max-frequency = <25000000>;
ti,otap-del-sel = <0x2>;
@@ -360,3 +361,7 @@
&wkup_i2c0 {
u-boot,dm-spl;
};
+
+&usb1 {
+ dr_mode = "peripheral";
+};
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts
index 573ead0..7ebbf17 100644
--- a/arch/arm/dts/k3-am654-base-board.dts
+++ b/arch/arm/dts/k3-am654-base-board.dts
@@ -58,6 +58,12 @@
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
};
+
+ usb1_pins_default: usb1_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -89,3 +95,25 @@
#gpio-cells = <2>;
};
};
+
+&dwc3_1 {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_default>;
+ dr_mode = "otg";
+};
+
+&dwc3_0 {
+ status = "disabled";
+};
+
+&usb0_phy {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 5c110ef..5d5689d 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -100,7 +100,7 @@
wkup_vtm0: wkup_vtm@42050000 {
compatible = "ti,am654-vtm", "ti,am654-avs";
reg = <0x42050000 0x25c>;
- power-domains = <&k3_pds 80>;
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 9291e57..7ea4d8d 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -282,6 +282,20 @@
u-boot,dm-spl;
};
+&main_usbss0_pins_default {
+ u-boot,dm-spl;
+};
+
+&usbss0 {
+ u-boot,dm-spl;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ u-boot,dm-spl;
+};
+
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
@@ -311,3 +325,15 @@
reg-names = "gmii-sel";
};
};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_i2c0_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index c978cab..f33a6d5 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -65,15 +65,83 @@
status = "disabled";
};
+&main_pmx0 {
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
+ >;
+ };
+};
+
&main_sdhci0 {
/* eMMC */
- voltage-ranges = <1800 1800>;
non-removable;
ti,driver-strength-ohm = <50>;
};
&main_sdhci1 {
- /* SD/MMC */
- voltage-ranges = <1800 1800 3300 3300>;
+ /* SD card */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
};
+
+&main_pmx0 {
+ main_usbss0_pins_default: main_usbss0_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+ >;
+ };
+
+ main_usbss1_pins_default: main_usbss1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>;
+ ti,usb2-only;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};
+
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 3a07632..5083a0c 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -340,6 +340,76 @@
resets = <&k3_reset 15 1>;
};
+ usbss0: cdns_usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x4104000 0x00 0x100>;
+ dma-coherent;
+ power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
+ clock-names = "usb2_refclk", "lpm_clk";
+ assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ phy@4108000 {
+ compatible = "ti,j721e-usb2-phy";
+ reg = <0x00 0x4108000 0x00 0x400>;
+ };
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x6000000 0x00 0x10000>,
+ <0x00 0x6010000 0x00 0x10000>,
+ <0x00 0x6020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ usbss1: cdns_usb@4114000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x4114000 0x00 0x100>;
+ dma-coherent;
+ power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
+ clock-names = "usb2_refclk", "lpm_clk";
+ assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ phy@4118000 {
+ compatible = "ti,j721e-usb2-phy";
+ reg = <0x00 0x4118000 0x00 0x400>;
+ };
+
+ usb1: usb@6400000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x6400000 0x00 0x10000>,
+ <0x00 0x6410000 0x00 0x10000>,
+ <0x00 0x6420000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
ufs_wrapper: ufs-wrapper@4e80000 {
compatible = "ti,j721e-ufs";
reg = <0x0 0x4e80000 0x0 0x100>;
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 41af482..28a355d 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -112,6 +112,27 @@
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
+
+ main_usbss0_pins_default: main_usbss0_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+ >;
+ };
+
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
+ >;
+ };
};
&wkup_uart0 {
@@ -149,6 +170,8 @@
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi
index 1abd9a3..173b492 100644
--- a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi
@@ -17,16 +17,44 @@
};
};
+&gpio1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio2 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio3 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio4 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio5 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio6 {
+ /delete-property/ u-boot,dm-spl;
+};
+
&i2c1 {
clock-frequency = <400000>;
+ /delete-property/ u-boot,dm-spl;
};
&i2c2 {
clock-frequency = <400000>;
+ /delete-property/ u-boot,dm-spl;
};
+/delete-node/ &bandgap;
/delete-node/ &uart2;
/delete-node/ &uart3;
/delete-node/ &mmc2;
/delete-node/ &mmc3;
+/delete-node/ &thermal_zones;
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
index e5d9e4f..173b492 100644
--- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
@@ -29,6 +29,10 @@
/delete-property/ u-boot,dm-spl;
};
+&gpio4 {
+ /delete-property/ u-boot,dm-spl;
+};
+
&gpio5 {
/delete-property/ u-boot,dm-spl;
};
@@ -39,14 +43,18 @@
&i2c1 {
clock-frequency = <400000>;
+ /delete-property/ u-boot,dm-spl;
};
&i2c2 {
clock-frequency = <400000>;
+ /delete-property/ u-boot,dm-spl;
};
+/delete-node/ &bandgap;
/delete-node/ &uart2;
/delete-node/ &uart3;
/delete-node/ &mmc2;
/delete-node/ &mmc3;
+/delete-node/ &thermal_zones;
diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi
index 1635e42..581247d 100644
--- a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi
@@ -7,21 +7,53 @@
#include "omap3-u-boot.dtsi"
/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
aliases {
/delete-property/ serial1;
/delete-property/ serial2;
};
};
+&gpio1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio2 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio3 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio4 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio5 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio6 {
+ /delete-property/ u-boot,dm-spl;
+};
+
&i2c1 {
clock-frequency = <400000>;
+ /delete-property/ u-boot,dm-spl;
};
&i2c2 {
clock-frequency = <400000>;
+ /delete-property/ u-boot,dm-spl;
};
+/delete-node/ &bandgap;
/delete-node/ &uart2;
/delete-node/ &uart3;
/delete-node/ &mmc2;
/delete-node/ &mmc3;
+/delete-node/ &thermal_zones;
diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
index 76f7432..9b709c1 100644
--- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
@@ -15,6 +15,7 @@
&i2c1 {
clock-frequency = <400000>;
+ /delete-property/ u-boot,dm-spl;
};
&i2c2 {
@@ -33,6 +34,10 @@
/delete-property/ u-boot,dm-spl;
};
+&gpio4 {
+ /delete-property/ u-boot,dm-spl;
+};
+
&gpio5 {
/delete-property/ u-boot,dm-spl;
};
@@ -41,8 +46,9 @@
/delete-property/ u-boot,dm-spl;
};
+/delete-node/ &bandgap;
/delete-node/ &uart2;
/delete-node/ &uart3;
/delete-node/ &mmc2;
/delete-node/ &mmc3;
-
+/delete-node/ &thermal_zones;
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 6c670cf..41aea75 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -1404,11 +1404,13 @@
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
+ "eth-ck",
"ethstp",
"syscfg-clk";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
+ <&rcc ETHCK_K>,
<&rcc ETHSTP>,
<&rcc SYSCFG>;
st,syscon = <&syscfg 0x4>;
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index 3c82e99..9a420dc 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -946,6 +946,10 @@
#define SNVS_LPCR_DPEN (0x20)
#define SNVS_LPCR_SRTC_ENV (0x1)
+#define SRC_BASE_ADDR CMC1_RBASE
+#define IRAM_BASE_ADDR OCRAM_0_BASE
+#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index ca4b4c0..c423ac0 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -47,7 +47,7 @@
PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
};
-int fracpll_configure(enum pll_clocks pll, u32 freq)
+static int fracpll_configure(enum pll_clocks pll, u32 freq)
{
int i;
u32 tmp, div_val;
@@ -268,7 +268,7 @@
return 24000000U;
}
-u32 decode_intpll(enum clk_root_src intpll)
+static u32 decode_intpll(enum clk_root_src intpll)
{
u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
u32 main_div, pre_div, post_div, div;
@@ -415,7 +415,7 @@
return lldiv(freq, pre_div * (1 << post_div) * div);
}
-u32 decode_fracpll(enum clk_root_src frac_pll)
+static u32 decode_fracpll(enum clk_root_src frac_pll)
{
u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
u32 main_div, pre_div, post_div, k;
@@ -480,7 +480,7 @@
65536 * pre_div * (1 << post_div));
}
-u32 get_root_src_clk(enum clk_root_src root_src)
+static u32 get_root_src_clk(enum clk_root_src root_src)
{
switch (root_src) {
case OSC_24M_CLK:
@@ -524,7 +524,7 @@
return 0;
}
-u32 get_root_clk(enum clk_root_index clock_id)
+static u32 get_root_clk(enum clk_root_index clock_id)
{
enum clk_root_src root_src;
u32 post_podf, pre_podf, root_src_clk;
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index f1a1021..9d91f9a 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -540,6 +540,18 @@
bool "sks-imx6"
select SUPPORT_SPL
+config TARGET_SOMLABS_VISIONSOM_6ULL
+ bool "visionsom-6ull"
+ select MX6ULL
+ select BOARD_LATE_INIT
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_MMC
+ select DM_SERIAL
+ select DM_THERMAL
+ imply CMD_DM
+
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
@@ -694,6 +706,7 @@
source "board/seco/Kconfig"
source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/somlabs/visionsom-6ull/Kconfig"
source "board/technexion/pico-imx6/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 7f8fdc7..4648481 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -118,6 +118,7 @@
disable_wdog(WDG2_RBASE);
}
+#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
#if defined(CONFIG_LDO_ENABLED_MODE)
static void init_ldo_mode(void)
{
@@ -175,6 +176,7 @@
#endif
return;
}
+#endif
#ifndef CONFIG_ULP_WATCHDOG
void reset_cpu(ulong addr)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 5583241..2e111bb 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -119,7 +119,7 @@
config K3_SYSFW_IMAGE_SIZE_MAX
int "Amount of memory dynamically allocated for loading SYSFW blob"
depends on K3_LOAD_SYSFW
- default 276000
+ default 277000
help
Amount of memory (in bytes) reserved through dynamic allocation at
runtime for loading the combined System Firmware and configuration image
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index a78ffbb..8d107b8 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * K3: Architecture initialization
+ * AM6: SoC specific initialization
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
@@ -19,6 +19,26 @@
#include <linux/soc/ti/ti_sci_protocol.h>
#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_K3_LOAD_SYSFW
+#ifdef CONFIG_TI_SECURE_DEVICE
+struct fwl_data main_cbass_fwls[] = {
+ { "MMCSD1_CFG", 2057, 1 },
+ { "MMCSD0_CFG", 2058, 1 },
+ { "USB3SS0_SLV0", 2176, 2 },
+ { "PCIE0_SLV", 2336, 8 },
+ { "PCIE1_SLV", 2337, 8 },
+ { "PCIE0_CFG", 2688, 1 },
+ { "PCIE1_CFG", 2689, 1 },
+}, mcu_cbass_fwls[] = {
+ { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
+ { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
+ { "MCU_FSS0_S1", 1033, 8 },
+ { "MCU_FSS0_S0", 1036, 8 },
+ { "MCU_CPSW0", 1220, 1 },
+};
+#endif
+#endif
+
static void mmr_unlock(u32 base, u32 partition)
{
/* Translate the base address */
@@ -109,6 +129,12 @@
* output.
*/
k3_sysfw_loader(preloader_console_init);
+
+ /* Disable ROM configured firewalls right after loading sysfw */
+#ifdef CONFIG_TI_SECURE_DEVICE
+ remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
+ remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
+#endif
#else
/* Prepare console output */
preloader_console_init();
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 4e35a13..2f82edb 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -175,8 +175,8 @@
offs = fdt_path_offset(blob, node_path);
if (offs < 0) {
- debug("Node %s not found.\n", node_path);
- return 0;
+ printf("Node %s not found.\n", node_path);
+ return offs;
}
ret = fdt_setprop_string(blob, offs, "status", "disabled");
if (ret < 0) {
@@ -270,3 +270,33 @@
asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
}
#endif
+
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+{
+ struct ti_sci_msg_fwl_region region;
+ struct ti_sci_fwl_ops *fwl_ops;
+ struct ti_sci_handle *ti_sci;
+ size_t i, j;
+
+ ti_sci = get_ti_sci_handle();
+ fwl_ops = &ti_sci->ops.fwl_ops;
+ for (i = 0; i < fwl_data_size; i++) {
+ for (j = 0; j < fwl_data[i].regions; j++) {
+ region.fwl_id = fwl_data[i].fwl_id;
+ region.region = j;
+ region.n_permission_regs = 3;
+
+ fwl_ops->get_fwl_region(ti_sci, ®ion);
+
+ if (region.control != 0) {
+ pr_debug("Attempting to disable firewall %5d (%25s)\n",
+ region.fwl_id, fwl_data[i].name);
+ region.control = 0;
+
+ if (fwl_ops->set_fwl_region(ti_sci, ®ion))
+ pr_err("Could not disable firewall %5d (%25s)\n",
+ region.fwl_id, fwl_data[i].name);
+ }
+ }
+ }
+}
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 35d1609..d8b34fe 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -14,6 +14,13 @@
#define REV_PG1_0 0
#define REV_PG2_0 1
+struct fwl_data {
+ const char *name;
+ u16 fwl_id;
+ u16 regions;
+};
+
void setup_k3_mpu_regions(void);
int early_console_init(void);
void disable_linefill_optimization(void);
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
index 8d42977..ead136e 100644
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -46,4 +46,7 @@
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
#endif /* __ASM_ARCH_J721E_HARDWARE_H */
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 4758739..f7f7398 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -20,6 +20,47 @@
#include <dm/pinctrl.h>
#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_K3_LOAD_SYSFW
+#ifdef CONFIG_TI_SECURE_DEVICE
+struct fwl_data cbass_hc_cfg0_fwls[] = {
+ { "PCIE0_CFG", 2560, 8 },
+ { "PCIE1_CFG", 2561, 8 },
+ { "USB3SS0_CORE", 2568, 4 },
+ { "USB3SS1_CORE", 2570, 4 },
+ { "EMMC8SS0_CFG", 2576, 4 },
+ { "UFS_HCI0_CFG", 2580, 4 },
+ { "SERDES0", 2584, 1 },
+ { "SERDES1", 2585, 1 },
+}, cbass_hc0_fwls[] = {
+ { "PCIE0_HP", 2528, 24 },
+ { "PCIE0_LP", 2529, 24 },
+ { "PCIE1_HP", 2530, 24 },
+ { "PCIE1_LP", 2531, 24 },
+}, cbass_rc_cfg0_fwls[] = {
+ { "EMMCSD4SS0_CFG", 2380, 4 },
+}, cbass_rc0_fwls[] = {
+ { "GPMC0", 2310, 8 },
+}, infra_cbass0_fwls[] = {
+ { "PLL_MMR0", 8, 26 },
+ { "CTRL_MMR0", 9, 16 },
+}, mcu_cbass0_fwls[] = {
+ { "MCU_R5FSS0_CORE0", 1024, 4 },
+ { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
+ { "MCU_R5FSS0_CORE1", 1028, 4 },
+ { "MCU_FSS0_CFG", 1032, 12 },
+ { "MCU_FSS0_S1", 1033, 8 },
+ { "MCU_FSS0_S0", 1036, 8 },
+ { "MCU_PSROM49152X32", 1048, 1 },
+ { "MCU_MSRAM128KX64", 1050, 8 },
+ { "MCU_CTRL_MMR0", 1200, 8 },
+ { "MCU_PLL_MMR0", 1201, 3 },
+ { "MCU_CPSW0", 1220, 2 },
+}, wkup_cbass0_fwls[] = {
+ { "WKUP_CTRL_MMR0", 131, 16 },
+};
+#endif
+#endif
+
static void mmr_unlock(u32 base, u32 partition)
{
/* Translate the base address */
@@ -114,11 +155,25 @@
* output.
*/
k3_sysfw_loader(preloader_console_init);
+
+ /* Disable ROM configured firewalls right after loading sysfw */
+#ifdef CONFIG_TI_SECURE_DEVICE
+ remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
+ remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
+ remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
+ remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
+ remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
+ remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
+ remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
+#endif
#else
/* Prepare console output */
preloader_console_init();
#endif
+ /* Perform EEPROM-based board detection */
+ do_board_detect();
+
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
&dev);
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 6934e88..0d77d98 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
#include <linux/soc/ti/ti_sci_protocol.h>
@@ -23,8 +24,14 @@
int ret;
image_addr = (uintptr_t)*p_image;
+ image_size = *p_size;
debug("Authenticating image at address 0x%016llx\n", image_addr);
+ debug("Authenticating image of size %d bytes\n", image_size);
+
+ flush_dcache_range((unsigned long)image_addr,
+ ALIGN((unsigned long)image_addr + image_size,
+ ARCH_DMA_MINALIGN));
/* Authenticate image */
ret = proc_ops->proc_auth_boot_image(ti_sci, &image_addr, &image_size);
@@ -33,6 +40,11 @@
hang();
}
+ if (image_size)
+ invalidate_dcache_range((unsigned long)image_addr,
+ ALIGN((unsigned long)image_addr +
+ image_size, ARCH_DMA_MINALIGN));
+
/*
* The image_size returned may be 0 when the authentication process has
* moved the image. When this happens no further processing on the
diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index 32cdf63..f2cd496 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -77,7 +77,7 @@
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
{30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */
- {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
+ {100, 2, 1, -1, -1, -1, -1}, /* OPP TB */
{125, 2, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 25 MHz */
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index c4a41db..fa4e270 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -418,6 +418,7 @@
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_l4per_uart1_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index ae28f6e..137178a 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -33,8 +33,8 @@
config ENV_SIZE
default 0x2000
-config TARGET_STM32MP1
- bool "Support stm32mp1xx"
+config STM32MP15x
+ bool "Support STMicroelectronics STM32MP15x Soc"
select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
select CPU_V7A
select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
@@ -45,19 +45,35 @@
select STM32_RESET
select STM32_SERIAL
select SYS_ARCH_TIMER
+ imply SYSRESET_PSCI if STM32MP1_TRUSTED
+ imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
+ help
+ support of STMicroelectronics SOC STM32MP15x family
+ STM32MP157, STM32MP153 or STM32MP151
+ STMicroelectronics MPU with core ARMv7
+ dual core A7 for STM32MP157/3, monocore for STM32MP151
+ target all the STMicroelectronics board with SOC STM32MP1 family
+
+choice
+ prompt "STM32MP15x board select"
+ optional
+
+config TARGET_ST_STM32MP15x
+ bool "STMicroelectronics STM32MP15x boards"
+ select STM32MP15x
imply BOOTCOUNT_LIMIT
imply CMD_BOOTCOUNT
imply CMD_CLS if CMD_BMP
imply DISABLE_CONSOLE
imply PRE_CONSOLE_BUFFER
imply SILENT_CONSOLE
- imply SYSRESET_PSCI if STM32MP1_TRUSTED
- imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
help
- target STMicroelectronics SOC STM32MP1 family
- STM32MP157, STM32MP153 or STM32MP151
- STMicroelectronics MPU with core ARMv7
- dual core A7 for STM32MP157/3, monocore for STM32MP151
+ target the STMicroelectronics board with SOC STM32MP15x
+ managed by board/st/stm32mp1:
+ Evalulation board (EV1) or Discovery board (DK1 and DK2).
+ The difference between board are managed with devicetree
+
+endchoice
config STM32MP1_TRUSTED
bool "Support trusted boot with TF-A"
@@ -80,12 +96,7 @@
OP-TEE monitor provides ST SMC to access to secure resources
config SYS_TEXT_BASE
- prompt "U-Boot base address"
default 0xC0100000
- help
- configure the U-Boot base address
- when DDR driver is used:
- DDR + 1MB (0xC0100000)
config NR_DRAM_BANKS
default 1
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 6a71465..de7891b 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -456,7 +456,7 @@
* If there is no MAC address in the environment, then it will be initialized
* (silently) from the value in the OTP.
*/
-static int setup_mac_address(void)
+__weak int setup_mac_address(void)
{
#if defined(CONFIG_NET)
int ret;
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 99eefab..47e5792 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -30,3 +30,5 @@
/* return boot mode */
u32 get_bootmode(void);
+
+int setup_mac_address(void);
diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
index 5017ab8..bb79130 100644
--- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
+++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
@@ -108,11 +108,6 @@
return 0;
}
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
-}
-
/*
* Board specific reset that is system reset.
*/
diff --git a/board/freescale/imx8mm_evk/README b/board/freescale/imx8mm_evk/README
index c908c0a..9921b35 100644
--- a/board/freescale/imx8mm_evk/README
+++ b/board/freescale/imx8mm_evk/README
@@ -15,12 +15,12 @@
$ make PLAT=imx8mm bl31
$ cp build/imx8mm/release/bl31.bin $(builddir)
-Get the ddr and hdmi firmware
+Get the ddr firmware
=============================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
$ chmod +x firmware-imx-8.0.bin
$ ./firmware-imx-8.0
-$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+$ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
Build U-Boot
============
diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
index a0af550..c5fd940 100644
--- a/board/freescale/imx8mm_evk/imx8mm_evk.c
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -8,6 +8,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index a26fc96..5d17f39 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -39,7 +39,7 @@
}
}
-void spl_dram_init(void)
+static void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
@@ -84,7 +84,7 @@
return 0;
}
-int power_init_board(void)
+static int power_init_board(void)
{
struct udevice *dev;
int ret;
diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c
index bf296a6..c9b9b25 100644
--- a/board/freescale/imx8qm_mek/imx8qm_mek.c
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -9,6 +9,7 @@
#include <errno.h>
#include <init.h>
#include <linux/libfdt.h>
+#include <fdt_support.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
@@ -100,11 +101,6 @@
return 0;
}
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
-}
-
/*
* Board specific reset that is system reset.
*/
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index 1577cd6..b96f0da 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -10,6 +10,7 @@
#include <init.h>
#include <linux/libfdt.h>
#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
@@ -113,11 +114,6 @@
return 0;
}
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
-}
-
/*
* Board specific reset that is system reset.
*/
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 835eed3..41c6207 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -264,7 +264,7 @@
struct udevice *dev;
int ret, dev_id, rev_id;
- ret = pmic_get("pfuze3000@08", &dev);
+ ret = pmic_get("pfuze3000@8", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index ef914b1..c74c06e 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -146,7 +146,7 @@
return NULL;
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
@@ -427,8 +427,6 @@
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
-
static iomux_v3_cfg_t const pcie_pads[] = {
MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};
@@ -461,30 +459,13 @@
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
+
int board_mmc_init(bd_t *bis)
{
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- u32 val;
- u32 port;
+ imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- val = readl(&src_regs->sbmr1);
-
- if ((val & 0xc0) != 0x40) {
- printf("Not boot from USDHC!\n");
- return -EINVAL;
- }
-
- port = (val >> 11) & 0x3;
- printf("port %d\n", port);
- switch (port) {
- case 3:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
- break;
- }
-
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg);
}
diff --git a/board/somlabs/visionsom-6ull/Kconfig b/board/somlabs/visionsom-6ull/Kconfig
new file mode 100644
index 0000000..37408aa
--- /dev/null
+++ b/board/somlabs/visionsom-6ull/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SOMLABS_VISIONSOM_6ULL
+
+config SYS_BOARD
+ default "visionsom-6ull"
+
+config SYS_VENDOR
+ default "somlabs"
+
+config SYS_CONFIG_NAME
+ default "somlabs_visionsom_6ull"
+
+endif
diff --git a/board/somlabs/visionsom-6ull/MAINTAINERS b/board/somlabs/visionsom-6ull/MAINTAINERS
new file mode 100644
index 0000000..905c000
--- /dev/null
+++ b/board/somlabs/visionsom-6ull/MAINTAINERS
@@ -0,0 +1,6 @@
+VISIONSOM-6ULL BOARD
+M: Arkadiusz Karas <arkadiusz.karas@somlabs.com>
+S: Maintained
+F: board/somlabs/visionsom-6ull/
+F: include/configs/somlabs_visionsom_6ull.h
+F: configs/somlabs_visionsom_6ull_defconfig
diff --git a/board/somlabs/visionsom-6ull/Makefile b/board/somlabs/visionsom-6ull/Makefile
new file mode 100644
index 0000000..9c3768a
--- /dev/null
+++ b/board/somlabs/visionsom-6ull/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2019 Arkadiusz Karas <arkadiusz.karas@somlabs.com>
+
+obj-y := visionsom-6ull.o
diff --git a/board/somlabs/visionsom-6ull/imximage.cfg b/board/somlabs/visionsom-6ull/imximage.cfg
new file mode 100644
index 0000000..b49a2df
--- /dev/null
+++ b/board/somlabs/visionsom-6ull/imximage.cfg
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 A. Karas
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Micron MT41K256M16TW-107 */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000000
+DATA 4 0x021B083C 0x41570155
+DATA 4 0x021B0848 0x4040474A
+DATA 4 0x021B0850 0x40405550
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x23400A38
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
diff --git a/board/somlabs/visionsom-6ull/visionsom-6ull.c b/board/somlabs/visionsom-6ull/visionsom-6ull.c
new file mode 100644
index 0000000..bc7257b
--- /dev/null
+++ b/board/somlabs/visionsom-6ull/visionsom-6ull.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2019 A. Karas, SomLabs
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ enable_enet_clk(1);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+ return devno;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ if (is_cpu_type(MXC_CPU_MX6ULL))
+ env_set("board", "visionsom-6ull");
+ else
+ env_set("board", "visionsom-6ul");
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: SoMLabs VisionSOM-6UL%s\n",
+ is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
+
+ return 0;
+}
diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig
new file mode 100644
index 0000000..af01ca4
--- /dev/null
+++ b/board/st/common/Kconfig
@@ -0,0 +1,7 @@
+config CMD_STBOARD
+ bool "stboard - command for OTP board information"
+ depends on ARCH_STM32MP
+ default y if TARGET_ST_STM32MP15x
+ help
+ This compile the stboard command to
+ read and write the board in the OTP.
diff --git a/board/st/common/MAINTAINERS b/board/st/common/MAINTAINERS
new file mode 100644
index 0000000..3b02f4a
--- /dev/null
+++ b/board/st/common/MAINTAINERS
@@ -0,0 +1,6 @@
+ST BOARDS
+M: Patrick Delaunay <patrick.delaunay@st.com>
+L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
+S: Maintained
+F: board/st/common/
diff --git a/board/st/common/Makefile b/board/st/common/Makefile
new file mode 100644
index 0000000..8553606
--- /dev/null
+++ b/board/st/common/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+#
+
+obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
diff --git a/board/st/stm32mp1/cmd_stboard.c b/board/st/common/cmd_stboard.c
similarity index 98%
rename from board/st/stm32mp1/cmd_stboard.c
rename to board/st/common/cmd_stboard.c
index 04352ae..e994a88 100644
--- a/board/st/stm32mp1/cmd_stboard.c
+++ b/board/st/common/cmd_stboard.c
@@ -3,6 +3,7 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+#ifndef CONFIG_SPL_BUILD
#include <common.h>
#include <console.h>
#include <misc.h>
@@ -143,3 +144,5 @@
" - Variant: 1 ... 15\n"
" - Revision: A...O\n"
" - BOM: 1...15\n");
+
+#endif
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
index 4fa2360..c5ab755 100644
--- a/board/st/stm32mp1/Kconfig
+++ b/board/st/stm32mp1/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_STM32MP1
+if TARGET_ST_STM32MP15x
config SYS_BOARD
default "stm32mp1"
@@ -9,21 +9,5 @@
config SYS_CONFIG_NAME
default "stm32mp1"
-config ENV_SECT_SIZE
- default 0x40000 if ENV_IS_IN_SPI_FLASH
-
-config ENV_OFFSET
- default 0x280000 if ENV_IS_IN_SPI_FLASH
-
-config CMD_STBOARD
- bool "stboard - command for OTP board information"
- default y
- help
- This compile the stboard command to
- read and write the board in the OTP.
-
-config TARGET_STM32MP157C_DK2
- bool "support of STMicroelectronics STM32MP157C-DK2 Discovery Board"
- default y
-
+source "board/st/common/Kconfig"
endif
diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile
index 3c6c035..8188075 100644
--- a/board/st/stm32mp1/Makefile
+++ b/board/st/stm32mp1/Makefile
@@ -7,7 +7,6 @@
obj-y += spl.o
else
obj-y += stm32mp1.o
-obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
endif
obj-y += board.o
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 9c345c7..e82a430 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -608,7 +608,7 @@
static bool board_is_dk2(void)
{
- if (CONFIG_IS_ENABLED(TARGET_STM32MP157C_DK2) &&
+ if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
of_machine_is_compatible("st,stm32mp157c-dk2"))
return true;
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 36f8692..21fc5ed 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <eeprom.h>
+#include <dm/uclass.h>
#include <env.h>
#include <fdt_support.h>
#include <i2c.h>
@@ -29,8 +30,6 @@
#include <power/pmic.h>
#include <power/tps65218.h>
#include <power/tps62362.h>
-#include <miiphy.h>
-#include <cpsw.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
@@ -854,109 +853,6 @@
#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-static void cpsw_control(int enabled)
-{
- /* Additional controls can be added here */
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 16,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int rv;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("ethaddr")) {
- puts("<ethaddr> not set. Validating first E-fuse MAC\n");
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("eth1addr", mac_addr);
- }
-
- if (board_is_eposevm()) {
- writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
- cpsw_slaves[0].phy_addr = 16;
- } else if (board_is_sk()) {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
- cpsw_slaves[0].phy_addr = 4;
- cpsw_slaves[1].phy_addr = 5;
- } else if (board_is_idk()) {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
- cpsw_slaves[0].phy_addr = 0;
- } else {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
- cpsw_slaves[0].phy_addr = 0;
- }
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
-
- return rv;
-}
-#endif
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index c57473c..d70ab0c 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -15,6 +15,7 @@
#include <sata.h>
#include <serial.h>
#include <usb.h>
+#include <errno.h>
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/emif.h>
@@ -38,6 +39,10 @@
#include "../common/board_detect.h"
#include "mux_data.h"
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int board_bootmode_has_emmc(void);
+#endif
+
#define board_is_x15() board_ti_is("BBRDX15_")
#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
!strncmp("B.10", board_ti_get_rev(), 3))
@@ -50,6 +55,7 @@
#define board_is_am574x_idk() board_ti_is("AM574IDK")
#define board_is_am572x_idk() board_ti_is("AM572IDK")
#define board_is_am571x_idk() board_ti_is("AM571IDK")
+#define board_is_bbai() board_ti_is("BBONE-AI")
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
@@ -99,12 +105,19 @@
.is_ma_present = 0x1
};
+static const struct dmm_lisa_map_regs bbai_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80640100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
if (board_is_am571x_idk())
*dmm_lisa_regs = &am571x_idk_lisa_regs;
else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;
+ else if (board_is_bbai())
+ *dmm_lisa_regs = &bbai_lisa_regs;
else
*dmm_lisa_regs = &beagle_x15_lisa_regs;
}
@@ -508,6 +521,14 @@
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ rc = board_bootmode_has_emmc();
+ if (!rc)
+ rc = ti_emmc_boardid_get();
+ if (rc)
+ printf("ti_emmc_boardid_get failed %d\n", rc);
+#endif
}
#else /* CONFIG_SPL_BUILD */
@@ -523,6 +544,14 @@
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ rc = board_bootmode_has_emmc();
+ if (!rc)
+ rc = ti_emmc_boardid_get();
+ if (rc)
+ printf("ti_emmc_boardid_get failed %d\n", rc);
+#endif
+
if (board_is_x15())
bname = "BeagleBoard X15";
else if (board_is_am572x_evm())
@@ -533,6 +562,8 @@
bname = "AM572x IDK";
else if (board_is_am571x_idk())
bname = "AM571x IDK";
+ else if (board_is_bbai())
+ bname = "BeagleBone AI";
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
@@ -567,6 +598,8 @@
name = "am572x_idk";
} else if (board_is_am571x_idk()) {
name = "am571x_idk";
+ } else if (board_is_bbai()) {
+ name = "am5729_beagleboneai";
} else {
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
@@ -630,7 +663,7 @@
struct udevice *dev;
/* Only valid for IDKs */
- if (board_is_x15() || board_is_am572x_evm())
+ if (board_is_x15() || board_is_am572x_evm() || board_is_bbai())
return;
/* Only AM571x IDK has gpio control detect.. so check that */
@@ -728,6 +761,9 @@
/* Just probe the potentially supported cdce913 device */
uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (board_is_bbai())
+ env_set("console", "ttyS0,115200n8");
+
#if !defined(CONFIG_SPL_BUILD)
board_ti_set_ethaddr(2);
#endif
@@ -745,6 +781,11 @@
{
do_set_mux32((*ctrl)->control_padconf_core_base,
early_padconf, ARRAY_SIZE(early_padconf));
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ emmc_padconf, ARRAY_SIZE(emmc_padconf));
+#endif
}
#ifdef CONFIG_IODELAY_RECALIBRATION
@@ -770,6 +811,11 @@
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
iod = iodelay_cfg_array_am571x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
+ } else if (board_is_bbai()) {
+ pconf = core_padconf_array_essential_bbai;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
+ iod = iodelay_cfg_array_bbai;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
} else {
/* Common for X15/GPEVM */
pconf = core_padconf_array_essential_x15;
@@ -1098,6 +1144,8 @@
return 0;
} else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
return 0;
+ } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
+ return 0;
}
return -1;
@@ -1114,6 +1162,17 @@
}
#endif
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int board_bootmode_has_emmc(void)
+{
+ /* Check that boot mode is same as BBAI */
+ if (gd->arch.omap_boot_mode != 2)
+ return -EIO;
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index d4a15ae..212799c 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -233,6 +233,203 @@
{RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
};
+const struct pad_conf_entry core_padconf_array_essential_bbai[] = {
+ /* Cape Bus i2c */
+ /* NOTE: For the i2cj_scl and i2ci_scl signals to work properly, the INPUTENABLE bit of the
+ * appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming
+ * purposes.
+ */
+ {GPMC_A0, (M7 | PIN_INPUT_PULLUP)}, /* P9_19A: R6_GPIO7_3: gpmc_a0.i2c4_scl (Shared with F4_UART10_RTSN) */
+ {GPMC_A1, (M7 | PIN_INPUT_PULLUP)}, /* P9_20A: T9_GPIO7_4: gpmc_a1.i2c4_sda (Shared with D2_UART10_CTSN) */
+
+ /* Bluetooth UART */
+ {GPMC_A4, (M8 | PIN_INPUT)}, /* P6 UART6_RXD: gpmc_a4.uart6_rxd */
+ {GPMC_A5, (M8 | PIN_OUTPUT)}, /* R9 UART6_TXD: gpmc_a5.uart6_txd */
+ {GPMC_A6, (M8 | PIN_INPUT)}, /* R5 UART6_CTSN: gpmc_a6.uart6_ctsn */
+ {GPMC_A7, (M8 | PIN_OUTPUT)}, /* P5 UART6_RTSN: gpmc_a7.uart6_rtsn */
+
+ /* eMMC */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* K7: gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* M7: gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J5: gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* K6: gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J7: gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J4: gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J6: gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* H4: gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* H5: gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* H6: gpmc_cs1.mmc2_cmd */
+
+ {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* N1 RGMII_RST: gpmc_advn_ale.gpio2_23 */
+
+ {VIN1A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* AG8 INT_ADC: vin1a_clk0.gpio2_30 */
+ {VIN1A_DE0, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_35B: AD9_EQEP1A_IN: vin1a_de0.eQEP1A_in */
+ {VIN1A_FLD0, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_33B: AF9_EQEP1B_IN: vin1a_fld0.eQEP1B_in */
+ {VIN1A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_21A: AF8_TIMER13: vin1a_vsync0.gpio3_3 */
+
+ {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* AH6 USR4: vin1a_d3.gpio3_7 */
+
+ {VIN1A_D6, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_12: AG6: vin1a_d6.eQEP2A_in */
+ {VIN1A_D7, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_11: AH4: vin1a_d7.eQEP2B_in */
+ {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_15: AG4: vin1a_d8.gpio3_12 */
+ {VIN1A_D9, (M14 | PIN_INPUT)}, /* AG2 USB ID: vin1a_d9.gpio3_13 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* AG3 USR3: vin1a_d10.gpio3_14 */
+ {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* AG5 USR2: vin1a_d11.gpio3_15 */
+ {VIN1A_D13, (M14 | PIN_OUTPUT_PULLDOWN)}, /* AF6 USR0: vin1a_d13.gpio3_17 */
+ {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* AF3 WL_REG_ON: vin1a_d14.gpio3_18 */
+ {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* AF1 BT_HOST_WAKE: vin1a_d16.gpio3_20 */
+ {VIN1A_D17, (M14 | PIN_OUTPUT_PULLDOWN)}, /* AE3 BT_WAKE: vin1a_d17.gpio3_21 */
+ {VIN1A_D18, (M14 | PIN_OUTPUT_PULLUP)}, /* AE5 BT_REG_ON: vin1a_d18.gpio3_22 */
+ {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* AE1 WL_HOST_WAKE: vin1a_d19.gpio3_23 */
+ {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_26B: AE2: vin1a_d20.gpio3_24 */
+ {VIN1A_D23, (M14 | PIN_OUTPUT_PULLDOWN)}, /* AD3 VDD_ADC_SEL: vin1a_d23.gpio3_27 */
+
+ {VIN2A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_15A: D1: vin2a_d2.gpio4_3 */
+
+ /* Cape Bus i2c (gpio shared) */
+ {VIN2A_D4, (M14 | PIN_INPUT)}, /* P9_20B: D2_UART10_CTSN: vin2a_d4. (Shared with T9_GPIO7_4) */
+ {VIN2A_D5, (M14 | PIN_INPUT)}, /* P9_19B: F4_UART10_RTSN: vin2a_d5. (Shared with R6_GPIO7_3) */
+
+ {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_18: F5_GPIO4_9: vin2a_d8.gpio4_9 */
+ {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_19: E6_EHRPWM2A: vin2a_d9.gpio4_10 */
+ {VIN2A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_13: D3_EHRPWM2B: vin2a_d10.gpio4_11 */
+ {VIN2A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_14: D5_GPIO4_13: vin2a_d12.gpio4_13 */
+ {VIN2A_D13, (M10 | PIN_INPUT_PULLDOWN)}, /* P9_42B: C2_GPIO4_14: vin2a_d13.eQEP3A_in */
+ {VIN2A_D14, (M10 | PIN_INPUT_PULLDOWN)}, /* P9_27A: C3_GPIO4_15: vin2a_d14.eQEP3B_in */
+ {VIN2A_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_14: D6_EHRPWM3A: vin2a_d17.gpio4_25 */
+ {VIN2A_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_16: C5_EHRPWM3B: vin2a_d18.gpio4_26 */
+ {VIN2A_D19, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_15B: A3_GPIO4_27: vin2a_d19.pr1_pru1_gpi16 */
+ {VIN2A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_26: B3_GPIO4_28: vin2a_d20.gpio4_28 */
+ {VIN2A_D21, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_16: B4_GPIO4_29: vin2a_d21.pr1_pru1_gpi18 */
+ {VOUT1_CLK, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_28A: D11_VOUT1_CLK: vout1_clk.gpio4_19 */
+ {VOUT1_DE, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_30A: B10_VOUT1_DE: vout1_de.gpio4_20 */
+ {VOUT1_HSYNC, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_29A: C11_VOUT1_HSYNC: vout1_hsync.gpio4_22 */
+ {VOUT1_VSYNC, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_27A: E11_VOUT1_VSYNC: vout1_vsync.gpio4_23 */
+ {VOUT1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_45A: F11_VOUT1_D0: vout1_d0.gpio8_0 */
+ {VOUT1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_46A: G10_VOUT1_D1: vout1_d1.gpio8_1 */
+ {VOUT1_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_43: F10_LCD_DATA2: vout1_d2.gpio8_2 */
+ {VOUT1_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_44: G11_LCD_DATA3: vout1_d3.gpio8_3 */
+ {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_41: E9_LCD_DATA4: vout1_d4.pr2_pru0_gpi1 */
+ {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_42: F9_LCD_DATA5: vout1_d5.pr2_pru0_gpi2 */
+ {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_39: F8_LCD_DATA6: vout1_d6.pr2_pru0_gpi3 */
+ {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_40: E7_LCD_DATA7: vout1_d7.pr2_pru0_gpi4 */
+ {VOUT1_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_37A: E8_VOUT1_D8: vout1_d8.gpio8_8 */
+ {VOUT1_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_38A: D9_VOUT1_D9: vout1_d9.gpio8_9 */
+ {VOUT1_D10, (M14 | PIN_INPUT)}, /* P8_36A: D7_VOUT1_D10: vout1_d10.gpio8_10 */
+ {VOUT1_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_34A: D8_VOUT1_D11: vout1_d11.gpio8_11 */
+ {VOUT1_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_31A: C8_VOUT1_D14: vout1_d14.gpio8_14 */
+ {VOUT1_D15, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_32A: C7_VOUT1_D15: vout1_d15.gpio8_15 */
+ {VOUT1_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_11B: B8_GPIO8_17: vout1_d17.gpio8_17 */
+ {VOUT1_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_17: A7_GPIO8_18: vout1_d18.gpio8_18 */
+ {VOUT1_D19, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_27B: A8_GPIO8_19: vout1_d19.pr2_pru0_gpi16 */
+ {VOUT1_D20, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_28B: C9_GPIO8_20: vout1_d20.pr2_pru0_gpi17 */
+ {VOUT1_D21, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_29B: A9_GPIO8_21: vout1_d21.pr2_pru0_gpi18 */
+ {VOUT1_D22, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_30B: B9_GPIO8_22: vout1_d22.pr2_pru0_gpi19 */
+
+ /* Ethernet (and USB A overcurrent) */
+ {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* V1 MDIO_CLK: mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* U4 MDIO_D: mdio_d.mdio_d */
+ {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* V2 GPIO5_18 (USB A overcurrent): uart3_rxd.gpio5_18 */
+ {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* Y1 MII0_INT: uart3_txd.gpio5_19 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* W9 RGMII0_TXC: rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* V9 RGMII0_TXCTL: rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* V7 RGMII0_TXD3: rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* U7 RGMII0_TXD2: rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* V6 RGMII0_TXD1: rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* U6 RGMII0_TXD0: rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* U5 RGMII0_RXC: rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* V5 RGMII0_RXCTL: rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* V4 RGMII0_RXD3: rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* V3 RGMII0_RXD2: rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* Y2 RGMII0_RXD1: rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* W2 RGMII0_RXD0: rgmii0_rxd0.rgmii0_rxd0 */
+
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* AC10 USB2_DRVVBUS: usb2_drvvbus.usb2_drvvbus */
+
+ {GPIO6_14, (M3 | PIN_INPUT)}, /* P9_26A: E21_UART10_RXD: gpio6_14.uart10_rxd */
+ {GPIO6_15, (M0 | PIN_INPUT_PULLDOWN)}, /* P9_24: F20_UART10_TXD: gpio6_15.gpio6_15 */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* F21 PMIC_INT: gpio6_16.gpio6_16 */
+ {XREF_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_25: D18_GPIO6_17: xref_clk0.gpio6_17 */
+ {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_09: E17_TIMER14: xref_clk1.gpio6_18 */
+ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_22A: B26_TIMER15: xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_41A: C23_CLKOUT3: xref_clk3.gpio6_20 */
+ {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_12: B14_MCASP_ACLKR: mcasp1_aclkr.gpio5_0 */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* P9_18B: G12_GPIO5_2: mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* P9_17B: F12_GPIO5_3: mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* J11 USR1: mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* F13 eMMC_RSTn (missing on schematic): mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR8, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_31A: B12_SPI3_SCLK: mcasp1_axr8.gpio5_10 */
+ {MCASP1_AXR9, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_29A: A11_SPI3_D1: mcasp1_axr9.gpio5_11 */
+ {MCASP1_AXR10, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_30: B13_SPI3_D0: mcasp1_axr10.gpio5_12 */
+ {MCASP1_AXR11, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_28: A12_SPI3_CS0: mcasp1_axr11.gpio4_17 */
+ {MCASP1_AXR12, (M14 | PIN_INPUT | SLEWCONTROL)}, /* P9_42A: E14_GPIO4_18: mcasp1_axr12.gpio4_18 */
+ {MCASP1_AXR13, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P8_10: A13_TIMER10: mcasp1_axr13.gpio6_4 */
+ {MCASP1_AXR14, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P8_07: G14_TIMER11: mcasp1_axr14.gpio6_5 */
+ {MCASP1_AXR15, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P8_08: F14_TIMER12: mcasp1_axr15.gpio6_6 */
+ {MCASP3_AXR0, (M4 | PIN_INPUT | SLEWCONTROL)}, /* P9_11A: B19_UART5_RXD: mcasp3_axr0.uart5_rxd */
+
+ /* microSD Socket */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* W6: mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* Y6: mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* AA6: mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* Y4: mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* AA5: mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* Y3: mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* W7: mmc1_sdcd.gpio6_27 */
+
+ {MMC3_CLK, (M14 | PIN_INPUT_PULLUP)}, /* P8_21: AD4_MMC3_CLK: mmc3_clk.gpio6_29 */
+ {MMC3_CMD, (M14 | PIN_INPUT_PULLUP)}, /* P8_20: AC4_MMC3_CMD: mmc3_cmd.gpio6_30 */
+ {MMC3_DAT0, (M14 | PIN_INPUT_PULLUP)}, /* P8_25: AC7_MMC3_DATA0: mmc3_dat0.gpio6_31 */
+ {MMC3_DAT1, (M14 | PIN_INPUT_PULLUP)}, /* P8_24: AC6_MMC3_DATA1: mmc3_dat1.gpio7_0 */
+ {MMC3_DAT2, (M14 | PIN_INPUT_PULLUP)}, /* P8_05: AC9_MMC3_DATA2: mmc3_dat2.gpio7_1 */
+ {MMC3_DAT3, (M14 | PIN_INPUT_PULLUP)}, /* P8_06: AC3_MMC3_DATA3: mmc3_dat3.gpio7_2 */
+ {MMC3_DAT4, (M14 | PIN_INPUT_PULLUP)}, /* P8_23: AC8_MMC3_DATA4: mmc3_dat4.gpio1_22 */
+ {MMC3_DAT5, (M14 | PIN_INPUT_PULLUP)}, /* P8_22: AD6_MMC3_DATA5: mmc3_dat5.gpio1_23 */
+ {MMC3_DAT6, (M14 | PIN_INPUT_PULLUP)}, /* P8_03: AB8_MMC3_DATA6: mmc3_dat6.gpio1_24 */
+ {MMC3_DAT7, (M14 | PIN_INPUT_PULLUP)}, /* P8_04: AB5_MMC3_DATA7: mmc3_dat7.gpio1_25 */
+ {SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_23: A22_SPI2_CS1: spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M6 | PIN_INPUT | SLEWCONTROL)}, /* B21 HDMI_DDC_HPD: spi1_cs2.hdmi1_hpd */
+ {SPI2_SCLK, (M1 | PIN_INPUT)}, /* P9_22B: A26_UART3_RXD: spi2_sclk.uart3_rxd */
+ {SPI2_D0, (M14 | PIN_INPUT | SLEWCONTROL)}, /* P9_18A: G17_SPI2_D0: spi2_d0.gpio7_16 */
+ {SPI2_CS0, (M14 | PIN_INPUT | SLEWCONTROL)}, /* P9_17A: B24_SPI2_CS0: spi2_cs0.gpio7_17 */
+ {DCAN1_TX, (M2 | PIN_INPUT | SLEWCONTROL)}, /* G20 unused: dcan1_tx.uart8_rxd */
+ {DCAN1_RX, (M6 | PIN_INPUT | SLEWCONTROL)}, /* G19 unused: dcan1_rx.hdmi1_cec */
+
+ /* BeagleBone AI: Debug UART */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
+
+ /* WiFi MMC */
+ {UART1_CTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart1_ctsn.mmc4_clk */
+ {UART1_RTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart1_rtsn.mmc4_cmd */
+ {UART2_RXD, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_rxd.mmc4_dat0 */
+ {UART2_TXD, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_txd.mmc4_dat1 */
+ {UART2_CTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_ctsn.mmc4_dat2 */
+ {UART2_RTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_rtsn.mmc4_dat3 */
+
+ /* On-board I2C */
+ {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */
+
+ /* HDMI I2C */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* Y11: on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* AB17: rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* F18: tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* D23: tdi.tdi */
+ {TDO, (M0 | PIN_OUTPUT)}, /* F19: tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* E20: tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT)}, /* D20: trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT)}, /* E18: rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT)}, /* G21: emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT)}, /* D24: emu1.emu1 */
+ {RESETN, (M0 | PIN_INPUT_PULLUP)}, /* E23: resetn.resetn */
+ {NMIN_DSP, (M0 | PIN_INPUT)}, /* D21: nmin_dsp.nmin_dsp */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* F23: rstoutn.rstoutn */
+};
+
const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */
@@ -297,6 +494,69 @@
{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
};
+const struct iodelay_cfg_entry iodelay_cfg_array_bbai[] = {
+ {0x0190, 274, 0}, /* CFG_GPMC_A19_OEN */
+ {0x0194, 162, 0}, /* CFG_GPMC_A19_OUT */
+ {0x01A8, 401, 0}, /* CFG_GPMC_A20_OEN */
+ {0x01AC, 73, 0}, /* CFG_GPMC_A20_OUT */
+ {0x01B4, 465, 0}, /* CFG_GPMC_A21_OEN */
+ {0x01B8, 115, 0}, /* CFG_GPMC_A21_OUT */
+ {0x01C0, 633, 0}, /* CFG_GPMC_A22_OEN */
+ {0x01C4, 47, 0}, /* CFG_GPMC_A22_OUT */
+ {0x01D0, 935, 280}, /* CFG_GPMC_A23_OUT */
+ {0x01D8, 621, 0}, /* CFG_GPMC_A24_OEN */
+ {0x01DC, 0, 0}, /* CFG_GPMC_A24_OUT */
+ {0x01E4, 183, 0}, /* CFG_GPMC_A25_OEN */
+ {0x01E8, 0, 0}, /* CFG_GPMC_A25_OUT */
+ {0x01F0, 467, 0}, /* CFG_GPMC_A26_OEN */
+ {0x01F4, 0, 0}, /* CFG_GPMC_A26_OUT */
+ {0x01FC, 262, 0}, /* CFG_GPMC_A27_OEN */
+ {0x0200, 46, 0}, /* CFG_GPMC_A27_OUT */
+ {0x0364, 684, 0}, /* CFG_GPMC_CS1_OEN */
+ {0x0368, 76, 0}, /* CFG_GPMC_CS1_OUT */
+ {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0840, 0, 0}, /* CFG_UART1_CTSN_IN */
+ {0x0848, 0, 0}, /* CFG_UART1_CTSN_OUT */
+ {0x084C, 307, 0}, /* CFG_UART1_RTSN_IN */
+ {0x0850, 0, 0}, /* CFG_UART1_RTSN_OEN */
+ {0x0854, 0, 0}, /* CFG_UART1_RTSN_OUT */
+ {0x0870, 785, 0}, /* CFG_UART2_CTSN_IN */
+ {0x0874, 0, 0}, /* CFG_UART2_CTSN_OEN */
+ {0x0878, 0, 0}, /* CFG_UART2_CTSN_OUT */
+ {0x087C, 613, 0}, /* CFG_UART2_RTSN_IN */
+ {0x0880, 0, 0}, /* CFG_UART2_RTSN_OEN */
+ {0x0884, 0, 0}, /* CFG_UART2_RTSN_OUT */
+ {0x0888, 683, 0}, /* CFG_UART2_RXD_IN */
+ {0x088C, 0, 0}, /* CFG_UART2_RXD_OEN */
+ {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */
+ {0x0894, 835, 0}, /* CFG_UART2_TXD_IN */
+ {0x0898, 0, 0}, /* CFG_UART2_TXD_OEN */
+ {0x089C, 0, 0}, /* CFG_UART2_TXD_OUT */
+ {0x0ABC, 0, 1100}, /* CFG_VIN2A_D19_IN */
+ {0x0AE0, 0, 1300}, /* CFG_VIN2A_D21_IN */
+ {0x0B1C, 0, 1000}, /* CFG_VIN2A_D4_IN */
+ {0x0B28, 0, 1700}, /* CFG_VIN2A_D5_IN */
+ {0x0C18, 0, 500}, /* CFG_VOUT1_D19_IN */
+ {0x0C30, 0, 716}, /* CFG_VOUT1_D20_IN */
+ {0x0C3C, 0, 0}, /* CFG_VOUT1_D21_IN */
+ {0x0C48, 0, 404}, /* CFG_VOUT1_D22_IN */
+ {0x0C78, 0, 0}, /* CFG_VOUT1_D4_IN */
+ {0x0C84, 0, 365}, /* CFG_VOUT1_D5_IN */
+ {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */
+ {0x0C9C, 0, 218}, /* CFG_VOUT1_D7_IN */
+};
+
const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = {
{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
@@ -998,8 +1258,28 @@
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
{I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */
{I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */
+
+ /* BeagleBone AI: Debug UART */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
};
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+const struct pad_conf_entry emmc_padconf[] = {
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* K7: gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* M7: gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* J5: gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* K6: gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* J7: gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* J4: gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* J6: gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* H4: gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* H5: gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* H6: gpmc_cs1.mmc2_cmd */
+ {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* F13: eMMC_RSTn (missing on schematic): mcasp1_axr5.gpio5_7 */
+};
+#endif
+
#ifdef CONFIG_IODELAY_RECALIBRATION
const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
{0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 4d86757..a610879 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -105,10 +105,8 @@
#if defined(CONFIG_TI_SECURE_DEVICE)
/* Make HW RNG reserved for secure world use */
ret = fdt_disable_node(blob, "/interconnect@100000/trng@4e10000");
- if (ret) {
+ if (ret)
printf("%s: disabling TRGN failed %d\n", __func__, ret);
- return ret;
- }
#endif
return 0;
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 564d2f7..cbd35f2 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -14,6 +14,9 @@
#include <dm/uclass.h>
#include <env.h>
#include <i2c.h>
+#include <mmc.h>
+#include <errno.h>
+#include <malloc.h>
#include "board_detect.h"
@@ -91,7 +94,7 @@
rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus);
if (rc)
return rc;
- rc = i2c_get_chip(bus, dev_addr, 1, &dev);
+ rc = dm_i2c_probe(bus, dev_addr, 0, &dev);
if (rc)
return rc;
@@ -171,6 +174,79 @@
return 0;
}
+int __maybe_unused ti_emmc_boardid_get(void)
+{
+ int rc;
+ struct udevice *dev;
+ struct mmc *mmc;
+ struct ti_common_eeprom *ep;
+ struct ti_am_eeprom brdid;
+ struct blk_desc *bdesc;
+ uchar *buffer;
+
+ ep = TI_EEPROM_DATA;
+ if (ep->header == TI_EEPROM_HEADER_MAGIC)
+ return 0; /* EEPROM has already been read */
+
+ /* Initialize with a known bad marker for emmc fails.. */
+ ep->header = TI_DEAD_EEPROM_MAGIC;
+ ep->name[0] = 0x0;
+ ep->version[0] = 0x0;
+ ep->serial[0] = 0x0;
+ ep->config[0] = 0x0;
+
+ /* uclass object initialization */
+ rc = mmc_initialize(NULL);
+ if (rc)
+ return rc;
+
+ /* Set device to /dev/mmcblk1 */
+ rc = uclass_get_device(UCLASS_MMC, 1, &dev);
+ if (rc)
+ return rc;
+
+ /* Grab the mmc device */
+ mmc = mmc_get_mmc_dev(dev);
+ if (!mmc)
+ return -ENODEV;
+
+ /* mmc hardware initialization routine */
+ mmc_init(mmc);
+
+ /* Set partition to /dev/mmcblk1boot1 */
+ rc = mmc_switch_part(mmc, 2);
+ if (rc)
+ return rc;
+
+ buffer = malloc(mmc->read_bl_len);
+ if (!buffer)
+ return -ENOMEM;
+
+ bdesc = mmc_get_blk_desc(mmc);
+
+ /* blk_dread returns the number of blocks read*/
+ if (blk_dread(bdesc, 0L, 1, buffer) != 1) {
+ rc = -EIO;
+ goto cleanup;
+ }
+
+ memcpy(&brdid, buffer, sizeof(brdid));
+
+ /* Write out the ep struct values */
+ ep->header = brdid.header;
+ strlcpy(ep->name, brdid.name, TI_EEPROM_HDR_NAME_LEN + 1);
+ ti_eeprom_string_cleanup(ep->name);
+ strlcpy(ep->version, brdid.version, TI_EEPROM_HDR_REV_LEN + 1);
+ ti_eeprom_string_cleanup(ep->version);
+ strlcpy(ep->serial, brdid.serial, TI_EEPROM_HDR_SERIAL_LEN + 1);
+ ti_eeprom_string_cleanup(ep->serial);
+
+cleanup:
+ free(buffer);
+
+ return rc;
+}
+
int __maybe_unused ti_i2c_eeprom_am_set(const char *name, const char *rev)
{
struct ti_common_eeprom *ep;
@@ -472,6 +548,15 @@
return ret;
}
+bool __maybe_unused board_ti_k3_is(char *name_tag)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (ep->header == TI_DEAD_EEPROM_MAGIC)
+ return false;
+ return !strncmp(ep->name, name_tag, AM6_EEPROM_HDR_NAME_LEN);
+}
+
bool __maybe_unused board_ti_is(char *name_tag)
{
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index a45d896..5835af5 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -268,6 +268,15 @@
int ti_i2c_eeprom_am_get(int bus_addr, int dev_addr);
/**
+ * ti_emmc_boardid_get() - Fetch board ID information from eMMC
+ *
+ * ep in SRAM is populated by the this function that is currently
+ * based on BeagleBone AI, but could be made more general across AM*
+ * platforms.
+ */
+int __maybe_unused ti_emmc_boardid_get(void);
+
+/**
* ti_i2c_eeprom_dra7_get() - Consolidated eeprom data for DRA7 TI EVMs
* @bus_addr: I2C bus address
* @dev_addr: I2C slave address
@@ -311,6 +320,15 @@
bool board_ti_is(char *name_tag);
/**
+ * board_ti_k3_is() - Board detection logic for TI K3 EVMs
+ * @name_tag: Tag used in eeprom for the board
+ *
+ * Return: false if board information does not match OR eeprom wasn't read.
+ * true otherwise
+ */
+bool board_ti_k3_is(char *name_tag);
+
+/**
* board_ti_rev_is() - Compare board revision for TI EVMs
* @rev_tag: Revision tag to check in eeprom
* @cmp_len: How many chars to compare?
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 94001a4..8132cdf 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -13,6 +13,7 @@
#include <env.h>
#include <fdt_support.h>
#include <init.h>
+#include <spl.h>
#include <palmas.h>
#include <sata.h>
#include <serial.h>
@@ -32,7 +33,6 @@
#include <dwc3-omap-uboot.h>
#include <i2c.h>
#include <ti-usb-phy-uboot.h>
-#include <miiphy.h>
#include "mux_data.h"
#include "../common/board_detect.h"
@@ -48,10 +48,6 @@
#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
-#ifdef CONFIG_DRIVER_TI_CPSW
-#include <cpsw.h>
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
/* GPIO 7_11 */
@@ -992,106 +988,6 @@
}
#endif
-#ifdef CONFIG_DRIVER_TI_CPSW
-extern u32 *const omap_si_rev;
-
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 2,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 3,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 2,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
- uint32_t ctrl_val;
-
- /* try reading mac address from efuse */
- mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!env_get("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("eth1addr", mac_addr);
- }
-
- ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
- ctrl_val |= 0x22;
- writel(ctrl_val, (*ctrl)->control_core_control_io1);
-
- if (*omap_si_rev == DRA722_ES1_0)
- cpsw_data.active_slave = 1;
-
- if (board_is_dra72x_revc_or_later()) {
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
- cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
- }
-
- ret = cpsw_register(&cpsw_data);
- if (ret < 0)
- printf("Error %d registering CPSW switch\n", ret);
-
- return ret;
-}
-#endif
-
#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 88097df..e56dc53 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -11,6 +11,8 @@
bool "TI K3 based J721E EVM running on A72"
select ARM64
select SOC_K3_J721E
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
select SYS_DISABLE_DCACHE_OPS
config TARGET_J721E_R5_EVM
@@ -23,6 +25,7 @@
select SPL_RAM
select K3_J721E_DDRSS
imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
endchoice
@@ -37,6 +40,8 @@
config SYS_CONFIG_NAME
default "j721e_evm"
+source "board/ti/common/Kconfig"
+
endif
if TARGET_J721E_R5_EVM
@@ -53,4 +58,6 @@
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
+source "board/ti/common/Kconfig"
+
endif
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 51b121c..aa2240b 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -9,10 +9,21 @@
#include <common.h>
#include <init.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
+#include "../common/board_detect.h"
+
+#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \
+ board_ti_k3_is("J721EX-PM2-SOM"))
+
+/* Max number of MAC addresses that are parsed/processed per daughter card */
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR 8
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -81,3 +92,256 @@
return ret;
}
#endif
+
+int do_board_detect(void)
+{
+ int ret;
+
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (ret)
+ pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+ CONFIG_EEPROM_CHIP_ADDRESS, ret);
+
+ return ret;
+}
+
+int checkboard(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (do_board_detect())
+ /* EEPROM not populated */
+ printf("Board: %s rev %s\n", "J721EX-PM1-SOM", "E2");
+ else
+ printf("Board: %s rev %s\n", ep->name, ep->version);
+
+ return 0;
+}
+
+static void setup_board_eeprom_env(void)
+{
+ char *name = "j721e";
+
+ if (do_board_detect())
+ goto invalid_eeprom;
+
+ if (board_is_j721e_som())
+ name = "j721e";
+ else
+ printf("Unidentified board claims %s in eeprom header\n",
+ board_ti_get_name());
+
+invalid_eeprom:
+ set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+ unsigned long board_serial;
+ char *endp;
+ char serial_string[17] = { 0 };
+
+ if (env_get("serial#"))
+ return;
+
+ board_serial = simple_strtoul(ep->serial, &endp, 16);
+ if (*endp != '\0') {
+ pr_err("Error: Can't set serial# to %s\n", ep->serial);
+ return;
+ }
+
+ snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+ env_set("serial#", serial_string);
+}
+
+/*
+ * Declaration of daughtercards to probe. Note that when adding more
+ * cards they should be grouped by the 'i2c_addr' field to allow for a
+ * more efficient probing process.
+ */
+static const struct {
+ u8 i2c_addr; /* I2C address of card EEPROM */
+ char *card_name; /* EEPROM-programmed card name */
+ char *dtbo_name; /* Device tree overlay to apply */
+ u8 eth_offset; /* ethXaddr MAC address index offset */
+} ext_cards[] = {
+ {
+ 0x51,
+ "J7X-BASE-CPB",
+ "", /* No dtbo for this board */
+ 0,
+ },
+ {
+ 0x52,
+ "J7X-INFOTAN-EXP",
+ "", /* No dtbo for this board */
+ 0,
+ },
+ {
+ 0x52,
+ "J7X-GESI-EXP",
+ "", /* No dtbo for this board */
+ 5, /* Start populating from eth5addr */
+ },
+ {
+ 0x54,
+ "J7X-VSC8514-ETH",
+ "", /* No dtbo for this board */
+ 1, /* Start populating from eth1addr */
+ },
+};
+
+static bool daughter_card_detect_flags[ARRAY_SIZE(ext_cards)];
+
+const char *board_fit_get_additionnal_images(int index, const char *type)
+{
+ int i, j;
+
+ if (strcmp(type, FIT_FDT_PROP))
+ return NULL;
+
+ j = 0;
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ if (daughter_card_detect_flags[i]) {
+ if (j == index) {
+ /*
+ * Return dtbo name only if populated,
+ * otherwise stop parsing here.
+ */
+ if (strlen(ext_cards[i].dtbo_name))
+ return ext_cards[i].dtbo_name;
+ else
+ return NULL;
+ };
+
+ j++;
+ }
+ }
+
+ return NULL;
+}
+
+static int probe_daughtercards(void)
+{
+ char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+ bool eeprom_read_success;
+ struct ti_am6_eeprom ep;
+ u8 previous_i2c_addr;
+ u8 mac_addr_cnt;
+ int i;
+ int ret;
+
+ /* Mark previous I2C address variable as not populated */
+ previous_i2c_addr = 0xff;
+
+ /* No EEPROM data was read yet */
+ eeprom_read_success = false;
+
+ /* Iterate through list of daughtercards */
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ /* Obtain card-specific I2C address */
+ u8 i2c_addr = ext_cards[i].i2c_addr;
+
+ /* Read card EEPROM if not already read previously */
+ if (i2c_addr != previous_i2c_addr) {
+ /* Store I2C address so we can avoid reading twice */
+ previous_i2c_addr = i2c_addr;
+
+ /* Get and parse the daughter card EEPROM record */
+ ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS,
+ i2c_addr,
+ &ep,
+ (char **)mac_addr,
+ DAUGHTER_CARD_NO_OF_MAC_ADDR,
+ &mac_addr_cnt);
+ if (ret) {
+ debug("%s: No daughtercard EEPROM at 0x%02x found %d\n",
+ __func__, i2c_addr, ret);
+ eeprom_read_success = false;
+ /* Skip to the next daughtercard to probe */
+ continue;
+ }
+
+ /* EEPROM read successful, okay to further process. */
+ eeprom_read_success = true;
+ }
+
+ /* Only continue processing if EEPROM data was read */
+ if (!eeprom_read_success)
+ continue;
+
+ /* Only process the parsed data if we found a match */
+ if (strncmp(ep.name, ext_cards[i].card_name, sizeof(ep.name)))
+ continue;
+
+ printf("Detected: %s rev %s\n", ep.name, ep.version);
+ daughter_card_detect_flags[i] = true;
+
+#ifndef CONFIG_SPL_BUILD
+ int j;
+ /*
+ * Populate any MAC addresses from daughtercard into the U-Boot
+ * environment, starting with a card-specific offset so we can
+ * have multiple ext_cards contribute to the MAC pool in a well-
+ * defined manner.
+ */
+ for (j = 0; j < mac_addr_cnt; j++) {
+ if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+ continue;
+
+ eth_env_set_enetaddr_by_index("eth",
+ ext_cards[i].eth_offset + j,
+ (uchar *)mac_addr[j]);
+ }
+#endif
+ }
+#ifndef CONFIG_SPL_BUILD
+ char name_overlays[1024] = { 0 };
+
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ if (!daughter_card_detect_flags[i])
+ continue;
+
+ /* Skip if no overlays are to be added */
+ if (!strlen(ext_cards[i].dtbo_name))
+ continue;
+
+ /*
+ * Make sure we are not running out of buffer space by checking
+ * if we can fit the new overlay, a trailing space to be used
+ * as a separator, plus the terminating zero.
+ */
+ if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
+ sizeof(name_overlays))
+ return -ENOMEM;
+
+ /* Append to our list of overlays */
+ strcat(name_overlays, ext_cards[i].dtbo_name);
+ strcat(name_overlays, " ");
+ }
+
+ /* Apply device tree overlay(s) to the U-Boot environment, if any */
+ if (strlen(name_overlays))
+ return env_set("name_overlays", name_overlays);
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_board_eeprom_env();
+ setup_serial();
+
+ /* Check for and probe any plugged-in daughtercards */
+ probe_daughtercards();
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ probe_daughtercards();
+}
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index fdfab8f..8c4af7d 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -90,11 +90,6 @@
return 0;
}
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
-}
-
/*
* Board specific reset that is system reset.
*/
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index 857e9fe..e4d762f 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -102,11 +102,6 @@
return 0;
}
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
-}
-
/*
* Board specific reset that is system reset.
*/
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 6121d78..1dceea5 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -31,13 +31,16 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
@@ -49,7 +52,6 @@
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
@@ -59,6 +61,8 @@
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
@@ -66,8 +70,11 @@
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
+CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_LZO=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index c5202a9..a7d76c8 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -33,13 +33,16 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
@@ -51,7 +54,6 @@
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
@@ -61,6 +63,8 @@
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
@@ -68,8 +72,11 @@
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
+CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_LZO=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index d399ab7..0255bcd 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -9,6 +9,7 @@
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0x403018E0
@@ -41,10 +42,17 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
@@ -54,6 +62,9 @@
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_OMAP_USB2_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
@@ -61,10 +72,13 @@
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_OMAP_USB_PHY=y
CONFIG_USB_GADGET=y
@@ -72,3 +86,4 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 6386157..96025a9 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -16,6 +16,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
+CONFIG_PREBOOT="if $board_name=am5729_beaglebonai; then setenv console ttyS0,115200; fi;"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
@@ -38,7 +39,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_OFFSET_REDUND=0x280000
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index cec99ee..30c1047 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -21,6 +21,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
@@ -32,11 +33,13 @@
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
# CONFIG_ISO_PARTITION is not set
@@ -54,9 +57,12 @@
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -65,10 +71,13 @@
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_KEYBOARD=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_PHY_TI=y
CONFIG_PHY_FIXED=y
@@ -81,6 +90,7 @@
CONFIG_PCI_KEYSTONE=y
CONFIG_PHY=y
CONFIG_AM654_PHY=y
+CONFIG_OMAP_USB2_PHY=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
@@ -96,5 +106,19 @@
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index e7f441e..4247f8d 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -74,6 +74,7 @@
CONFIG_K3_AVS0=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index daa6613..1cc75ce 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -5,10 +5,11 @@
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_ENV_SIZE=0x20000
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_FS_FAT=y
@@ -21,23 +22,30 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
@@ -50,6 +58,9 @@
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0x700000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
@@ -62,14 +73,27 @@
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
@@ -93,6 +117,7 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_RAM=y
CONFIG_REMOTEPROC_TI_K3_DSP=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_DM_RESET=y
@@ -107,7 +132,21 @@
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 10f4f00..cb6c74d 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -6,10 +6,11 @@
CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_ENV_SIZE=0x20000
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -46,6 +47,9 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0x700000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
@@ -69,6 +73,7 @@
CONFIG_K3_AVS0=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig
new file mode 100644
index 0000000..26fbdb8
--- /dev/null
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -0,0 +1,155 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_A72_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0x700000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_HBMC_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
+CONFIG_UFS=y
+CONFIG_CADENCE_UFS=y
+CONFIG_TI_J721E_UFS=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig
new file mode 100644
index 0000000..49d933b
--- /dev/null
+++ b/configs/j721e_hs_evm_r5_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x55000
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x41c00000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_USE_BOOTCOMMAND=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0x700000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_GPIO=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MISC=y
+CONFIG_FS_LOADER=y
+CONFIG_K3_AVS0=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_TPS65941=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index 3cf9015..8c17477 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -19,6 +19,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_NET is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index 1c37d6b..54ff93e 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -17,6 +17,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_NET is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index c7b67f0..aabb438 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -21,7 +21,9 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
+# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP Logic # "
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index 9773464..51c5d44 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -20,7 +20,9 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
+# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_SPL_POWER_SUPPORT is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index f336c38..15925fb 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -20,7 +20,9 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
+# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP Logic # "
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 163bb18..ea8fc37 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -21,7 +21,9 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
+# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_SPL_POWER_SUPPORT is not set
diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig
new file mode 100644
index 0000000..e39c035
--- /dev/null
+++ b/configs/somlabs_visionsom_6ull_defconfig
@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index c85369c..0b646da 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32MP=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x280000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
-CONFIG_TARGET_STM32MP1=y
+CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_ARMV7_VIRT is not set
diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig
index c192d8d..b45462b 100644
--- a/configs/stm32mp15_optee_defconfig
+++ b/configs/stm32mp15_optee_defconfig
@@ -1,7 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32MP=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
-CONFIG_TARGET_STM32MP1=y
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x280000
+CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_STM32MP1_OPTEE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index a846962..5dc530f 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -1,7 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32MP=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
-CONFIG_TARGET_STM32MP1=y
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x280000
+CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index c1542fe..34b49ce 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -26,6 +26,9 @@
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -74,5 +77,11 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Softing"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/doc/git-mailrc b/doc/git-mailrc
index d29416a..be88afc 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -28,6 +28,7 @@
alias jhersh Joe Hershberger <joe.hershberger@ni.com>
alias kevery Kever Yang <kever.yang@rock-chips.com>
alias leyfoon Ley Foon Tan <ley.foon.tan@intel.com>
+alias lokeshvutla Lokesh Vutla <lokeshvutla@ti.com>
alias lukma Lukasz Majewski <lukma@denx.de>
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias marex Marek Vasut <marex@denx.de>
@@ -70,7 +71,7 @@
alias sunxi uboot, jagan, maxime
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
-alias ti uboot, trini
+alias ti uboot, lokeshvutla
alias uniphier uboot, masahiro
alias zynq uboot, monstr
alias rockchip uboot, sjg, kevery, ptomsich
diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/clk-ti-sci.c
index 478349f..ed1facb 100644
--- a/drivers/clk/clk-ti-sci.c
+++ b/drivers/clk/clk-ti-sci.c
@@ -106,8 +106,7 @@
k3_avs_notify_freq(clk->id, clk->data, rate);
#endif
- /* Ask for exact frequency by using same value for min/target/max */
- ret = cops->set_freq(sci, clk->id, clk->data, rate, rate, rate);
+ ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
if (ret)
dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f712861..95f6b5a 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -12,12 +12,14 @@
#include <malloc.h>
#include <asm/dma-mapping.h>
#include <dm.h>
+#include <dm/device.h>
#include <dm/read.h>
#include <dm/of_access.h>
#include <dma.h>
#include <dma-uclass.h>
#include <linux/delay.h>
#include <dt-bindings/dma/k3-udma.h>
+#include <linux/bitmap.h>
#include <linux/soc/ti/k3-navss-ringacc.h>
#include <linux/soc/ti/cppi5.h>
#include <linux/soc/ti/ti-udma.h>
@@ -31,6 +33,8 @@
#define RINGACC_RING_USE_PROXY (1)
#endif
+#define K3_UDMA_MAX_RFLOWS 1024
+
struct udma_chan;
enum udma_mmr {
@@ -64,10 +68,30 @@
int id;
};
+enum udma_rm_range {
+ RM_RANGE_TCHAN = 0,
+ RM_RANGE_RCHAN,
+ RM_RANGE_RFLOW,
+ RM_RANGE_LAST,
+};
+
+struct udma_tisci_rm {
+ const struct ti_sci_handle *tisci;
+ const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
+ u32 tisci_dev_id;
+
+ /* tisci information for PSI-L thread pairing/unpairing */
+ const struct ti_sci_rm_psil_ops *tisci_psil_ops;
+ u32 tisci_navss_dev_id;
+
+ struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
+};
+
struct udma_dev {
- struct device *dev;
+ struct udevice *dev;
void __iomem *mmrs[MMR_LAST];
+ struct udma_tisci_rm tisci_rm;
struct k3_nav_ringacc *ringacc;
u32 features;
@@ -79,6 +103,7 @@
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_map;
+ unsigned long *rflow_map_reserved;
struct udma_tchan *tchans;
struct udma_rchan *rchans;
@@ -88,12 +113,6 @@
u32 psil_base;
u32 ch_count;
- const struct ti_sci_handle *tisci;
- const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
- const struct ti_sci_rm_psil_ops *tisci_psil_ops;
- u32 tisci_dev_id;
- u32 tisci_navss_dev_id;
- bool is_coherent;
};
struct udma_chan {
@@ -203,19 +222,25 @@
static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
u32 dst_thread)
{
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
- return ud->tisci_psil_ops->pair(ud->tisci,
- ud->tisci_navss_dev_id,
- src_thread, dst_thread);
+
+ return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci,
+ tisci_rm->tisci_navss_dev_id,
+ src_thread, dst_thread);
}
static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
u32 dst_thread)
{
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
- return ud->tisci_psil_ops->unpair(ud->tisci,
- ud->tisci_navss_dev_id,
- src_thread, dst_thread);
+
+ return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci,
+ tisci_rm->tisci_navss_dev_id,
+ src_thread, dst_thread);
}
static inline char *udma_get_dir_text(enum dma_direction dir)
@@ -270,11 +295,6 @@
return false;
}
-static int udma_is_coherent(struct udma_chan *uc)
-{
- return uc->ud->is_coherent;
-}
-
static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
{
struct k3_nav_ring *ring = NULL;
@@ -429,9 +449,9 @@
pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
__func__,
- udma_rchanrt_read(uc->rchan,
+ udma_tchanrt_read(uc->tchan,
UDMA_TCHAN_RT_CTL_REG),
- udma_rchanrt_read(uc->rchan,
+ udma_tchanrt_read(uc->tchan,
UDMA_TCHAN_RT_PEER_RT_EN_REG));
break;
case DMA_MEM_TO_MEM:
@@ -538,6 +558,28 @@
}
}
+static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)
+{
+ DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
+
+ if (id >= 0) {
+ if (test_bit(id, ud->rflow_map)) {
+ dev_err(ud->dev, "rflow%d is in use\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+ } else {
+ bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
+ ud->rflow_cnt);
+
+ id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
+ if (id >= ud->rflow_cnt)
+ return ERR_PTR(-ENOENT);
+ }
+
+ __set_bit(id, ud->rflow_map);
+ return &ud->rflows[id];
+}
+
#define UDMA_RESERVE_RESOURCE(res) \
static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
int id) \
@@ -560,7 +602,6 @@
UDMA_RESERVE_RESOURCE(tchan);
UDMA_RESERVE_RESOURCE(rchan);
-UDMA_RESERVE_RESOURCE(rflow);
static int udma_get_tchan(struct udma_chan *uc)
{
@@ -740,7 +781,7 @@
memset(&ring_cfg, 0, sizeof(ring_cfg));
ring_cfg.size = 16;
ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
- ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE;
+ ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
ret = k3_nav_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
ret |= k3_nav_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
@@ -817,7 +858,7 @@
memset(&ring_cfg, 0, sizeof(ring_cfg));
ring_cfg.size = 16;
ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
- ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE;
+ ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
ret = k3_nav_ringacc_ring_cfg(uc->rchan->fd_ring, &ring_cfg);
ret |= k3_nav_ringacc_ring_cfg(uc->rchan->r_ring, &ring_cfg);
@@ -846,6 +887,7 @@
struct udma_dev *ud = uc->ud;
int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
u32 mode;
int ret;
@@ -857,7 +899,7 @@
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID;
- req.nav_id = ud->tisci_dev_id;
+ req.nav_id = tisci_rm->tisci_dev_id;
req.index = uc->tchan->id;
req.tx_chan_type = mode;
if (uc->dir == DMA_MEM_TO_MEM)
@@ -868,7 +910,7 @@
0) >> 2;
req.txcq_qnum = tc_ring;
- ret = ud->tisci_udmap_ops->tx_ch_cfg(ud->tisci, &req);
+ ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
if (ret)
dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
@@ -883,6 +925,7 @@
int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
struct ti_sci_msg_rm_udmap_rx_ch_cfg req = { 0 };
struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
u32 mode;
int ret;
@@ -894,7 +937,7 @@
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID;
- req.nav_id = ud->tisci_dev_id;
+ req.nav_id = tisci_rm->tisci_dev_id;
req.index = uc->rchan->id;
req.rx_chan_type = mode;
if (uc->dir == DMA_MEM_TO_MEM) {
@@ -914,7 +957,7 @@
TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
}
- ret = ud->tisci_udmap_ops->rx_ch_cfg(ud->tisci, &req);
+ ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
if (ret) {
dev_err(ud->dev, "tisci rx %u cfg failed %d\n",
uc->rchan->id, ret);
@@ -939,7 +982,7 @@
TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID;
- flow_req.nav_id = ud->tisci_dev_id;
+ flow_req.nav_id = tisci_rm->tisci_dev_id;
flow_req.flow_index = uc->rflow->id;
if (uc->needs_epib)
@@ -965,7 +1008,8 @@
flow_req.rx_fdq3_qnum = fd_ring;
flow_req.rx_ps_location = 0;
- ret = ud->tisci_udmap_ops->rx_flow_cfg(ud->tisci, &flow_req);
+ ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci,
+ &flow_req);
if (ret)
dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
uc->rchan->id, uc->rflow->id, ret);
@@ -1106,16 +1150,134 @@
return 0;
}
-#define UDMA_MAX_CHANNELS 192
+static int udma_setup_resources(struct udma_dev *ud)
+{
+ struct udevice *dev = ud->dev;
+ int ch_count, i;
+ u32 cap2, cap3;
+ struct ti_sci_resource_desc *rm_desc;
+ struct ti_sci_resource *rm_res;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ static const char * const range_names[] = { "ti,sci-rm-range-tchan",
+ "ti,sci-rm-range-rchan",
+ "ti,sci-rm-range-rflow" };
+ cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
+ cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+
+ ud->rflow_cnt = cap3 & 0x3fff;
+ ud->tchan_cnt = cap2 & 0x1ff;
+ ud->echan_cnt = (cap2 >> 9) & 0x1ff;
+ ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+ ch_count = ud->tchan_cnt + ud->rchan_cnt;
+
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ ud->rflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rflow_map_reserved = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+
+ if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map ||
+ !ud->rflow_map_reserved || !ud->tchans || !ud->rchans ||
+ !ud->rflows)
+ return -ENOMEM;
+
+ /*
+ * RX flows with the same Ids as RX channels are reserved to be used
+ * as default flows if remote HW can't generate flow_ids. Those
+ * RX flows can be requested only explicitly by id.
+ */
+ bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
+
+ /* Get resource ranges from tisci */
+ for (i = 0; i < RM_RANGE_LAST; i++)
+ tisci_rm->rm_ranges[i] =
+ devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
+ tisci_rm->tisci_dev_id,
+ (char *)range_names[i]);
+
+ /* tchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+ } else {
+ bitmap_fill(ud->tchan_map, ud->tchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->tchan_map, rm_desc->start,
+ rm_desc->num);
+ }
+ }
+
+ /* rchan and matching default flow ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ bitmap_zero(ud->rflow_map, ud->rchan_cnt);
+ } else {
+ bitmap_fill(ud->rchan_map, ud->rchan_cnt);
+ bitmap_fill(ud->rflow_map, ud->rchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rchan_map, rm_desc->start,
+ rm_desc->num);
+ bitmap_clear(ud->rflow_map, rm_desc->start,
+ rm_desc->num);
+ }
+ }
+
+ /* GP rflow ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
+ if (IS_ERR(rm_res)) {
+ bitmap_clear(ud->rflow_map, ud->rchan_cnt,
+ ud->rflow_cnt - ud->rchan_cnt);
+ } else {
+ bitmap_set(ud->rflow_map, ud->rchan_cnt,
+ ud->rflow_cnt - ud->rchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rflow_map, rm_desc->start,
+ rm_desc->num);
+ }
+ }
+
+ ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
+ ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
+ if (!ch_count)
+ return -ENODEV;
+
+ ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
+ GFP_KERNEL);
+ if (!ud->channels)
+ return -ENOMEM;
+
+ dev_info(dev,
+ "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n",
+ ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
+ ud->rflow_cnt);
+
+ return ch_count;
+}
static int udma_probe(struct udevice *dev)
{
struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct udma_dev *ud = dev_get_priv(dev);
int i, ret;
- u32 cap2, cap3;
struct udevice *tmp;
struct udevice *tisci_dev = NULL;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
+
ret = udma_get_mmrs(dev);
if (ret)
@@ -1134,79 +1296,45 @@
return -EINVAL;
}
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev);
+ ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
+ "ti,sci", &tisci_dev);
if (ret) {
- debug("TISCI RA RM get failed (%d)\n", ret);
- ud->tisci = NULL;
- return 0;
+ debug("Failed to get TISCI phandle (%d)\n", ret);
+ tisci_rm->tisci = NULL;
+ return -EINVAL;
}
- ud->tisci = (struct ti_sci_handle *)
- (ti_sci_get_handle_from_sysfw(tisci_dev));
+ tisci_rm->tisci = (struct ti_sci_handle *)
+ (ti_sci_get_handle_from_sysfw(tisci_dev));
- ret = dev_read_u32_default(dev, "ti,sci", 0);
- if (!ret) {
- dev_err(dev, "TISCI RA RM disabled\n");
- ud->tisci = NULL;
+ tisci_rm->tisci_dev_id = -1;
+ ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
+ if (ret) {
+ dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
+ return ret;
}
- if (ud->tisci) {
- ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
-
- ud->tisci_dev_id = -1;
- ret = dev_read_u32(dev, "ti,sci-dev-id", &ud->tisci_dev_id);
- if (ret) {
- dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
- return ret;
- }
-
- ud->tisci_navss_dev_id = -1;
- ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
- &ud->tisci_navss_dev_id);
- if (ret) {
- dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
- return ret;
- }
-
- ud->tisci_udmap_ops = &ud->tisci->ops.rm_udmap_ops;
- ud->tisci_psil_ops = &ud->tisci->ops.rm_psil_ops;
+ tisci_rm->tisci_navss_dev_id = -1;
+ ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
+ &tisci_rm->tisci_navss_dev_id);
+ if (ret) {
+ dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
+ return ret;
}
- ud->is_coherent = dev_read_bool(dev, "dma-coherent");
+ tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
+ tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
- cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
- cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
-
- ud->rflow_cnt = cap3 & 0x3fff;
- ud->tchan_cnt = cap2 & 0x1ff;
- ud->echan_cnt = (cap2 >> 9) & 0x1ff;
- ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
- ud->ch_count = ud->tchan_cnt + ud->rchan_cnt;
+ ud->dev = dev;
+ ud->ch_count = udma_setup_resources(ud);
+ if (ud->ch_count <= 0)
+ return ud->ch_count;
dev_info(dev,
"Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
- ud->tisci_dev_id);
+ tisci_rm->tisci_dev_id);
dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
- ud->channels = devm_kcalloc(dev, ud->ch_count, sizeof(*ud->channels),
- GFP_KERNEL);
- ud->tchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->tchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->tchans = devm_kcalloc(dev, ud->tchan_cnt,
- sizeof(*ud->tchans), GFP_KERNEL);
- ud->rchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt,
- sizeof(*ud->rchans), GFP_KERNEL);
- ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rflows = devm_kcalloc(dev, ud->rflow_cnt,
- sizeof(*ud->rflows), GFP_KERNEL);
-
- if (!ud->channels || !ud->tchan_map || !ud->rchan_map ||
- !ud->rflow_map || !ud->tchans || !ud->rchans || !ud->rflows)
- return -ENOMEM;
-
for (i = 0; i < ud->tchan_cnt; i++) {
struct udma_tchan *tchan = &ud->tchans[i];
@@ -1253,6 +1381,14 @@
return ret;
}
+static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem)
+{
+ u64 addr = 0;
+
+ memcpy(&addr, &elem, sizeof(elem));
+ return k3_nav_ringacc_ring_push(ring, &addr);
+}
+
static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
dma_addr_t src, size_t len)
{
@@ -1340,13 +1476,11 @@
cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
- if (!udma_is_coherent(uc)) {
- flush_dcache_range((u64)tr_desc,
- ALIGN((u64)tr_desc + desc_size,
- ARCH_DMA_MINALIGN));
- }
+ flush_dcache_range((unsigned long)tr_desc,
+ ALIGN((unsigned long)tr_desc + desc_size,
+ ARCH_DMA_MINALIGN));
- k3_nav_ringacc_ring_push(uc->tchan->t_ring, &tr_desc);
+ udma_push_to_ring(uc->tchan->t_ring, tr_desc);
return 0;
}
@@ -1514,16 +1648,14 @@
cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
- if (!udma_is_coherent(uc)) {
- flush_dcache_range((u64)dma_src,
- ALIGN((u64)dma_src + len,
- ARCH_DMA_MINALIGN));
- flush_dcache_range((u64)desc_tx,
- ALIGN((u64)desc_tx + uc->hdesc_size,
- ARCH_DMA_MINALIGN));
- }
+ flush_dcache_range((unsigned long)dma_src,
+ ALIGN((unsigned long)dma_src + len,
+ ARCH_DMA_MINALIGN));
+ flush_dcache_range((unsigned long)desc_tx,
+ ALIGN((unsigned long)desc_tx + uc->hdesc_size,
+ ARCH_DMA_MINALIGN));
- ret = k3_nav_ringacc_ring_push(uc->tchan->t_ring, &uc->desc_tx);
+ ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx);
if (ret) {
dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
dma->id, ret);
@@ -1565,19 +1697,15 @@
}
/* invalidate cache data */
- if (!udma_is_coherent(uc)) {
- invalidate_dcache_range((ulong)desc_rx,
- (ulong)(desc_rx + uc->hdesc_size));
- }
+ invalidate_dcache_range((ulong)desc_rx,
+ (ulong)(desc_rx + uc->hdesc_size));
cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
/* invalidate cache data */
- if (!udma_is_coherent(uc)) {
- invalidate_dcache_range((ulong)buf_dma,
- (ulong)(buf_dma + buf_dma_len));
- }
+ invalidate_dcache_range((ulong)buf_dma,
+ (ulong)(buf_dma + buf_dma_len));
cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
@@ -1682,13 +1810,11 @@
cppi5_hdesc_set_pktlen(desc_rx, size);
cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
- if (!udma_is_coherent(uc)) {
- flush_dcache_range((u64)desc_rx,
- ALIGN((u64)desc_rx + uc->hdesc_size,
- ARCH_DMA_MINALIGN));
- }
+ flush_dcache_range((unsigned long)desc_rx,
+ ALIGN((unsigned long)desc_rx + uc->hdesc_size,
+ ARCH_DMA_MINALIGN));
- k3_nav_ringacc_ring_push(uc->rchan->fd_ring, &desc_rx);
+ udma_push_to_ring(uc->rchan->fd_ring, desc_rx);
uc->num_rx_bufs++;
uc->desc_rx_cur++;
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 7cd5516..41a9083 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -36,11 +36,14 @@
#define OTAPDLYSEL_SHIFT 12
#define OTAPDLYSEL_MASK GENMASK(15, 12)
#define STRBSEL_SHIFT 24
-#define STRBSEL_MASK GENMASK(27, 24)
+#define STRBSEL_4BIT_MASK GENMASK(27, 24)
+#define STRBSEL_8BIT_MASK GENMASK(31, 24)
#define SEL50_SHIFT 8
#define SEL50_MASK BIT(SEL50_SHIFT)
#define SEL100_SHIFT 9
#define SEL100_MASK BIT(SEL100_SHIFT)
+#define FREQSEL_SHIFT 8
+#define FREQSEL_MASK GENMASK(10, 8)
#define DLL_TRIM_ICP_SHIFT 4
#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
#define DR_TY_SHIFT 20
@@ -72,11 +75,20 @@
u32 otap_del_sel;
u32 trm_icp;
u32 drv_strength;
+ u32 strb_sel;
u32 flags;
#define DLL_PRESENT (1 << 0)
+#define IOMUX_PRESENT (1 << 1)
+#define FREQSEL_2_BIT (1 << 2)
+#define STRBSEL_4_BIT (1 << 3)
bool dll_on;
};
+struct am654_driver_data {
+ const struct sdhci_ops *ops;
+ u32 flags;
+};
+
static void am654_sdhci_set_control_reg(struct sdhci_host *host)
{
struct mmc *mmc = (struct mmc *)host->mmc;
@@ -97,7 +109,7 @@
struct udevice *dev = host->mmc->dev;
struct am654_sdhci_plat *plat = dev_get_platdata(dev);
unsigned int speed = host->mmc->clock;
- int sel50, sel100;
+ int sel50, sel100, freqsel;
u32 mask, val;
int ret;
@@ -121,25 +133,49 @@
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
val = (1 << OTAPDLYENA_SHIFT) |
(plat->otap_del_sel << OTAPDLYSEL_SHIFT);
- regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
- switch (speed) {
- case 200000000:
- sel50 = 0;
- sel100 = 0;
- break;
- case 100000000:
- sel50 = 0;
- sel100 = 1;
- break;
- default:
- sel50 = 1;
- sel100 = 0;
+
+ /* Write to STRBSEL for HS400 speed mode */
+ if (host->mmc->selected_mode == MMC_HS_400) {
+ if (plat->flags & STRBSEL_4_BIT)
+ mask |= STRBSEL_4BIT_MASK;
+ else
+ mask |= STRBSEL_8BIT_MASK;
+
+ val |= plat->strb_sel << STRBSEL_SHIFT;
}
- /* Configure PHY DLL frequency */
- mask = SEL50_MASK | SEL100_MASK;
- val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
- regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
+ regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+
+ if (plat->flags & FREQSEL_2_BIT) {
+ switch (speed) {
+ case 200000000:
+ sel50 = 0;
+ sel100 = 0;
+ break;
+ case 100000000:
+ sel50 = 0;
+ sel100 = 1;
+ break;
+ default:
+ sel50 = 1;
+ sel100 = 0;
+ }
+
+ /* Configure PHY DLL frequency */
+ mask = SEL50_MASK | SEL100_MASK;
+ val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
+ regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
+ } else {
+ switch (speed) {
+ case 200000000:
+ freqsel = 0x0;
+ break;
+ default:
+ freqsel = 0x4;
+ }
+ regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
+ freqsel << FREQSEL_SHIFT);
+ }
/* Enable DLL */
regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
@@ -164,8 +200,37 @@
.set_control_reg = &am654_sdhci_set_control_reg,
};
+const struct am654_driver_data am654_drv_data = {
+ .ops = &am654_sdhci_ops,
+ .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
+};
+
+const struct am654_driver_data j721e_8bit_drv_data = {
+ .ops = &am654_sdhci_ops,
+ .flags = DLL_PRESENT,
+};
+
+static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
+{
+ struct udevice *dev = host->mmc->dev;
+ struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ u32 mask, val;
+
+ mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
+ val = (1 << OTAPDLYENA_SHIFT) |
+ (plat->otap_del_sel << OTAPDLYSEL_SHIFT);
+ regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+
+ return 0;
+}
+
const struct sdhci_ops j721e_4bit_sdhci_ops = {
- .set_control_reg = &am654_sdhci_set_control_reg,
+ .set_ios_post = &j721e_4bit_sdhci_set_ios_post,
+};
+
+const struct am654_driver_data j721e_4bit_drv_data = {
+ .ops = &j721e_4bit_sdhci_ops,
+ .flags = IOMUX_PRESENT,
};
int am654_sdhci_init(struct am654_sdhci_plat *plat)
@@ -202,7 +267,8 @@
}
/* Enable pins by setting IO mux to 0 */
- regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
+ if (plat->flags & IOMUX_PRESENT)
+ regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
/* Set slot type based on SD or eMMC */
if (plat->non_removable)
@@ -215,6 +281,8 @@
static int am654_sdhci_probe(struct udevice *dev)
{
+ struct am654_driver_data *drv_data =
+ (struct am654_driver_data *)dev_get_driver_data(dev);
struct am654_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
@@ -223,7 +291,7 @@
unsigned long clock;
int ret;
- ret = clk_get_by_index(dev, 0, &clk);
+ ret = clk_get_by_name(dev, "clk_xin", &clk);
if (ret) {
dev_err(dev, "failed to get clock\n");
return ret;
@@ -242,7 +310,8 @@
AM654_SDHCI_MIN_FREQ);
if (ret)
return ret;
- host->ops = (struct sdhci_ops *)dev_get_driver_data(dev);
+
+ host->ops = drv_data->ops;
host->mmc->priv = host;
upriv->mmc = host->mmc;
@@ -265,10 +334,6 @@
host->ioaddr = (void *)dev_read_addr(dev);
plat->non_removable = dev_read_bool(dev, "non-removable");
- if (device_is_compatible(dev, "ti,am654-sdhci-5.1") ||
- device_is_compatible(dev, "ti,j721e-sdhci-8bit"))
- plat->flags |= DLL_PRESENT;
-
ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
if (ret)
return ret;
@@ -314,23 +379,27 @@
static int am654_sdhci_bind(struct udevice *dev)
{
+ struct am654_driver_data *drv_data =
+ (struct am654_driver_data *)dev_get_driver_data(dev);
struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ plat->flags = drv_data->flags;
+
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id am654_sdhci_ids[] = {
{
.compatible = "ti,am654-sdhci-5.1",
- .data = (ulong)&am654_sdhci_ops,
+ .data = (ulong)&am654_drv_data,
},
{
.compatible = "ti,j721e-sdhci-8bit",
- .data = (ulong)&am654_sdhci_ops,
+ .data = (ulong)&j721e_8bit_drv_data,
},
{
.compatible = "ti,j721e-sdhci-4bit",
- .data = (ulong)&j721e_4bit_sdhci_ops,
+ .data = (ulong)&j721e_4bit_drv_data,
},
{ }
};
diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c
index be3bb0d..923f2c1 100644
--- a/drivers/phy/omap-usb2-phy.c
+++ b/drivers/phy/omap-usb2-phy.c
@@ -27,6 +27,10 @@
#define USB2PHY_DISCON_BYP_LATCH BIT(31)
#define USB2PHY_ANA_CONFIG1 (0x4c)
+#define AM654_USB2_OTG_PD BIT(8)
+#define AM654_USB2_VBUS_DET_EN BIT(5)
+#define AM654_USB2_VBUSVALID_DET_EN BIT(4)
+
DECLARE_GLOBAL_DATA_PTR;
struct omap_usb2_phy {
@@ -74,6 +78,15 @@
.power_off = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD,
};
+static const struct usb_phy_data am654_usb2_data = {
+ .label = "am654_usb2",
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .mask = AM654_USB2_OTG_PD | AM654_USB2_VBUS_DET_EN |
+ AM654_USB2_VBUSVALID_DET_EN,
+ .power_on = AM654_USB2_VBUS_DET_EN | AM654_USB2_VBUSVALID_DET_EN,
+ .power_off = AM654_USB2_OTG_PD,
+};
+
static const struct udevice_id omap_usb2_id_table[] = {
{
.compatible = "ti,omap5-usb2",
@@ -91,6 +104,10 @@
.compatible = "ti,am437x-usb2",
.data = (ulong)&am437x_usb2_data,
},
+ {
+ .compatible = "ti,am654-usb2",
+ .data = (ulong)&am654_usb2_data,
+ },
{},
};
@@ -179,11 +196,10 @@
return -EINVAL;
if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
- u32 base = dev_read_addr(dev);
+ priv->phy_base = dev_read_addr_ptr(dev);
- if (base == FDT_ADDR_T_NONE)
+ if (!priv->phy_base)
return -EINVAL;
- priv->phy_base = (void *)base;
priv->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
}
diff --git a/drivers/power/regulator/tps62360_regulator.c b/drivers/power/regulator/tps62360_regulator.c
index 3b123f5..2c076c0 100644
--- a/drivers/power/regulator/tps62360_regulator.c
+++ b/drivers/power/regulator/tps62360_regulator.c
@@ -77,7 +77,7 @@
return (u32)regval * TPS62360_VSEL_STEPSIZE + pdata->config->vmin;
}
-static int tps62360_regulator_ofdata_to_platdata(struct udevice *dev)
+static int tps62360_regulator_probe(struct udevice *dev)
{
struct tps62360_regulator_pdata *pdata = dev_get_platdata(dev);
u8 vsel0;
@@ -119,5 +119,5 @@
.ops = &tps62360_regulator_ops,
.of_match = tps62360_regulator_ids,
.platdata_auto_alloc_size = sizeof(struct tps62360_regulator_pdata),
- .ofdata_to_platdata = tps62360_regulator_ofdata_to_platdata,
+ .probe = tps62360_regulator_probe,
};
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index 64ebc0b..17949d2 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <cpu_func.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/dma-mapping.h>
@@ -807,6 +808,11 @@
memcpy(elem_ptr, elem, (4 << ring->elm_size));
+ flush_dcache_range((unsigned long)ring->ring_mem_virt,
+ ALIGN((unsigned long)ring->ring_mem_virt +
+ ring->size * (4 << ring->elm_size),
+ ARCH_DMA_MINALIGN));
+
ring->windex = (ring->windex + 1) % ring->size;
ring->free--;
ringacc_writel(1, &ring->rt->db);
@@ -823,6 +829,11 @@
elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->rindex);
+ invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
+ ALIGN((unsigned long)ring->ring_mem_virt +
+ ring->size * (4 << ring->elm_size),
+ ARCH_DMA_MINALIGN));
+
memcpy(elem, elem_ptr, (4 << ring->elm_size));
ring->rindex = (ring->rindex + 1) % ring->size;
@@ -931,7 +942,8 @@
ringacc->dma_ring_reset_quirk =
dev_read_bool(dev, "ti,dma-ring-reset-quirk");
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev);
+ ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
+ "ti,sci", &tisci_dev);
if (ret) {
pr_debug("TISCI RA RM get failed (%d)\n", ret);
ringacc->tisci = NULL;
diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c
index b490391..8b332f1 100644
--- a/drivers/thermal/ti-bandgap.c
+++ b/drivers/thermal/ti-bandgap.c
@@ -26,7 +26,7 @@
struct ti_bandgap {
ulong base;
- int temperature; /* in mili degree celsius */
+ uint adc_val;
};
/*
@@ -162,8 +162,8 @@
{
struct ti_bandgap *bgp = dev_get_priv(dev);
- bgp->temperature = 0x3ff & readl(bgp->base + CTRL_CORE_TEMP_SENSOR_MPU);
- *temp = dra752_adc_to_temp[bgp->temperature - DRA752_ADC_START_VALUE];
+ bgp->adc_val = 0x3ff & readl(bgp->base + CTRL_CORE_TEMP_SENSOR_MPU);
+ *temp = dra752_adc_to_temp[bgp->adc_val - DRA752_ADC_START_VALUE];
return 0;
}
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 8d45748..3e116b2 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -426,6 +426,7 @@
{ .compatible = "ti,keystone-dwc3"},
{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
+ { .compatible = "ti,am654-dwc3" },
{ }
};
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index cdab924..fea9300 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -22,7 +22,6 @@
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-#define CONSOLEDEV "ttyS2"
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
@@ -33,7 +32,6 @@
#define CONFIG_SYS_OMAP_ABE_SYSCK
-#ifdef CONFIG_SPL_DFU
#ifndef CONFIG_SPL_BUILD
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
@@ -43,6 +41,7 @@
DFU_ALT_INFO_QSPI
#else
#undef CONFIG_CMD_BOOTD
+#ifdef CONFIG_SPL_DFU
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 06be7cc..7d7f86a 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -13,6 +13,7 @@
#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
#include <environment/ti/k3_rproc.h>
+#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
@@ -71,6 +72,7 @@
"overlayaddr=0x83000000\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
+ "stdin=serial,usbkbd\0" \
"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
@@ -104,13 +106,20 @@
"0 /lib/firmware/am65x-mcu-r5f0_0-fw " \
"1 /lib/firmware/am65x-mcu-r5f0_1-fw "
+#define EXTRA_ENV_DFUARGS \
+ "dfu_bufsiz=0x20000\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_EMMC \
+ DFU_ALT_INFO_OSPI
+
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \
- EXTRA_ENV_RPROC_SETTINGS
+ EXTRA_ENV_RPROC_SETTINGS \
+ EXTRA_ENV_DFUARGS
/* MMC ENV related defines */
#ifdef CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 8451878..eaed520 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -14,6 +14,7 @@
#include <environment/ti/mmc.h>
#include <environment/ti/k3_rproc.h>
#include <environment/ti/ufs.h>
+#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
@@ -61,7 +62,9 @@
/* U-Boot general configuration */
#define EXTRA_ENV_J721E_BOARD_SETTINGS \
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "findfdt=setenv fdtfile ${default_device_tree}\0" \
+ "findfdt=" \
+ "setenv name_fdt ${default_device_tree};" \
+ "setenv fdtfile ${name_fdt}\0" \
"loadaddr=0x80080000\0" \
"fdtaddr=0x82000000\0" \
"overlayaddr=0x83000000\0" \
@@ -70,6 +73,11 @@
"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+#define PARTS_DEFAULT \
+ /* Linux partitions */ \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
/* U-Boot MMC-specific configuration */
#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
"boot=mmc\0" \
@@ -78,7 +86,7 @@
"bootdir=/boot\0" \
"rd_spec=-\0" \
"init_mmc=run args_all args_mmc\0" \
- "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
"get_overlay_mmc=" \
"fdt address ${fdtaddr};" \
"fdt resize 0x100000;" \
@@ -87,8 +95,12 @@
"load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \
"fdt apply ${overlayaddr};" \
"done;\0" \
+ "partitions=" PARTS_DEFAULT \
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
- "${bootdir}/${name_kern}\0"
+ "${bootdir}/${name_kern}\0" \
+ "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
+ "${bootdir}/${name_fit}\0" \
+ "partitions=" PARTS_DEFAULT
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
@@ -100,15 +112,31 @@
"7 /lib/firmware/j7-c66_1-fw " \
"8 /lib/firmware/j7-c71_0-fw "
+/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
+#define EXTRA_ENV_DFUARGS \
+ "dfu_bufsiz=0x20000\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_EMMC \
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_OSPI
+
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_J721E_BOARD_SETTINGS \
EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
EXTRA_ENV_RPROC_SETTINGS \
+ EXTRA_ENV_DFUARGS \
DEFAULT_UFS_TI_ARGS
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
+/* MMC ENV related defines */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
#endif /* __CONFIG_J721E_EVM_H */
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index cdc1a48..c1b379b 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -14,13 +14,6 @@
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_SYS_BOOTM_LEN 0x1000000
-#define SRC_BASE_ADDR CMC1_RBASE
-#define IRAM_BASE_ADDR OCRAM_0_BASE
-#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
-
-#define CONFIG_SYS_FSL_USDHC_NUM 1
-
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
new file mode 100644
index 0000000..6759f24
--- /dev/null
+++ b/include/configs/somlabs_visionsom_6ull.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017-2019 A. Karas, SomLabs
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the SoMlabs VisionSOM 6ULL board.
+ */
+#ifndef __SOMLABS_VISIONSOM_6ULL_H
+#define __SOMLABS_VISIONSOM_6ULL_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/mach-imx/gpio.h>
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#endif /* CONFIG_FSL_USDHC */
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
+ "console=ttymxc0\0" \
+ "initrd_addr=0x86800000\0" \
+ "fdt_addr=0x83000000\0" \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "splashimage=0x80000000\0" \
+ "splashfile=/boot/splash.bmp\0" \
+ "mmcdev=1\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk1p1 rootwait rw\0" \
+ "setrootmmc=setenv rootspec root=${mmcroot}\0" \
+ "setbootscriptmmc=setenv loadbootscript " \
+ "load mmc ${mmcdev}:${mmcpart} " \
+ "${loadaddr} /boot/${script};\0" \
+ "setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \
+ "${loadaddr} /boot/${image}; " \
+ "setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \
+ "${fdt_addr} /boot/${fdt_file};\0" \
+ "setbootargs=setenv bootargs console=${console},${baudrate} " \
+ "${rootspec}\0" \
+ "execbootscript=echo Running bootscript...; source\0" \
+ "setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \
+ "checkbootdev=run setbootscriptmmc; " \
+ "run setrootmmc; " \
+ "run setloadmmc; " \
+
+#define CONFIG_BOOTCOMMAND \
+ "run setfdtfile; " \
+ "run checkbootdev; " \
+ "run loadfdt;" \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run setbootargs; " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "fi; " \
+ "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "eth0"
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#endif
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index d42a786..a66534e 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -33,9 +33,10 @@
#define CONFIG_SYS_CBSIZE SZ_1K
/*
- * Needed by "loadb"
+ * default load address used for command tftp, bootm , loadb, ...
*/
-#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE
+#define CONFIG_LOADADDR 0xc2000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* ATAGs */
#define CONFIG_CMDLINE_TAG
@@ -98,12 +99,34 @@
#if !defined(CONFIG_SPL_BUILD)
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 1) \
- func(UBIFS, ubifs, 0) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 2) \
- func(PXE, pxe, na)
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
+#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
+#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2)
+#else
+#define BOOT_TARGET_MMC0(func)
+#define BOOT_TARGET_MMC1(func)
+#define BOOT_TARGET_MMC2(func)
+#endif
+
+#ifdef CONFIG_NET
+#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0)
+#else
+#define BOOT_TARGET_UBIFS(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_MMC1(func) \
+ BOOT_TARGET_UBIFS(func) \
+ BOOT_TARGET_MMC0(func) \
+ BOOT_TARGET_MMC2(func) \
+ BOOT_TARGET_PXE(func)
/*
* bootcmd for stm32mp1:
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index adc7861..a1a053e 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -61,7 +61,6 @@
"setenv overlaystring ${overlaystring}'#'${overlay};" \
"done;\0" \
"run_fit=bootm ${addr_fit}#${fdtfile}${overlaystring}\0" \
- "loadfit=run args_mmc; run run_fit;\0" \
/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 0c0baf2..61d9c62 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -66,12 +66,10 @@
#define CONFIG_PHY_ATHEROS
-#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#endif
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index 684a744..6313f3e 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -185,6 +185,8 @@
"setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \
"if test $board_name = beagle_x15_revc; then " \
"setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
+ "if test $board_name = am5729_beagleboneai; then " \
+ "setenv fdtfile am5729-beagleboneai.dtb; fi;" \
"if test $board_name = am572x_idk; then " \
"setenv fdtfile am572x-idk.dtb; fi;" \
"if test $board_name = am574x_idk; then " \
diff --git a/include/environment/ti/k3_dfu.h b/include/environment/ti/k3_dfu.h
new file mode 100644
index 0000000..2f503b8
--- /dev/null
+++ b/include/environment/ti/k3_dfu.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for DFU on TI K3 SoCs.
+ *
+ */
+
+#ifndef __TI_DFU_H
+#define __TI_DFU_H
+
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 1 1;" \
+ "rootfs part 1 2;" \
+ "tiboot3.bin fat 1 1;" \
+ "tispl.bin fat 1 1;" \
+ "u-boot.img fat 1 1;" \
+ "uEnv.txt fat 1 1;" \
+ "sysfw.itb fat 1 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+ "dfu_alt_info_emmc=" \
+ "rawemmc raw 0 0x800000 mmcpart 1;" \
+ "rootfs part 0 1 mmcpart 0;" \
+ "tiboot3.bin.raw raw 0x0 0x400 mmcpart 1;" \
+ "tispl.bin.raw raw 0x400 0x1000 mmcpart 1;" \
+ "u-boot.img.raw raw 0x1400 0x2000 mmcpart 1;" \
+ "u-env.raw raw 0x3400 0x100 mmcpart 1;" \
+ "sysfw.itb.raw raw 0x3600 0x800 mmcpart 1\0"
+
+#define DFU_ALT_INFO_OSPI \
+ "dfu_alt_info_ospi=" \
+ "tiboot3.bin raw 0x0 0x080000;" \
+ "tispl.bin raw 0x080000 0x200000;" \
+ "u-boot.img raw 0x280000 0x400000;" \
+ "u-boot-env raw 0x680000 0x020000;" \
+ "sysfw.itb raw 0x6c0000 0x100000;" \
+ "rootfs raw 0x800000 0x3800000\0"
+
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "tispl.bin ram 0x80080000 0x100000;" \
+ "u-boot.img ram 0x81000000 0x100000\0" \
+
+#endif /* __TI_DFU_H */
diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
index bb4af0a..1c8e49a 100644
--- a/include/environment/ti/mmc.h
+++ b/include/environment/ti/mmc.h
@@ -41,7 +41,7 @@
"fi;" \
"fi;" \
"fi;\0" \
- "mmcloados=run args_mmc; " \
+ "mmcloados=" \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdtaddr}; " \
@@ -61,8 +61,9 @@
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadimage; then " \
+ "run args_mmc; " \
"if test ${boot_fit} -eq 1; then " \
- "run loadfit; " \
+ "run run_fit; " \
"else " \
"run mmcloados;" \
"fi;" \
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c7b3ffc..06951fc 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -212,7 +212,7 @@
/* ESBC global structure.
* Data to be used across verification of different images.
- * Stores follwoing Data:
+ * Stores following Data:
* IE Table
*/
struct fsl_secboot_glb {
diff --git a/include/imximage.h b/include/imximage.h
index ace5cf8..1ed3284 100644
--- a/include/imximage.h
+++ b/include/imximage.h
@@ -73,7 +73,7 @@
CMD_CHECK_BITS_CLR,
CMD_CSF,
CMD_PLUGIN,
- /* Follwoing on i.MX8MQ/MM */
+ /* Following on i.MX8MQ/MM */
CMD_FIT,
CMD_SIGNED_HDMI,
CMD_LOADER,
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index fbbb67c..dae4225 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -5,10 +5,88 @@
#include <asm/types.h>
#include <linux/types.h>
#include <linux/bitops.h>
+#include <linux/string.h>
+#ifdef __LITTLE_ENDIAN
+#define BITMAP_MEM_ALIGNMENT 8
+#else
+#define BITMAP_MEM_ALIGNMENT (8 * sizeof(unsigned long))
+#endif
+#define BITMAP_MEM_MASK (BITMAP_MEM_ALIGNMENT - 1)
+
+#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1)))
+#define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1)))
#define small_const_nbits(nbits) \
(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
+static inline void
+__bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
+ const unsigned long *bitmap2, unsigned int bits)
+{
+ unsigned int k;
+ unsigned int nr = BITS_TO_LONGS(bits);
+
+ for (k = 0; k < nr; k++)
+ dst[k] = bitmap1[k] | bitmap2[k];
+}
+
+static inline int
+__bitmap_weight(const unsigned long *bitmap, unsigned int bits)
+{
+ unsigned int k, lim = bits / BITS_PER_LONG;
+ int w = 0;
+
+ for (k = 0; k < lim; k++)
+ w += hweight_long(bitmap[k]);
+
+ if (bits % BITS_PER_LONG)
+ w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits));
+
+ return w;
+}
+
+static inline void
+__bitmap_set(unsigned long *map, unsigned int start, int len)
+{
+ unsigned long *p = map + BIT_WORD(start);
+ const unsigned int size = start + len;
+ int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG);
+ unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start);
+
+ while (len - bits_to_set >= 0) {
+ *p |= mask_to_set;
+ len -= bits_to_set;
+ bits_to_set = BITS_PER_LONG;
+ mask_to_set = ~0UL;
+ p++;
+ }
+ if (len) {
+ mask_to_set &= BITMAP_LAST_WORD_MASK(size);
+ *p |= mask_to_set;
+ }
+}
+
+static inline void
+__bitmap_clear(unsigned long *map, unsigned int start, int len)
+{
+ unsigned long *p = map + BIT_WORD(start);
+ const unsigned int size = start + len;
+ int bits_to_clear = BITS_PER_LONG - (start % BITS_PER_LONG);
+ unsigned long mask_to_clear = BITMAP_FIRST_WORD_MASK(start);
+
+ while (len - bits_to_clear >= 0) {
+ *p &= ~mask_to_clear;
+ len -= bits_to_clear;
+ bits_to_clear = BITS_PER_LONG;
+ mask_to_clear = ~0UL;
+ p++;
+ }
+ if (len) {
+ mask_to_clear &= BITMAP_LAST_WORD_MASK(size);
+ *p &= ~mask_to_clear;
+ }
+}
+
static inline void bitmap_zero(unsigned long *dst, int nbits)
{
if (small_const_nbits(nbits)) {
@@ -81,4 +159,59 @@
(bit) < (size); \
(bit) = find_next_bit((addr), (size), (bit) + 1))
+static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
+{
+ if (small_const_nbits(nbits)) {
+ *dst = ~0UL;
+ } else {
+ unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
+
+ memset(dst, 0xff, len);
+ }
+}
+
+static inline void bitmap_or(unsigned long *dst, const unsigned long *src1,
+ const unsigned long *src2, unsigned int nbits)
+{
+ if (small_const_nbits(nbits))
+ *dst = *src1 | *src2;
+ else
+ __bitmap_or(dst, src1, src2, nbits);
+}
+
+static inline int bitmap_weight(const unsigned long *src, unsigned int nbits)
+{
+ if (small_const_nbits(nbits))
+ return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits));
+ return __bitmap_weight(src, nbits);
+}
+
+static inline void bitmap_set(unsigned long *map, unsigned int start,
+ unsigned int nbits)
+{
+ if (__builtin_constant_p(nbits) && nbits == 1)
+ __set_bit(start, map);
+ else if (__builtin_constant_p(start & BITMAP_MEM_MASK) &&
+ IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) &&
+ __builtin_constant_p(nbits & BITMAP_MEM_MASK) &&
+ IS_ALIGNED(nbits, BITMAP_MEM_ALIGNMENT))
+ memset((char *)map + start / 8, 0xff, nbits / 8);
+ else
+ __bitmap_set(map, start, nbits);
+}
+
+static inline void bitmap_clear(unsigned long *map, unsigned int start,
+ unsigned int nbits)
+{
+ if (__builtin_constant_p(nbits) && nbits == 1)
+ __clear_bit(start, map);
+ else if (__builtin_constant_p(start & BITMAP_MEM_MASK) &&
+ IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) &&
+ __builtin_constant_p(nbits & BITMAP_MEM_MASK) &&
+ IS_ALIGNED(nbits, BITMAP_MEM_ALIGNMENT))
+ memset((char *)map + start / 8, 0, nbits / 8);
+ else
+ __bitmap_clear(map, start, nbits);
+}
+
#endif /* __LINUX_BITMAP_H */
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 259df43..a07c70f 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -4,6 +4,7 @@
#include <asm/types.h>
#include <asm-generic/bitsperlong.h>
#include <linux/compiler.h>
+#include <linux/kernel.h>
#ifdef __KERNEL__
#define BIT(nr) (1UL << (nr))
@@ -133,6 +134,17 @@
return (res & 0x0F) + ((res >> 4) & 0x0F);
}
+static inline unsigned long generic_hweight64(__u64 w)
+{
+ return generic_hweight32((unsigned int)(w >> 32)) +
+ generic_hweight32((unsigned int)w);
+}
+
+static inline unsigned long hweight_long(unsigned long w)
+{
+ return sizeof(w) == 4 ? generic_hweight32(w) : generic_hweight64(w);
+}
+
#include <asm/bitops.h>
/* linux/include/asm-generic/bitops/non-atomic.h */
diff --git a/include/spl.h b/include/spl.h
index cd4669f..6087cd7 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -269,6 +269,7 @@
void spl_board_prepare_for_linux(void);
void spl_board_prepare_for_boot(void);
int spl_board_ubi_load_image(u32 boot_device);
+int spl_board_boot_device(u32 boot_device);
/**
* jump_to_image_linux() - Jump to a Linux kernel from SPL