ppc4xx: Correct UART input clock calculation and passing to fdt
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 8b1e2ff..0fdef7e 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -528,12 +528,18 @@
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+ gd->freqUART = CFG_EXT_SERIAL_CLOCK;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
* values that are subject to the 1/2 opb clock constraint
*/
serial_divs (gd->baudrate, &udiv, &bdiv);
+
+ /* Correct UART frequency in bd-info struct now that
+ * the UART divisor is available
+ */
+ gd->freqUART = gd->freqUART / udiv;
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
@@ -644,6 +650,15 @@
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EX */
+ /* Correct UART frequency in bd-info struct now that
+ * the UART divisor is available
+ */
+#ifdef CFG_EXT_SERIAL_CLOCK
+ gd->freqUART = CFG_EXT_SERIAL_CLOCK;
+#else
+ gd->freqUART = gd->freqUART / udiv;
+#endif
+
out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */