| commit | 78773f1467336f4d874a6de8e56a5092b786fde5 | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | Tue Sep 26 20:34:35 2017 +0200 |
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | Wed Apr 11 23:11:58 2018 +0200 |
| tree | 256bce0922fe3b34ebe2578b4610c4844181d86e | |
| parent | f98833dbe61e8784f6c7afed8f5ff9290973d211 [diff] |
mmc: matsushita-common: Handle Renesas div-by-1 On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>