ARM: uniphier: split out UMC clock enable
The clock enable bits for UMC are more SoC-specific than for
the other hardware blocks. Separate the UMC clocks and the other
clocks for better code reuse across SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
new file mode 100644
index 0000000..75eaab7
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pxs2_dram_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL4);
+ tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+ SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+ SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
+ SC_RSTCTRL4_NRST_UMC30;
+ writel(tmp, SC_RSTCTRL4);
+ readl(SC_RSTCTRL4); /* dummy read */
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
+ SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
+ writel(tmp, SC_CLKCTRL4);
+ readl(SC_CLKCTRL4); /* dummy read */
+}