Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- H6 WDT reset fix (Clément)
- H6 SPL_TEXT_BASE fixes (Clément, Jonas)
- NPI-M1+ emac enablment (Emmanuel)
diff --git a/Kconfig b/Kconfig
index 91c1082..da208d6 100644
--- a/Kconfig
+++ b/Kconfig
@@ -278,7 +278,7 @@
if FIT
config FIT_EXTERNAL_OFFSET
- hex "Text Base"
+ hex "FIT external data offset"
default 0x0
help
This specifies a data offset in fit image.
diff --git a/README b/README
index 8e93460..fd1e17c 100644
--- a/README
+++ b/README
@@ -634,8 +634,6 @@
the defaults discussed just above.
- Cache Configuration:
- CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
- CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
- Cache Configuration for ARM:
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 50369d5..0cb9720 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -109,12 +109,30 @@
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
- bool "Do not use Instruction Cache"
+ bool "Do not enable icache"
default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
- bool "Do not use Data Cache"
+ bool "Do not enable dcache"
default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
menuconfig ARC_DBG
bool "ARC debugging"
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 84959b4..8c744f5 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -16,7 +16,7 @@
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
@@ -37,7 +37,7 @@
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3c4af1f..00be3d1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -74,6 +74,32 @@
config THUMB2_KERNEL
bool
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
help
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 41feeef..8aee153 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -51,7 +51,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
@@ -87,7 +87,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -95,15 +95,15 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 22a55f5..16eea69 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -46,7 +46,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -54,7 +54,7 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
@@ -66,7 +66,7 @@
__weak void invalidate_l2_cache(void) {}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
@@ -80,10 +80,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index c3f1ee1..d7cffe8 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -44,7 +44,7 @@
/* flush I/D-cache */
static void cache_flush (void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 1045673..ff592ba 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -84,7 +84,7 @@
/*
* disable MMU and D cache
- * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+ * enable I cache if SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
@@ -95,7 +95,7 @@
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 99484c2..0dc4ebf 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -12,7 +12,7 @@
#define ARMV7_DCACHE_INVAL_RANGE 1
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Asm functions from cache_v7_asm.S */
void v7_flush_dcache_all(void);
@@ -149,7 +149,7 @@
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -177,9 +177,9 @@
void arm_init_domains(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
index 8bf06a3..70431ec 100644
--- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
@@ -5,7 +5,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
index 8783893..10e7488 100644
--- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <linux/sizes.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 7c4018e..ecf9e86 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* Bit[1] of the descriptor indicates the descriptor type,
@@ -215,7 +215,7 @@
invalidate_dcache_all();
set_cr(get_cr() | CR_C);
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
uint get_svr(void)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0cb6dd3..dcb4195 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -97,7 +97,7 @@
/*
* If I-cache is enabled invalidate it
*/
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
@@ -155,7 +155,7 @@
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 90fa695..f962903 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -360,7 +360,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index 815e623..1106bea 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -54,7 +54,7 @@
FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
};
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct dcache_config {
u32 ways;
u32 sets;
@@ -292,7 +292,7 @@
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
@@ -349,10 +349,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9ca397e..e500e72 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* With 4k page granule, a virtual address is split into 4 lookup parts
@@ -657,7 +657,7 @@
__asm_invalidate_tlb_all();
}
-#else /* CONFIG_SYS_DCACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -694,9 +694,9 @@
{
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable(void)
{
@@ -720,7 +720,7 @@
__asm_invalidate_l3_icache();
}
-#else /* CONFIG_SYS_ICACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
void icache_enable(void)
{
@@ -739,7 +739,7 @@
{
}
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
/*
* Enable dCache & iCache, whether cache is actually enabled
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b..12d709e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -388,7 +388,7 @@
strcpy(name, "unknown");
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -611,7 +611,7 @@
icache_enable();
dcache_enable();
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
index 1fa6841..b4cb67a 100644
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -16,7 +16,7 @@
return readl(MC_ME_CS);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL
diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
index 8b932b1..5cd4a95 100644
--- a/arch/arm/cpu/pxa/cache.c
+++ b/arch/arm/cpu/pxa/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
@@ -35,7 +35,7 @@
{
return invalidate_dcache_range(start, stop);
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -43,7 +43,7 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index b9fd41e..0b28f0a 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -286,10 +286,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83058c4..0ec7bc9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -296,6 +296,7 @@
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
+ socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi
index e4c35d4..50fc0be 100644
--- a/arch/arm/dts/armada-370-xp.dtsi
+++ b/arch/arm/dts/armada-370-xp.dtsi
@@ -102,6 +102,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+ u-boot,dm-pre-reloc;
rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
index 4b2eaee..175af38 100644
--- a/arch/arm/dts/bcm63158.dtsi
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -66,6 +66,12 @@
clock-frequency = <0xbebc200>;
u-boot,dm-pre-reloc;
};
+
+ refclk50mhz: refclk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
};
ubus {
@@ -92,13 +98,13 @@
wdt1: watchdog@ff800480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff800480 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt2: watchdog@ff8004c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff8004c0 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt-reboot {
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index 76ba0ea..91f7787 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -66,6 +66,12 @@
clock-frequency = <200000000>;
u-boot,dm-pre-reloc;
};
+
+ refclk50mhz: refclk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
};
ubus {
@@ -92,13 +98,13 @@
wdt1: watchdog@ff802780 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff802780 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt2: watchdog@ff8027c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff8027c0 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt-reboot {
diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
new file mode 100644
index 0000000..ef21523
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+
+ mainpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ perpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+
+ shared {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpga {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ noc@0xffd10000 {
+ u-boot,dm-pre-reloc;
+
+ firewall {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fpgabridge@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@2 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@3 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@4 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@5 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 42e8885..6e5578d 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -14,7 +14,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+
+#include "socfpga_arria10.dtsi"
/ {
model = "Altera SOCFPGA Arria 10";
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index cc76196..d6b6c2d 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -17,6 +17,8 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
/ {
chosen {
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index 3900965..0446fd4 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -11,8 +11,6 @@
*</auto-generated>
*/
-#include "socfpga_arria10.dtsi"
-
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -24,13 +22,11 @@
/* Clock sources */
clocks {
- u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
/* Clock source: altera_arria10_hps_eosc1 */
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
@@ -39,7 +35,6 @@
/* Clock source: altera_arria10_hps_cb_intosc_ls */
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
@@ -48,7 +43,6 @@
/* Clock source: altera_arria10_hps_f2h_free */
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
@@ -62,14 +56,12 @@
* Binding: device
*/
i_clk_mgr: clock_manager@0xffd04000 {
- u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-clk-init";
reg = <0xffd04000 0x00000200>;
reg-names = "soc_clock_manager_OCP_SLV";
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
mainpll {
- u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <191>; /* Field: vco1.numer */
@@ -98,7 +90,6 @@
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
perpll {
- u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <159>; /* Field: vco1.numer */
@@ -124,7 +115,6 @@
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
alteragrp {
- u-boot,dm-pre-reloc;
nocclk = <0x0384000b>; /* Register: nocclk */
mpuclk = <0x03840001>; /* Register: mpuclk */
};
@@ -136,7 +126,6 @@
* Binding: pinmux
*/
i_io48_pin_mux: pinmux@0xffd07000 {
- u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "pinctrl-single";
@@ -145,7 +134,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
shared {
- u-boot,dm-pre-reloc;
reg = <0xffd07000 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
@@ -202,7 +190,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated {
- u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
@@ -225,7 +212,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated_cfg {
- u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
@@ -252,7 +238,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
fpga {
- u-boot,dm-pre-reloc;
reg = <0xffd07400 0x00000100>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000001>;
@@ -283,13 +268,11 @@
* Binding: device
*/
i_noc: noc@0xffd10000 {
- u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-noc";
reg = <0xffd10000 0x00008000>;
reg-names = "mpu_m0";
firewall {
- u-boot,dm-pre-reloc;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
diff --git a/arch/arm/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi
new file mode 100644
index 0000000..bd92806
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Aries/DENX MCV";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1 GiB */
+ };
+};
+
+&mmc0 { /* On-SoM eMMC */
+ bus-width = <8>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
new file mode 100644
index 0000000..eea453b
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2019 Wolfgang Grandegger <wg@aries-embedded.de>
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
new file mode 100644
index 0000000..ceaec29
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include "socfpga_cyclone5_mcv.dtsi"
+
+/ {
+ model = "Aries/DENX MCV EVK";
+ compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ stmpe-i2c0 = &stmpe1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&gpio0 { /* GPIO 0 ... 28 */
+ status = "okay";
+};
+
+&gpio1 { /* GPIO 29 ... 57 */
+ status = "okay";
+};
+
+&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ stmpe1: stmpe811@41 {
+ compatible = "st,stmpe811";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ id = <0>;
+ blocks = <0x5>;
+ irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <3>;
+ ts,settling = <4>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c3ee5f0..a81b106 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -35,7 +35,7 @@
unsigned int tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
#if defined(CONFIG_ARM64)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0688f1e..b2913e8 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -10,7 +10,7 @@
#include <linux/compiler.h>
#include <asm/armv7_mpu.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
@@ -246,7 +246,7 @@
}
#endif
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable (void)
{
return;
@@ -278,7 +278,7 @@
}
#endif
-#ifdef CONFIG_SYS_DCACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_enable (void)
{
return;
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 565fbbe..449544d 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -87,7 +87,7 @@
noncached_end = end;
noncached_next = start;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
}
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 589e16c..2ae9a43 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -25,7 +25,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 75e1f54..a605942 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -37,7 +37,7 @@
}
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2c42535..53f9a87 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -446,7 +446,7 @@
dcache_enable();
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c
index 43d6c08..bbb335e 100644
--- a/arch/arm/mach-imx/mx5/soc.c
+++ b/arch/arm/mach-imx/mx5/soc.c
@@ -62,7 +62,7 @@
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index f43b3dc..3dee300 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -204,7 +204,7 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 893bd3f..b6cf629 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -26,12 +26,6 @@
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-/*
- * Disable the dcache. Currently the network driver (mvgbe.c) and USB
- * EHCI driver (ehci-marvell.c) and possibly others rely on the data
- * cache being disabled.
- */
-#define CONFIG_SYS_DCACHE_OFF
/*
* By default kwbimage.cfg from board specific folder is used
diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c
index 26a215a..186f6c0 100644
--- a/arch/arm/mach-mediatek/mt8516/init.c
+++ b/arch/arm/mach-mediatek/mt8516/init.c
@@ -14,14 +14,10 @@
#include <asm/armv8/mmu.h>
#include <asm/sections.h>
#include <dm/uclass.h>
-#include <linux/io.h>
#include <dt-bindings/clock/mt8516-clk.h>
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_SWRST 0x10007014
-#define WDOG_SWRST_KEY 0x1209
-
int dram_init(void)
{
int ret;
@@ -87,10 +83,7 @@
void reset_cpu(ulong addr)
{
- while (1) {
- writel(WDOG_SWRST_KEY, WDOG_SWRST);
- mdelay(5);
- }
+ psci_system_reset();
}
int print_cpuinfo(void)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0777a0c..bb01eab 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -34,7 +34,7 @@
endif
endif
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
index 6dc92a6..32de9d3 100644
--- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
@@ -16,7 +16,7 @@
.arch_extension sec
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.global flush_dcache_range
#endif
@@ -79,7 +79,7 @@
push {r4, r5, lr}
ldr r4, =omap_smc_sec_cpu1_args
stm r4, {r0,r1,r2,r3} @ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mov r0, r4
mov r1, #CONFIG_SYS_CACHELINE_SIZE
add r1, r0, r1 @ dcache is not enabled on CPU1, so
@@ -109,7 +109,7 @@
*/
.section .data
omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.balign CONFIG_SYS_CACHELINE_SIZE
.rept CONFIG_SYS_CACHELINE_SIZE/4
.word 0
diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 600a312..b45d3ee 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -333,7 +333,7 @@
debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
debug("tee_file_size = %d\n", tee_file_size);
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range(
rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
@@ -356,7 +356,7 @@
/* Reuse the tee_info buffer for SMC params */
smc_cpu1_params = (u32 *)&tee_info;
smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
roundup(sizeof(u32), ARCH_DMA_MINALIGN));
#endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index b0686ed..784a2a2 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -17,7 +17,7 @@
/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_GEN3
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
index 2094a43..e6ea0e9 100644
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ b/arch/arm/mach-rockchip/rk3036-board.c
@@ -48,7 +48,7 @@
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
index b1c6638..fa71685 100644
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -57,7 +57,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index e03759f..80d8c42 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -75,7 +75,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
index 6170c76..e7a1e54 100644
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -58,7 +58,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 41e9786..e2de5b2 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -186,7 +186,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 33596f6..66aeb3f 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -6,7 +6,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c
index 12c9d7c..0b879b5 100644
--- a/arch/arm/mach-s5pc1xx/cache.c
+++ b/arch/arm/mach-s5pc1xx/cache.c
@@ -9,7 +9,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index ea316d0..48f02f0 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -64,6 +64,10 @@
prompt "Altera SOCFPGA board select"
optional
+config TARGET_SOCFPGA_ARIES_MCVEVK
+ bool "Aries MCVEVK (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
@@ -128,6 +132,7 @@
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
+ default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
@@ -139,6 +144,7 @@
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
+ default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -159,6 +165,7 @@
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
+ default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index 5e490d1..f4dcb14 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -8,7 +8,6 @@
#include <dt-bindings/reset/altr,rst-mgr.h>
-void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index b93bbaf..452147b 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -8,7 +8,6 @@
#define _RESET_MANAGER_S10_
void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void socfpga_bridges_reset(int enable);
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index d887f02..db1983d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -48,10 +48,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 89a384b..9a32f5a 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -61,14 +61,6 @@
writel(0xffffffff, &reset_manager_base->per2_mod_reset);
}
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, &reset_manager_base->per_mod_reset);
-}
-
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 39753a1..499a84a 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -95,17 +95,6 @@
}
/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, &reset_manager_base->per1modrst);
- /* Enable OCP first */
- writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
- writel(0, &reset_manager_base->per0modrst);
-}
-
-/*
* Return non-zero if the CPU has been warm reset
*/
int cpu_has_been_warmreset(void)
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index bd2a9fe..1a60cdc 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -175,8 +175,7 @@
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for peripherals and bridges based on handoff */
- reset_deassert_peripherals_handoff();
+ /* Set bridges handoff value */
socfpga_bridges_set_handoff_regs(true, true, true);
debug("Unfreezing/Thaw all I/O banks\n");
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 921e4c5..8e9bb63 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -305,7 +305,7 @@
#endif
}
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f8fc042..4e15907 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -226,7 +226,7 @@
};
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index a3422cd..e5f55771 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -83,7 +83,7 @@
;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
index d72ff46..b6f16bf 100644
--- a/arch/nds32/Kconfig
+++ b/arch/nds32/Kconfig
@@ -16,6 +16,32 @@
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
source "board/AndesTech/adp-ag101p/Kconfig"
source "board/AndesTech/adp-ae3xx/Kconfig"
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index cf966e2..6918881 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -129,7 +129,7 @@
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
-#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/*
* MMU_CTL NTC0 Cacheable/Write-Back
*/
@@ -139,7 +139,7 @@
mtsr $r1, $mr0
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_ARCH_MAP_SYSMEM
/*
* MMU_CTL NTC1 Non-cacheable
@@ -158,14 +158,14 @@
#endif
#endif
-#if !defined(CONFIG_SYS_ICACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
li $r0, 0x2
mfsr $r1, $mr8
or $r1, $r1, $r0
diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c
index 9ab30d1..2706513 100644
--- a/arch/nds32/lib/cache.c
+++ b/arch/nds32/lib/cache.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
static inline unsigned long CACHE_SET(unsigned char cache)
{
if (cache == ICACHE)
@@ -38,7 +38,7 @@
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
unsigned long end, line_size;
@@ -133,7 +133,7 @@
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_wbinval_all(void)
{
unsigned long end, line_size;
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 362f3cd..0d04d91 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -19,6 +19,32 @@
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 228fc55..cd95058 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -30,7 +30,7 @@
void icache_enable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@@ -43,7 +43,7 @@
void icache_disable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
@@ -57,7 +57,7 @@
void dcache_enable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@@ -70,7 +70,7 @@
void dcache_disable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence\n\t"
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index bc18b71..37e0424 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -109,6 +109,10 @@
*info = (char *)((struct cb_string *)ptr)->string;
}
+__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr)
+{
+}
+
static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
{
struct cb_header *header;
@@ -211,6 +215,9 @@
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
break;
+ default:
+ cb_parse_unhandled(rec->tag, ptr);
+ break;
}
ptr += rec->size;
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 2ba7132..6de31e8 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -16,6 +16,32 @@
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
source "board/cadence/xtfpga/Kconfig"
endmenu
diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S
index 66acb4c..38d2fa2 100644
--- a/arch/xtensa/cpu/start.S
+++ b/arch/xtensa/cpu/start.S
@@ -164,19 +164,19 @@
* enable data/instruction cache for relocated image.
*/
#if XCHAL_HAVE_SPANNING_WAY && \
- (!defined(CONFIG_SYS_DCACHE_OFF) || \
- !defined(CONFIG_SYS_ICACHE_OFF))
+ !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
+ CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
srli a7, a4, 29
slli a7, a7, 29
addi a7, a7, XCHAL_SPANNING_WAY
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
rdtlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
addi a8, a8, CA_WRITEBACK
wdtlb a8, a7
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
ritlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
diff --git a/board/aries/mcvevk/MAINTAINERS b/board/aries/mcvevk/MAINTAINERS
new file mode 100644
index 0000000..8646eaf
--- /dev/null
+++ b/board/aries/mcvevk/MAINTAINERS
@@ -0,0 +1,9 @@
+Aries MCVEVK BOARD
+M: Wolfgang Grandegger <wg@aries-embedded.de>
+S: Maintained
+F: board/aries/mcvevk/
+F: include/configs/socfpga_mcvevk.h
+F: configs/socfpga_mcvevk_defconfig
+F: arch/arm/dts/socfpga_cyclone5_mcv.dtsi
+F: arch/arm/dts/socfpga_cyclone5_mcvevk.dts
+F: arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
diff --git a/board/aries/mcvevk/Makefile b/board/aries/mcvevk/Makefile
new file mode 100644
index 0000000..e1c8a6b
--- /dev/null
+++ b/board/aries/mcvevk/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y := socfpga.o
diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h
new file mode 100644
index 0000000..e233d02
--- /dev/null
+++ b/board/aries/mcvevk/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00000000,
+ 0x18060000,
+ 0x00000060,
+ 0x00000000,
+ 0x00000000,
+ 0x00004000,
+ 0x0C0300C0,
+ 0x00000000,
+ 0x0C000000,
+ 0x0000C030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x06000018,
+ 0x00006018,
+ 0x01806018,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x000C0300,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0300C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00000000,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001806,
+ 0x00000400,
+ 0x0000300C,
+ 0x00C03000,
+ 0x00C00000,
+ 0x00000003,
+ 0x00000C03,
+ 0x00000200,
+ 0x00001806,
+ 0x00601800,
+ 0x80600000,
+ 0x80000001,
+ 0x00000601,
+ 0x00000100,
+ 0x00001000,
+ 0x00300C00,
+ 0xC0300000,
+ 0xC0000000,
+ 0x00000300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x300C0300,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C0300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x00000000,
+ 0x18000000,
+ 0x00018060,
+ 0x06018060,
+ 0x00004000,
+ 0x200300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x00000000,
+ 0x06000000,
+ 0x00010018,
+ 0x01806018,
+ 0x00001000,
+ 0x0000C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00C0300C,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0C420D80,
+ 0x0C3000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x45034030,
+ 0x12481A01,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A01450,
+ 0x280D0000,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD000001A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000FF0,
+ 0x4810C000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x24086001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x49034030,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A00040,
+ 0x280D0002,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD00A281A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A890,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA24,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0x9A28A3D7,
+ 0xF511451E,
+ 0x0356E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x05140680,
+ 0xD749247A,
+ 0x1E9A28A3,
+ 0x88F51145,
+ 0x00034EE3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A890,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00800000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA24,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x86120800,
+ 0x00600240,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xEBCF23D7,
+ 0xF611451E,
+ 0x034E9248,
+ 0x821A038E,
+ 0x0000D000,
+ 0x00000680,
+ 0xD749247A,
+ 0x1E9BCF23,
+ 0x88F61145,
+ 0x00034EE3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820004,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A890,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00800000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010000,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00200000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0x9A28A3D7,
+ 0xF431451E,
+ 0x034E9248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD749247A,
+ 0x1E9A28A3,
+ 0x88F61145,
+ 0x000356E3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820004,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00800000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020000,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00001000,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x08864000,
+ 0x49247A02,
+ 0xEBCF23DB,
+ 0xF431451E,
+ 0x0356E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD749247A,
+ 0x1EEBCF23,
+ 0x88F43E79,
+ 0x000356A2,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820004,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00004000,
+ 0x00010000,
+ 0x40002080,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x00000000,
+ 0x00000008,
+ 0x00000020,
+ 0x00008000,
+ 0x20001040,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/aries/mcvevk/qts/pinmux_config.h b/board/aries/mcvevk/qts/pinmux_config.h
new file mode 100644
index 0000000..85f892a
--- /dev/null
+++ b/board/aries/mcvevk/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 3, /* EMACIO0 */
+ 3, /* EMACIO1 */
+ 3, /* EMACIO2 */
+ 3, /* EMACIO3 */
+ 3, /* EMACIO4 */
+ 3, /* EMACIO5 */
+ 3, /* EMACIO6 */
+ 3, /* EMACIO7 */
+ 3, /* EMACIO8 */
+ 3, /* EMACIO9 */
+ 3, /* EMACIO10 */
+ 3, /* EMACIO11 */
+ 3, /* EMACIO12 */
+ 3, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 3, /* FLASHIO4 */
+ 3, /* FLASHIO5 */
+ 3, /* FLASHIO6 */
+ 3, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 0, /* GENERALIO3 */
+ 0, /* GENERALIO4 */
+ 1, /* GENERALIO5 */
+ 1, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 1, /* MIXED1IO1 */
+ 1, /* MIXED1IO2 */
+ 1, /* MIXED1IO3 */
+ 1, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 1, /* MIXED1IO8 */
+ 1, /* MIXED1IO9 */
+ 1, /* MIXED1IO10 */
+ 1, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 1, /* MIXED1IO15 */
+ 1, /* MIXED1IO16 */
+ 1, /* MIXED1IO17 */
+ 1, /* MIXED1IO18 */
+ 0, /* MIXED1IO19 */
+ 0, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 1, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h
new file mode 100644
index 0000000..4fa868e
--- /dev/null
+++ b/board/aries/mcvevk/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h
new file mode 100644
index 0000000..fd72926
--- /dev/null
+++ b/board/aries/mcvevk/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 99
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 99
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080421,
+ 0x10080520,
+ 0x10090044,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080441,
+ 0x100804c0,
+ 0x100a0024,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/aries/mcvevk/socfpga.c b/board/aries/mcvevk/socfpga.c
new file mode 100644
index 0000000..f173bf8
--- /dev/null
+++ b/board/aries/mcvevk/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#include <common.h>
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index b4fc8f3..111e64b 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -26,7 +26,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 69fbc8b..9d7a94f 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -46,6 +46,15 @@
#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
#define REV_DETECTION IMX_GPIO_NR(2, 28)
+/* Speed defined in Kconfig is only applicable when not using DM_I2C. */
+#ifdef CONFIG_DM_I2C
+#define I2C1_SPEED_NON_DM 0
+#define I2C2_SPEED_NON_DM 0
+#else
+#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
+#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
+#endif
+
static bool with_pmic;
int dram_init(void)
@@ -463,13 +472,13 @@
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#if defined(CONFIG_VIDEO_IPUV3)
- setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+ setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
if (is_mx6dq() || is_mx6dqp()) {
- setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
- setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
+ setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
+ setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
} else {
- setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
- setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
+ setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
+ setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
}
setup_display();
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index cbeba6b..f576e22 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -321,7 +321,7 @@
print_eths();
#endif
print_baudrate();
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);
diff --git a/common/board_f.c b/common/board_f.c
index 7ef20f2..c25eb18 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -381,7 +381,7 @@
#ifdef CONFIG_ARM
__weak int reserve_mmu(void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
gd->relocaddr -= gd->arch.tlb_size;
diff --git a/common/lcd.c b/common/lcd.c
index cd63040..95526b1 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -61,7 +61,7 @@
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
int line_length;
if (lcd_flush_dcache)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 0a6a47c..4ddeff9 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -195,10 +195,12 @@
#ifdef CONFIG_SPL_FIT_SIGNATURE
images.verify = 1;
#endif
- fit_image_load(&images, (ulong)header,
+ ret = fit_image_load(&images, (ulong)header,
&fit_uname_fdt, &fit_uname_config,
IH_ARCH_DEFAULT, IH_TYPE_FLATDT, -1,
FIT_LOAD_OPTIONAL, &dt_data, &dt_len);
+ if (ret >= 0)
+ spl_image->fdt_addr = (void *)dt_data;
conf_noffset = fit_conf_get_node((const void *)header,
fit_uname_config);
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index afda7ed..8cb397c 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFKW=y
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index 4cb4797..1f7ff81 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFXCAT=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index b1d923c..8168c3a 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0xE80C0000
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 9727d28..37ad6ac 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -25,7 +25,6 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
@@ -43,4 +42,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index bcc5a0a..73febdf 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig
index 214a6a6..baffb2d 100644
--- a/configs/bcm23550_w1d_defconfig
+++ b/configs/bcm23550_w1d_defconfig
@@ -1,4 +1,6 @@
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM23550_W1D=y
CONFIG_SYS_TEXT_BASE=0x9f000000
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig
index 321bc22..dfd6906 100644
--- a/configs/bcm963158_ram_defconfig
+++ b/configs/bcm963158_ram_defconfig
@@ -16,7 +16,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig
index d6509e3..d331e4e 100644
--- a/configs/bcm968580xref_ram_defconfig
+++ b/configs/bcm968580xref_ram_defconfig
@@ -14,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index 63acd28..3787a95 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_BOARD="antminer_s9"
CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index 6cd948e..492ee9e 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_COLIBRI_PXA270=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 9a4d770..845565d 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 09c6147..8c16d5c 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPL_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/db-88f6281-bp-nand_defconfig b/configs/db-88f6281-bp-nand_defconfig
index 3004347..ffb24ea 100644
--- a/configs/db-88f6281-bp-nand_defconfig
+++ b/configs/db-88f6281-bp-nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/db-88f6281-bp-spi_defconfig b/configs/db-88f6281-bp-spi_defconfig
index e059680..4b1b158 100644
--- a/configs/db-88f6281-bp-spi_defconfig
+++ b/configs/db-88f6281-bp-spi_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index b41a97f..c7a7983 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -1,4 +1,6 @@
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x83F00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index 20c6628..aca8abb 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DNS325=y
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 41a70c9..679c182 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DOCKSTAR=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index 728b470..e148208 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DREAMPLUG=y
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
index 22996e8..671572b 100644
--- a/configs/ds109_defconfig
+++ b/configs/ds109_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DS109=y
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 7fb52d2..b73da72 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ASPEED=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ASPEED_AST2500=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index f6e8048..a13f609 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_FLEA3=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index c9abfb5..b5d31db 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GOFLEXHOME=y
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index b12dec2..fe2e00a 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_GPLUGD=y
CONFIG_SYS_TEXT_BASE=0x00f00000
CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index c0e798e..787ba6c 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GURUPLUG=y
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index ea64ca7..50e6bce 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_SYS_TEXT_BASE=0x00008000
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 5cadc56..979f724 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_IB62X0=y
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index e1fb3c7..eb0e8a9 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_ICONNECT=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 6811a62..7383124 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8MQ_EVK=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 238d44d..1a6ce3a 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 59675e5..c4a8cf3 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 2d43a67..53898a1 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index d68045b..78864f2 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index bcc8a69..5fabbb4 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 13cf9c9..48d7fdc 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000000
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index e93fc00..05f535b 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 37308aa..12358d1 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000000
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index cfa5959..64537ce 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index cbe1fdf..1eef7f8 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 66f48a1..c412c6f 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index 92fb248..0bd9a7f 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index b1a95cb..08b8825 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig
index 443399d..5abf543 100644
--- a/configs/km_kirkwood_pci_defconfig
+++ b/configs/km_kirkwood_pci_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index 7ec7281..b6ac31e 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index 34ece18..08e9b75 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig
index 63c5925..cafc1f9 100644
--- a/configs/kmsugp1_defconfig
+++ b/configs/kmsugp1_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig
index b2d6232..14c1c16 100644
--- a/configs/kmsuv31_defconfig
+++ b/configs/kmsuv31_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 906800c..f02776d 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 038f9d1..daeecb5 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig
index d85a216..6b36cf9 100644
--- a/configs/mgcoge3un_defconfig
+++ b/configs/mgcoge3un_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 5ca8223..80b122d 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NAS220=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index cec280b..9ae774a 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 3fa5938..6611046 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 3367889..41eeab8 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index 9a0afaa..fd56ae0 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 2f3f4d3..ffb60da 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index eb29a70..a428d76 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NSA310S=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index ea27731..3a529e8 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -4,7 +4,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 446a6d4..0868e33 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -4,7 +4,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 151e3c2..23521b2 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index c5404ef..ea53231 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index d6dcbb6..589e248 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 9d5bf7e..e7d2f45 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 943a500..5878060 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_POGO_E02=y
diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig
index 7e0abaa..fa546aa 100644
--- a/configs/portl2_defconfig
+++ b/configs/portl2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 3ffcb4a..d8792d6 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -63,6 +63,7 @@
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CPU=y
+CONFIG_NVME=y
CONFIG_SPL_DM_RTC=y
CONFIG_SPI=y
CONFIG_SPL_TIMER=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index e290c38..74a52e6 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 005b6e9..ffe50b1 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -2,6 +2,8 @@
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23000000
CONFIG_TARGET_SMARTWEB=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
new file mode 100644
index 0000000..7feedbe
--- /dev/null
+++ b/configs/socfpga_mcvevk_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="denx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 834a75f..0012374 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_STV0991=y
CONFIG_SYS_TEXT_BASE=0x00010000
CONFIG_SYS_MALLOC_F_LEN=0x2000
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 896232a..5616b3e 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 02a8959..8af7dd7 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -2,6 +2,8 @@
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index b558856..bb8d37a 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 6983245..87af8c8 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 89461ee..874ca8a 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index bb74542..ebc12ab 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_WOODBURN=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 4976a70..7182aff 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_WOODBURN_SD=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_GPIO_SUPPORT=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 2cfcf4d..bbd13e0 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -1,4 +1,6 @@
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 186c164..19fac90 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index 7f12da6..60c368c 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index 720b0dd..cbbf75f 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index e54c81c..aa9dd23 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index c8d6886..0faa332 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 29e4728..867d2e5 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index 6dc0690..4be6248 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 3fe9820..d3cc851 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 089df8d..966bb150 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 23f9549..76b85d4 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -1,6 +1,9 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index d2bddec..fad7b5d 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -1,6 +1,9 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 2d33b62..8adeffc 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig
index 913581e..f9d2b31 100644
--- a/configs/zynq_dlc20_rev1_0_defconfig
+++ b/configs/zynq_dlc20_rev1_0_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 83fa967..5e7ff16 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig
index 809fa91..f253483 100644
--- a/configs/zynq_minized_defconfig
+++ b/configs/zynq_minized_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 09d78dc..0650ce2 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index f24fe31..4839ee2 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 748b080..71559b0 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 9b0ddb0..132ef6c 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 8653d7a..8ba35cb 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index eb25836..84f46a7 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index 4e40339..43ff1f4 100644
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 868b73b..2adf686 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index b1d19f1..ed6506d 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 09fc1c3..2da6d40b 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 607bc27..b51272b 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index 81da0d2..4deb14e 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 188d843..e3135bb 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -55,17 +55,6 @@
return base + 0x100 + (port * 0x80);
}
-
-static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
- unsigned int port_idx)
-{
- base = ahci_port_base(base, port_idx);
-
- port->cmd_addr = base;
- port->scr_addr = base + PORT_SCR;
-}
-
-
#define msleep(a) udelay(a * 1000)
static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
@@ -240,7 +229,6 @@
continue;
uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
port_mmio = (u8 *)uc_priv->port[i].port_mmio;
- ahci_setup_port(&uc_priv->port[i], mmio, i);
/* make sure port is not active */
tmp = readl(port_mmio + PORT_CMD);
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 017cc89..ac589fe 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -81,7 +81,7 @@
return tmp;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
{
uint32_t addr;
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 2156240..095a9bc 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -161,7 +161,10 @@
channels and operating on standard mode up to 100 kbits/s and fast
mode up to 400 kbits/s.
-if SYS_I2C_MXC
+# These settings are not used with DM_I2C, however SPL doesn't use
+# DM_I2C even if DM_I2C is enabled, and so might use these settings even
+# when main u-boot does not!
+if SYS_I2C_MXC && (!DM_I2C || SPL)
config SYS_I2C_MXC_I2C1
bool "NXP MXC I2C1"
help
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 5420afb..23119cc 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -482,8 +482,13 @@
return ret;
}
+/* Will generate a STOP after the last byte if "last" is true, i.e. this is the
+ * final message of a transaction. If not, it switches the bus back to TX mode
+ * and does not send a STOP, leaving the bus in a state where a repeated start
+ * and address can be sent for another message.
+ */
static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
- int len)
+ int len, bool last)
{
int ret;
unsigned int temp;
@@ -513,17 +518,31 @@
return ret;
}
- /*
- * It must generate STOP before read I2DR to prevent
- * controller from generating another clock cycle
- */
if (i == (len - 1)) {
- i2c_imx_stop(i2c_bus);
+ /* Final byte has already been received by master! When
+ * we read it from I2DR, the master will start another
+ * cycle. We must program it first to send a STOP or
+ * switch to TX to avoid this.
+ */
+ if (last) {
+ i2c_imx_stop(i2c_bus);
+ } else {
+ /* Final read, no stop, switch back to tx */
+ temp = readb(base + (I2CR << reg_shift));
+ temp |= I2CR_MTX | I2CR_TX_NO_AK;
+ writeb(temp, base + (I2CR << reg_shift));
+ }
} else if (i == (len - 2)) {
+ /* Master has already recevied penultimate byte. When
+ * we read it from I2DR, master will start RX of final
+ * byte. We must set TX_NO_AK now so it does not ACK
+ * that final byte.
+ */
temp = readb(base + (I2CR << reg_shift));
temp |= I2CR_TX_NO_AK;
writeb(temp, base + (I2CR << reg_shift));
}
+
writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
buf[i] = readb(base + (I2DR << reg_shift));
}
@@ -533,13 +552,34 @@
debug(" 0x%02x", buf[ret]);
debug("\n");
- i2c_imx_stop(i2c_bus);
+ /* It is not clear to me that this is necessary */
+ if (last)
+ i2c_imx_stop(i2c_bus);
return 0;
}
#ifndef CONFIG_DM_I2C
/*
* Read data from I2C device
+ *
+ * The transactions use the syntax defined in the Linux kernel I2C docs.
+ *
+ * If alen is > 0, then this function will send a transaction of the form:
+ * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
+ * This is a normal I2C register read: writing the register address, then doing
+ * a repeated start and reading the data.
+ *
+ * If alen == 0, then we get this transaction:
+ * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
+ * This is somewhat unusual, though valid, transaction. It addresses the chip
+ * in write mode, but doesn't actually write any register address or data, then
+ * does a repeated start and reads data.
+ *
+ * If alen < 0, then we get this transaction:
+ * S Chip Rd [A] [data] A ... NA P
+ * The chip is addressed in read mode and then data is read. No register
+ * address is written first. This is perfectly valid on most devices and
+ * required on some (usually those that don't act like an array of registers).
*/
static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
int alen, u8 *buf, int len)
@@ -566,7 +606,7 @@
return ret;
}
- ret = i2c_read_data(i2c_bus, chip, buf, len);
+ ret = i2c_read_data(i2c_bus, chip, buf, len, true);
i2c_imx_stop(i2c_bus);
return ret;
@@ -574,6 +614,20 @@
/*
* Write data to I2C device
+ *
+ * If alen > 0, we get this transaction:
+ * S Chip Wr [A] addr [A] data [A] ... [A] P
+ * An ordinary write register command.
+ *
+ * If alen == 0, then we get this:
+ * S Chip Wr [A] data [A] ... [A] P
+ * This is a simple I2C write.
+ *
+ * If alen < 0, then we get this:
+ * S data [A] ... [A] P
+ * This is most likely NOT something that should be used. It doesn't send the
+ * chip address first, so in effect, the first byte of data will be used as the
+ * address.
*/
static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
int alen, const u8 *buf, int len)
@@ -881,6 +935,7 @@
return 0;
}
+/* Sends: S Addr Wr [A|NA] P */
static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
u32 chip_flags)
{
@@ -905,42 +960,54 @@
ulong base = i2c_bus->base;
int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+ int read_mode;
- /*
- * Here the 3rd parameter addr and the 4th one alen are set to 0,
- * because here we only want to send out chip address. The register
- * address is wrapped in msg.
+ /* Here address len is set to -1 to not send any address at first.
+ * Otherwise i2c_init_transfer will send the chip address with write
+ * mode set. This is wrong if the 1st message is read.
*/
- ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
+ ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
if (ret < 0) {
debug("i2c_init_transfer error: %d\n", ret);
return ret;
}
+ read_mode = -1; /* So it's always different on the first message */
for (; nmsgs > 0; nmsgs--, msg++) {
- bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
- debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
- if (msg->flags & I2C_M_RD)
- ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
- msg->len);
- else {
- ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
- msg->len);
- if (ret)
- break;
- if (next_is_read) {
- /* Reuse ret */
+ const int msg_is_read = !!(msg->flags & I2C_M_RD);
+
+ debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
+ msg->len, msg_is_read ? 'R' : 'W');
+
+ if (msg_is_read != read_mode) {
+ /* Send repeated start if not 1st message */
+ if (read_mode != -1) {
+ debug("i2c_xfer: [RSTART]\n");
ret = readb(base + (I2CR << reg_shift));
ret |= I2CR_RSTA;
writeb(ret, base + (I2CR << reg_shift));
-
- ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
- if (ret < 0) {
- i2c_imx_stop(i2c_bus);
- break;
- }
}
+ debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
+ msg_is_read ? 'R' : 'W');
+ ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
+ if (ret < 0) {
+ debug("i2c_xfer: [STOP]\n");
+ i2c_imx_stop(i2c_bus);
+ break;
+ }
+ read_mode = msg_is_read;
}
+
+ if (msg->flags & I2C_M_RD)
+ ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
+ msg->len, nmsgs == 1 ||
+ (msg->flags & I2C_M_STOP));
+ else
+ ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
+ msg->len);
+
+ if (ret < 0)
+ break;
}
if (ret)
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index be4ee2c..b93d77a 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -50,7 +50,7 @@
/*
* Cache management functions
*/
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
{
uint32_t addr = (uint32_t)info->data_buf;
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9f1c5af..590e756 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -241,7 +241,7 @@
*/
#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning Cache line size is larger than descriptor size
#endif
#endif
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index bc052e7..521e590 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -302,7 +302,7 @@
*/
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning cache-line size is larger than descriptor size
#endif
#endif
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8e54e7c..da79b76 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -34,7 +34,8 @@
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
-#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
flush_dcache_range((u32)addr, \
(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 1ee0a0a..d4965e2 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -577,7 +577,7 @@
int ret;
int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
- ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl);
+ ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl);
if (ret)
return -EIO;
@@ -646,7 +646,7 @@
ns->dev = ndev;
/* extract the namespace id from the block device name */
ns->ns_id = trailing_strtol(udev->name) + 1;
- if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)id))
+ if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id))
return -EIO;
flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c
index 395b061..15e459d 100644
--- a/drivers/nvme/nvme_show.c
+++ b/drivers/nvme/nvme_show.c
@@ -111,14 +111,14 @@
ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl));
struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl;
- if (nvme_identify(dev, 0, 1, (dma_addr_t)ctrl))
+ if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl))
return -EIO;
print_optional_admin_cmd(le16_to_cpu(ctrl->oacs), ns->devnum);
print_optional_nvm_cmd(le16_to_cpu(ctrl->oncs), ns->devnum);
print_format_nvme_attributes(ctrl->fna, ns->devnum);
- if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)id))
+ if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id))
return -EIO;
print_formats(id, ns);
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 14aac88..b19bfb4 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -149,7 +149,7 @@
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct video_priv *priv = dev_get_uclass_priv(vid);
if (priv->flush_dcache) {
diff --git a/drivers/watchdog/bcm6345_wdt.c b/drivers/watchdog/bcm6345_wdt.c
index 44f5662..9f14e7d 100644
--- a/drivers/watchdog/bcm6345_wdt.c
+++ b/drivers/watchdog/bcm6345_wdt.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <dm.h>
#include <wdt.h>
+#include <clk.h>
#include <asm/io.h>
/* WDT Value register */
@@ -26,6 +27,7 @@
struct bcm6345_wdt_priv {
void __iomem *regs;
+ unsigned long clk_rate;
};
static int bcm6345_wdt_reset(struct udevice *dev)
@@ -41,16 +43,17 @@
static int bcm6345_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
{
struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+ u32 val = priv->clk_rate / 1000 * timeout;
- if (timeout < WDT_VAL_MIN) {
+ if (val < WDT_VAL_MIN) {
debug("watchdog won't fire with less than 2 ticks\n");
- timeout = WDT_VAL_MIN;
- } else if (timeout > WDT_VAL_MAX) {
+ val = WDT_VAL_MIN;
+ } else if (val > WDT_VAL_MAX) {
debug("maximum watchdog timeout exceeded\n");
- timeout = WDT_VAL_MAX;
+ val = WDT_VAL_MAX;
}
- writel(timeout, priv->regs + WDT_VAL_REG);
+ writel(val, priv->regs + WDT_VAL_REG);
return bcm6345_wdt_reset(dev);
}
@@ -85,11 +88,19 @@
static int bcm6345_wdt_probe(struct udevice *dev)
{
struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
priv->regs = dev_remap_addr(dev);
if (!priv->regs)
return -EINVAL;
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret)
+ priv->clk_rate = clk_get_rate(&clk);
+ else
+ return -EINVAL;
+
bcm6345_wdt_stop(dev);
return 0;
diff --git a/include/ahci.h b/include/ahci.h
index b42df6c..fb96dd8 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -134,8 +134,6 @@
};
struct ahci_ioports {
- void __iomem *cmd_addr;
- void __iomem *scr_addr;
void __iomem *port_mmio;
struct ahci_cmd_hdr *cmd_slot;
struct ahci_sg *cmd_tbl_sg;
diff --git a/include/android_bootloader_message.h b/include/android_bootloader_message.h
new file mode 100644
index 0000000..b84789f
--- /dev/null
+++ b/include/android_bootloader_message.h
@@ -0,0 +1,246 @@
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/bootable/recovery
+ * File: bootloader_message/include/bootloader_message/bootloader_message.h
+ * Commit: c784ce50e8c10eaf70e1f97e24e8324aef45faf5
+ *
+ * Copyright (C) 2008 The Android Open Source Project
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ANDROID_BOOTLOADER_MESSAGE_H
+#define __ANDROID_BOOTLOADER_MESSAGE_H
+
+/* compiler.h defines the types that otherwise are included from stdint.h and
+ * stddef.h
+ */
+#include <compiler.h>
+
+/* Spaces used by misc partition are as below:
+ * 0 - 2K For bootloader_message
+ * 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used
+ * as bootloader_message_ab struct)
+ * 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices
+ * Note that these offsets are admitted by bootloader,recovery and uncrypt, so they
+ * are not configurable without changing all of them. */
+static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
+static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
+
+/* Bootloader Message (2-KiB)
+ *
+ * This structure describes the content of a block in flash
+ * that is used for recovery and the bootloader to talk to
+ * each other.
+ *
+ * The command field is updated by linux when it wants to
+ * reboot into recovery or to update radio or bootloader firmware.
+ * It is also updated by the bootloader when firmware update
+ * is complete (to boot into recovery for any final cleanup)
+ *
+ * The status field was used by the bootloader after the completion
+ * of an "update-radio" or "update-hboot" command, which has been
+ * deprecated since Froyo.
+ *
+ * The recovery field is only written by linux and used
+ * for the system to send a message to recovery or the
+ * other way around.
+ *
+ * The stage field is written by packages which restart themselves
+ * multiple times, so that the UI can reflect which invocation of the
+ * package it is. If the value is of the format "#/#" (eg, "1/3"),
+ * the UI will add a simple indicator of that status.
+ *
+ * We used to have slot_suffix field for A/B boot control metadata in
+ * this struct, which gets unintentionally cleared by recovery or
+ * uncrypt. Move it into struct bootloader_message_ab to avoid the
+ * issue.
+ */
+struct bootloader_message {
+ char command[32];
+ char status[32];
+ char recovery[768];
+
+ /* The 'recovery' field used to be 1024 bytes. It has only ever
+ * been used to store the recovery command line, so 768 bytes
+ * should be plenty. We carve off the last 256 bytes to store the
+ * stage string (for multistage packages) and possible future
+ * expansion. */
+ char stage[32];
+
+ /* The 'reserved' field used to be 224 bytes when it was initially
+ * carved off from the 1024-byte recovery field. Bump it up to
+ * 1184-byte so that the entire bootloader_message struct rounds up
+ * to 2048-byte. */
+ char reserved[1184];
+};
+
+/**
+ * We must be cautious when changing the bootloader_message struct size,
+ * because A/B-specific fields may end up with different offsets.
+ */
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_message) == 2048,
+ "struct bootloader_message size changes, which may break A/B devices");
+#endif
+
+/**
+ * The A/B-specific bootloader message structure (4-KiB).
+ *
+ * We separate A/B boot control metadata from the regular bootloader
+ * message struct and keep it here. Everything that's A/B-specific
+ * stays after struct bootloader_message, which should be managed by
+ * the A/B-bootloader or boot control HAL.
+ *
+ * The slot_suffix field is used for A/B implementations where the
+ * bootloader does not set the androidboot.ro.boot.slot_suffix kernel
+ * commandline parameter. This is used by fs_mgr to mount /system and
+ * other partitions with the slotselect flag set in fstab. A/B
+ * implementations are free to use all 32 bytes and may store private
+ * data past the first NUL-byte in this field. It is encouraged, but
+ * not mandatory, to use 'struct bootloader_control' described below.
+ *
+ * The update_channel field is used to store the Omaha update channel
+ * if update_engine is compiled with Omaha support.
+ */
+struct bootloader_message_ab {
+ struct bootloader_message message;
+ char slot_suffix[32];
+ char update_channel[128];
+
+ /* Round up the entire struct to 4096-byte. */
+ char reserved[1888];
+};
+
+/**
+ * Be cautious about the struct size change, in case we put anything post
+ * bootloader_message_ab struct (b/29159185).
+ */
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_message_ab) == 4096,
+ "struct bootloader_message_ab size changes");
+#endif
+
+#define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */
+#define BOOT_CTRL_VERSION 1
+
+struct slot_metadata {
+ /* Slot priority with 15 meaning highest priority, 1 lowest
+ * priority and 0 the slot is unbootable. */
+ uint8_t priority : 4;
+ /* Number of times left attempting to boot this slot. */
+ uint8_t tries_remaining : 3;
+ /* 1 if this slot has booted successfully, 0 otherwise. */
+ uint8_t successful_boot : 1;
+ /* 1 if this slot is corrupted from a dm-verity corruption, 0
+ * otherwise. */
+ uint8_t verity_corrupted : 1;
+ /* Reserved for further use. */
+ uint8_t reserved : 7;
+} __attribute__((packed));
+
+/* Bootloader Control AB
+ *
+ * This struct can be used to manage A/B metadata. It is designed to
+ * be put in the 'slot_suffix' field of the 'bootloader_message'
+ * structure described above. It is encouraged to use the
+ * 'bootloader_control' structure to store the A/B metadata, but not
+ * mandatory.
+ */
+struct bootloader_control {
+ /* NUL terminated active slot suffix. */
+ char slot_suffix[4];
+ /* Bootloader Control AB magic number (see BOOT_CTRL_MAGIC). */
+ uint32_t magic;
+ /* Version of struct being used (see BOOT_CTRL_VERSION). */
+ uint8_t version;
+ /* Number of slots being managed. */
+ uint8_t nb_slot : 3;
+ /* Number of times left attempting to boot recovery. */
+ uint8_t recovery_tries_remaining : 3;
+ /* Ensure 4-bytes alignment for slot_info field. */
+ uint8_t reserved0[2];
+ /* Per-slot information. Up to 4 slots. */
+ struct slot_metadata slot_info[4];
+ /* Reserved for further use. */
+ uint8_t reserved1[8];
+ /* CRC32 of all 28 bytes preceding this field (little endian
+ * format). */
+ uint32_t crc32_le;
+} __attribute__((packed));
+
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_control) ==
+ sizeof(((struct bootloader_message_ab *)0)->slot_suffix),
+ "struct bootloader_control has wrong size");
+#endif
+
+#ifndef __UBOOT__
+
+#ifdef __cplusplus
+
+#include <string>
+#include <vector>
+
+/* Return the block device name for the bootloader message partition and waits
+ * for the device for up to 10 seconds. In case of error returns the empty
+ * string. */
+std::string get_bootloader_message_blk_device(std::string* err);
+
+/* Read bootloader message into boot. Error message will be set in err. */
+bool read_bootloader_message(bootloader_message* boot, std::string* err);
+
+/* Read bootloader message from the specified misc device into boot. */
+bool read_bootloader_message_from(bootloader_message* boot, const std::string& misc_blk_device,
+ std::string* err);
+
+/* Write bootloader message to BCB. */
+bool write_bootloader_message(const bootloader_message& boot, std::string* err);
+
+/* Write bootloader message to the specified BCB device. */
+bool write_bootloader_message_to(const bootloader_message& boot,
+ const std::string& misc_blk_device, std::string* err);
+
+/* Write bootloader message (boots into recovery with the options) to BCB. Will
+ * set the command and recovery fields, and reset the rest. */
+bool write_bootloader_message(const std::vector<std::string>& options, std::string* err);
+
+/* Write bootloader message (boots into recovery with the options) to the specific BCB device. Will
+ * set the command and recovery fields, and reset the rest. */
+bool write_bootloader_message_to(const std::vector<std::string>& options,
+ const std::string& misc_blk_device, std::string* err);
+
+/* Update bootloader message (boots into recovery with the options) to BCB. Will
+ * only update the command and recovery fields. */
+bool update_bootloader_message(const std::vector<std::string>& options, std::string* err);
+
+/* Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update
+ * the command and recovery fields. */
+bool update_bootloader_message_in_struct(bootloader_message* boot,
+ const std::vector<std::string>& options);
+
+/* Clear BCB. */
+bool clear_bootloader_message(std::string* err);
+
+/* Writes the reboot-bootloader reboot reason to the bootloader_message. */
+bool write_reboot_bootloader(std::string* err);
+
+/* Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC). */
+bool read_wipe_package(std::string* package_data, size_t size, std::string* err);
+
+/* Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC). */
+bool write_wipe_package(const std::string& package_data, std::string* err);
+
+#else
+
+#include <stdbool.h>
+
+/* C Interface. */
+bool write_bootloader_message(const char* options);
+bool write_reboot_bootloader(void);
+
+#endif /* ifdef __cplusplus */
+
+#endif /* __UBOOT__ */
+
+#endif /* __ANDROID_BOOTLOADER_MESSAGE_H */
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 771189d..0cb40e7 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -21,7 +21,6 @@
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
-#define CONFIG_SYS_DCACHE_OFF
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index dd321c4..841f361 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -29,10 +29,6 @@
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-
#define CONFIG_PREBOOT
#define CONFIG_S5P_PA_SYSRAM 0x02020000
@@ -41,8 +37,4 @@
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
-/* Power */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-
#endif /* __CONFIG_H */
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
index 4606249..6815c5f 100644
--- a/include/configs/aspeed-common.h
+++ b/include/configs/aspeed-common.h
@@ -15,9 +15,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-/* Enable cache controller */
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#ifdef CONFIG_PRE_CON_BUF_SZ
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
index d0c7de3..deafb7b 100644
--- a/include/configs/bcm23550_w1d.h
+++ b/include/configs/bcm23550_w1d.h
@@ -100,8 +100,6 @@
#define CONFIG_USBID_ADDR 0x34052c46
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_L2CACHE_OFF
#endif /* __BCM23550_W1D_H */
diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h
index 2de6f21..a0f7ead 100644
--- a/include/configs/broadcom_bcm963158.h
+++ b/include/configs/broadcom_bcm963158.h
@@ -34,7 +34,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif /* CONFIG_NAND */
/*
diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h
index 355f3ef..aa6ce67 100644
--- a/include/configs/broadcom_bcm968380gerg.h
+++ b/include/configs/broadcom_bcm968380gerg.h
@@ -12,5 +12,4 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif /* CONFIG_NAND */
diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h
index 52b4f55..fdb6203 100644
--- a/include/configs/broadcom_bcm968580xref.h
+++ b/include/configs/broadcom_bcm968580xref.h
@@ -33,7 +33,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif /* CONFIG_NAND */
/*
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 622b024..d4802f9 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -16,9 +16,6 @@
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT 0x40000
-/* We will never enable dcache because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
/*
* Environment settings
*/
diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h
index 680de8f..97af9a6 100644
--- a/include/configs/db-88f6281-bp.h
+++ b/include/configs/db-88f6281-bp.h
@@ -94,6 +94,4 @@
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_SYS_DCACHE_OFF
-
#endif /* _CONFIG_DB_88F6281_BP_H */
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index ae9e4d4..c93a5de 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -14,8 +14,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index e7f8b7a..4cd823f 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -17,8 +17,6 @@
/* High Level Configuration Options */
#define CONFIG_MX35
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* Set TEXT at the beginning of the NOR flash */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index a8c4ddf..7da8739 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -33,9 +33,6 @@
* Commands configuration
*/
-/* Disable DCACHE */
-#define CONFIG_SYS_DCACHE_OFF
-
/* Network configuration */
#ifdef CONFIG_CMD_NET
#define CONFIG_ARMADA100_FEC
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 01704d8..b7271ab 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -31,7 +31,7 @@
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET 0x80000
/* Malloc */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 2566867..c0e295b 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -6,8 +6,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_SYS_TIMER_RATE (150000000/256)
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 7759bbf..e4fa2df 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -36,8 +36,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index 02c5d1c..2bdf3be 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -24,8 +24,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 40163c8..261661a 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -23,8 +23,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 5bd6392..2af5a4f 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -167,7 +167,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define CONFIG_CMD_CACHE
#endif
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 1075084..44561ac 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -14,8 +14,6 @@
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
-#define CONFIG_SYS_DCACHE_OFF 1
-
/* ORIGEN has 4 bank of DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 0d0c6bd..776d7d7 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -216,11 +216,6 @@
#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
#define CONFIG_SYS_AT91_PLLB 0x10483f0e
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
new file mode 100644
index 0000000..a2fc103
--- /dev/null
+++ b/include/configs/socfpga_mcvevk.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_ARIES_MCVEVK_H__
+#define __CONFIG_ARIES_MCVEVK_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE "fitImage"
+#define CONFIG_PREBOOT "run try_bootscript"
+#define CONFIG_BOOTCOMMAND "run mmc_mmc"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Environment is in MMC */
+#define CONFIG_ENV_OVERWRITE
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "consdev=ttyS0\0" \
+ "baudrate=115200\0" \
+ "bootscript=boot.scr\0" \
+ "setuuid=part uuid mmc 0:3 uuid\0" \
+ "netdev=eth0\0" \
+ "hostname=mcvevk\0" \
+ "kernel_addr_r=0x10000000\0" \
+ "socfpga_legacy_reset_compat=1\0" \
+ "bootm_size=0xa000000\0" \
+ "dfu_alt_info=mmc raw 0 3867148288\0" \
+ "update_filename=u-boot-with-spl.sfp\0" \
+ "update_sd_offset=0x800\0" \
+ "update_sd=" /* Update the SD firmware partition */ \
+ "if mmc rescan ; then " \
+ "if tftp ${update_filename} ; then " \
+ "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
+ "setexpr fw_sz ${fw_sz} + 1 ; " \
+ "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \
+ "fi ; " \
+ "fi\0" \
+ "update_qspi_offset=0x0\0" \
+ "update_qspi=" /* Update the QSPI firmware */ \
+ "if sf probe ; then " \
+ "if tftp ${update_filename} ; then " \
+ "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+ "fi ; " \
+ "fi\0" \
+ "fpga_filename=output_file.rbf\0" \
+ "load_fpga=" /* Load FPGA bitstream */ \
+ "if tftp ${fpga_filename} ; then " \
+ "fpga load 0 $loadaddr $filesize ; " \
+ "bridge enable ; " \
+ "fi\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "addargs=run addcons addmisc\0" \
+ "mmcload=" \
+ "mmc rescan ; " \
+ "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "mmcargs=setenv bootargs root=PARTUUID=${uuid} rw rootwait\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "mmc_mmc=" \
+ "run mmcload setuuid mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_nfs=" \
+ "run mmcload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_mmc=" \
+ "run netload setuuid mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "try_bootscript=" \
+ "mmc rescan;" \
+ "if test -e mmc 0:2 ${bootscript} ; then " \
+ "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
+ "then ; " \
+ "echo Running bootscript... ; " \
+ "source ${kernel_addr_r} ; " \
+ "fi ; " \
+ "fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_ARIES_MCVEVK_H__ */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 3177b7a..e526208 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -6,7 +6,6 @@
#ifndef __CONFIG_STV0991_H
#define __CONFIG_STV0991_H
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
/* ram memory-related information */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 45a4a80..dbb01af 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -21,10 +21,6 @@
#include <asm/hardware.h>
#include <linux/sizes.h>
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 6c86767..b44b51b 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -17,7 +17,6 @@
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
-#define CONFIG_SYS_DCACHE_OFF
/* Memory Configuration */
#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index bec7b68..5b42e0c 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -45,10 +45,6 @@
* MMU and Cache Setting
*----------------------------------------------------------------------*/
-/* Comment out the following to enable L1 cache */
-/* #define CONFIG_SYS_ICACHE_OFF */
-/* #define CONFIG_SYS_DCACHE_OFF */
-
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_TIMESTAMP
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 82c57b6..5ad3dab 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -17,8 +17,6 @@
#define CONFIG_MX35_HCLK_FREQ 24000000
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* This is required to setup the ESDC controller */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 8d97905..e260a63 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -19,8 +19,6 @@
*/
#define CONFIG_MACH_TYPE 736
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h
index c15fb5f..4b3691b 100644
--- a/include/configs/xilinx_versal_mini.h
+++ b/include/configs/xilinx_versal_mini.h
@@ -10,9 +10,6 @@
#ifndef __CONFIG_VERSAL_MINI_H
#define __CONFIG_VERSAL_MINI_H
-/* #define CONFIG_SYS_DCACHE_OFF */
-#define CONFIG_SYS_ICACHE_OFF
-
#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
#define CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h
index 8fdff50..a7ae30d 100644
--- a/include/configs/xilinx_zynqmp_mini_emmc.h
+++ b/include/configs/xilinx_zynqmp_mini_emmc.h
@@ -12,7 +12,6 @@
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x800000
diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h
index aaa9eee..692f6e5 100644
--- a/include/configs/xilinx_zynqmp_mini_nand.h
+++ b/include/configs/xilinx_zynqmp_mini_nand.h
@@ -12,7 +12,6 @@
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h
index 679ad0b..129af6e 100644
--- a/include/configs/xilinx_zynqmp_mini_qspi.h
+++ b/include/configs/xilinx_zynqmp_mini_qspi.h
@@ -12,7 +12,6 @@
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000)
#define CONFIG_SYS_MALLOC_LEN 0x2000
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 523d4da..143dc7b 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -284,11 +284,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-/* Disable dcache for SPL just for sure */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
index e7a4d41..daf7d75 100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h
@@ -10,8 +10,6 @@
#define __CONFIG_ZYNQ_CSE_H
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
#include <configs/zynq-common.h>
diff --git a/include/efi_api.h b/include/efi_api.h
index 755c405..65584dd 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -639,7 +639,7 @@
struct efi_event *wait_for_key_ex;
efi_status_t (EFIAPI *set_state) (
struct efi_simple_text_input_ex_protocol *this,
- u8 key_toggle_state);
+ u8 *key_toggle_state);
efi_status_t (EFIAPI *register_key_notify) (
struct efi_simple_text_input_ex_protocol *this,
struct efi_key_data *key_data,
@@ -1425,6 +1425,11 @@
efi_handle_t driver_binding_handle;
};
+/* Deprecated version of the Unicode collation protocol */
+#define EFI_UNICODE_COLLATION_PROTOCOL_GUID \
+ EFI_GUID(0x1d85cd7f, 0xf43d, 0x11d2, \
+ 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+/* Current version of the Unicode collation protocol */
#define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \
EFI_GUID(0xa4c751fc, 0x23ae, 0x4c3e, \
0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 07ef14b..8167e6f 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -106,9 +106,12 @@
/* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */
extern const struct efi_device_path_utilities_protocol
efi_device_path_utilities;
-/* Implementation of the EFI_UNICODE_COLLATION_PROTOCOL */
+/* deprecated version of the EFI_UNICODE_COLLATION_PROTOCOL */
extern const struct efi_unicode_collation_protocol
efi_unicode_collation_protocol;
+/* current version of the EFI_UNICODE_COLLATION_PROTOCOL */
+extern const struct efi_unicode_collation_protocol
+ efi_unicode_collation_protocol2;
extern const struct efi_hii_config_routing_protocol efi_hii_config_routing;
extern const struct efi_hii_config_access_protocol efi_hii_config_access;
extern const struct efi_hii_database_protocol efi_hii_database;
@@ -145,8 +148,10 @@
/* GUID for file system information */
extern const efi_guid_t efi_file_system_info_guid;
extern const efi_guid_t efi_guid_device_path_utilities_protocol;
-/* GUID of the Unicode collation protocol */
+/* GUID of the deprecated Unicode collation protocol */
extern const efi_guid_t efi_guid_unicode_collation_protocol;
+/* GUID of the Unicode collation protocol */
+extern const efi_guid_t efi_guid_unicode_collation_protocol2;
extern const efi_guid_t efi_guid_hii_config_routing_protocol;
extern const efi_guid_t efi_guid_hii_config_access_protocol;
extern const efi_guid_t efi_guid_hii_database_protocol;
diff --git a/include/spl.h b/include/spl.h
index f09909e..a9aaef3 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -67,7 +67,7 @@
u8 os;
uintptr_t load_addr;
uintptr_t entry_point;
-#if CONFIG_IS_ENABLED(LOAD_FIT)
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
void *fdt_addr;
#endif
u32 boot_device;
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 6501ee5..fc04ea3 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -36,14 +36,14 @@
U-Boot implements enough of its features to be able to run the UEFI
Shell, but not more than that.
-config EFI_UNICODE_COLLATION_PROTOCOL
+config EFI_UNICODE_COLLATION_PROTOCOL2
bool "Unicode collation protocol"
default y
help
The Unicode collation protocol is used for lexical comparisons. It is
required to run the UEFI shell.
-if EFI_UNICODE_COLLATION_PROTOCOL
+if EFI_UNICODE_COLLATION_PROTOCOL2
config EFI_UNICODE_CAPITALIZATION
bool "Support Unicode capitalization"
@@ -54,6 +54,17 @@
set, only the the correct handling of the letters of the codepage
used by the FAT file system is ensured.
+config EFI_UNICODE_COLLATION_PROTOCOL
+ bool "Deprecated version of the Unicode collation protocol"
+ default n
+ help
+ In EFI 1.10 a version of the Unicode collation protocol using ISO
+ 639-2 language codes existed. This protocol is not part of the UEFI
+ specification any longer. Unfortunately it is required to run the
+ UEFI Self Certification Test (SCT) II, version 2.6, 2017.
+
+ Choose this option for testing only. It is bound to be removed.
+
endif
config EFI_LOADER_BOUNCE_BUFFER
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index f3d6773..01769ea 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -30,7 +30,7 @@
obj-y += efi_root_node.o
obj-y += efi_runtime.o
obj-y += efi_setup.o
-obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL) += efi_unicode_collation.o
+obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o
obj-y += efi_variable.o
obj-y += efi_watchdog.o
obj-$(CONFIG_LCD) += efi_gop.o
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index ec6f575..971bd5f 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1916,10 +1916,17 @@
static efi_status_t EFIAPI efi_get_next_monotonic_count(uint64_t *count)
{
static uint64_t mono;
+ efi_status_t ret;
EFI_ENTRY("%p", count);
+ if (!count) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
*count = mono++;
- return EFI_EXIT(EFI_SUCCESS);
+ ret = EFI_SUCCESS;
+out:
+ return EFI_EXIT(ret);
}
/**
@@ -2334,6 +2341,7 @@
efi_va_list argptr;
const efi_guid_t *protocol;
void *protocol_interface;
+ efi_handle_t old_handle;
efi_status_t r = EFI_SUCCESS;
int i = 0;
@@ -2346,6 +2354,17 @@
if (!protocol)
break;
protocol_interface = efi_va_arg(argptr, void*);
+ /* Check that a device path has not been installed before */
+ if (!guidcmp(protocol, &efi_guid_device_path)) {
+ struct efi_device_path *dp = protocol_interface;
+
+ r = EFI_CALL(efi_locate_device_path(protocol, &dp,
+ &old_handle));
+ if (r == EFI_SUCCESS) {
+ r = EFI_ALREADY_STARTED;
+ break;
+ }
+ }
r = EFI_CALL(efi_install_protocol_interface(
handle, protocol,
EFI_NATIVE_INTERFACE,
@@ -2453,9 +2472,16 @@
efi_uintn_t data_size,
u32 *crc32_p)
{
+ efi_status_t ret = EFI_SUCCESS;
+
EFI_ENTRY("%p, %zu", data, data_size);
+ if (!data || !data_size || !crc32_p) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
*crc32_p = crc32(0, data, data_size);
- return EFI_EXIT(EFI_SUCCESS);
+out:
+ return EFI_EXIT(ret);
}
/**
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 051fc1d..b2cb18e 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -136,6 +136,11 @@
EFI_ENTRY("%p, %p", this, string);
+ if (!this || !string) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
buf = malloc(utf16_utf8_strlen(string) + 1);
if (!buf) {
ret = EFI_OUT_OF_RESOURCES;
@@ -825,7 +830,7 @@
* efi_cin_set_state() - set toggle key state
*
* @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
- * @key_toggle_state: key toggle state
+ * @key_toggle_state: pointer to key toggle state
* Return: status code
*
* This function implements the SetState service of the
@@ -836,9 +841,9 @@
*/
static efi_status_t EFIAPI efi_cin_set_state(
struct efi_simple_text_input_ex_protocol *this,
- u8 key_toggle_state)
+ u8 *key_toggle_state)
{
- EFI_ENTRY("%p, %u", this, key_toggle_state);
+ EFI_ENTRY("%p, %p", this, key_toggle_state);
/*
* U-Boot supports multiple console input sources like serial and
* net console for which a key toggle state cannot be set at all.
diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c
index f3a9579..96fd089 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -79,9 +79,8 @@
struct efi_device_path_acpi_path *adp =
(struct efi_device_path_acpi_path *)dp;
- s += sprintf(s, "Acpi(PNP%04X", EISA_PNP_NUM(adp->hid));
- s += sprintf(s, ",%d", adp->uid);
- s += sprintf(s, ")");
+ s += sprintf(s, "Acpi(PNP%04X,%d)", EISA_PNP_NUM(adp->hid),
+ adp->uid);
break;
}
default:
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index e0e222a..d71c663 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -392,7 +392,7 @@
efi_timer_check();
/* Check parameters */
- if (!this) {
+ if (!this || !buffer) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
@@ -408,7 +408,7 @@
* TODO: We would need to create the header
* if header_size != 0
*/
- ret = EFI_INVALID_PARAMETER;
+ ret = EFI_UNSUPPORTED;
goto out;
}
@@ -466,7 +466,7 @@
efi_timer_check();
/* Check parameters */
- if (!this) {
+ if (!this || !buffer || !buffer_size) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
diff --git a/lib/efi_loader/efi_root_node.c b/lib/efi_loader/efi_root_node.c
index d8496cc..f68b0fd 100644
--- a/lib/efi_loader/efi_root_node.c
+++ b/lib/efi_loader/efi_root_node.c
@@ -60,11 +60,16 @@
/* Device path utilities protocol */
&efi_guid_device_path_utilities_protocol,
(void *)&efi_device_path_utilities,
+#if CONFIG_IS_ENABLED(EFI_UNICODE_COLLATION_PROTOCOL2)
#if CONFIG_IS_ENABLED(EFI_UNICODE_COLLATION_PROTOCOL)
- /* Unicode collation protocol */
+ /* Deprecated Unicode collation protocol */
&efi_guid_unicode_collation_protocol,
(void *)&efi_unicode_collation_protocol,
#endif
+ /* Current Unicode collation protocol */
+ &efi_guid_unicode_collation_protocol2,
+ (void *)&efi_unicode_collation_protocol2,
+#endif
#if CONFIG_IS_ENABLED(EFI_LOADER_HII)
/* HII string protocol */
&efi_guid_hii_string_protocol,
diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c
index 7f3ea3c..06fddca 100644
--- a/lib/efi_loader/efi_unicode_collation.c
+++ b/lib/efi_loader/efi_unicode_collation.c
@@ -26,8 +26,8 @@
static const u16 codepage[] = CP437;
#endif
-/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL */
-const efi_guid_t efi_guid_unicode_collation_protocol =
+/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL2 */
+const efi_guid_t efi_guid_unicode_collation_protocol2 =
EFI_UNICODE_COLLATION_PROTOCOL2_GUID;
/**
@@ -318,7 +318,7 @@
return ret;
}
-const struct efi_unicode_collation_protocol efi_unicode_collation_protocol = {
+const struct efi_unicode_collation_protocol efi_unicode_collation_protocol2 = {
.stri_coll = efi_stri_coll,
.metai_match = efi_metai_match,
.str_lwr = efi_str_lwr,
@@ -327,3 +327,30 @@
.str_to_fat = efi_str_to_fat,
.supported_languages = "en",
};
+
+/*
+ * In EFI 1.10 a version of the Unicode collation protocol using ISO 639-2
+ * language codes existed. This protocol is not part of the UEFI specification
+ * any longer. Unfortunately it is required to run the UEFI Self Certification
+ * Test (SCT) II, version 2.6, 2017. So we implement it here for the sole
+ * purpose of running the SCT. It can be removed when a compliant SCT is
+ * available.
+ */
+#if CONFIG_IS_ENABLED(EFI_UNICODE_COLLATION_PROTOCOL)
+
+/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL */
+const efi_guid_t efi_guid_unicode_collation_protocol =
+ EFI_UNICODE_COLLATION_PROTOCOL_GUID;
+
+const struct efi_unicode_collation_protocol efi_unicode_collation_protocol = {
+ .stri_coll = efi_stri_coll,
+ .metai_match = efi_metai_match,
+ .str_lwr = efi_str_lwr,
+ .str_upr = efi_str_upr,
+ .fat_to_str = efi_fat_to_str,
+ .str_to_fat = efi_str_to_fat,
+ /* ISO 639-2 language code */
+ .supported_languages = "eng",
+};
+
+#endif
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 37728c3..28b1aa7 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -202,8 +202,10 @@
len /= 2;
*data_size = len;
- if (in_size < len)
- return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ if (in_size < len) {
+ ret = EFI_BUFFER_TOO_SMALL;
+ goto out;
+ }
if (!data)
return EFI_EXIT(EFI_INVALID_PARAMETER);
@@ -217,8 +219,10 @@
*data_size = len;
- if (in_size < len)
- return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ if (in_size < len) {
+ ret = EFI_BUFFER_TOO_SMALL;
+ goto out;
+ }
if (!data)
return EFI_EXIT(EFI_INVALID_PARAMETER);
@@ -232,10 +236,11 @@
return EFI_EXIT(EFI_DEVICE_ERROR);
}
+out:
if (attributes)
*attributes = attr & EFI_VARIABLE_MASK;
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_EXIT(ret);
}
static char *efi_variables_list;
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index d0bebc7..cfbb40c 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -38,7 +38,8 @@
efi_selftest_watchdog.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o
-obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL) += efi_selftest_unicode_collation.o
+obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += \
+efi_selftest_unicode_collation.o
obj-$(CONFIG_CPU_V7) += efi_selftest_unaligned.o
obj-$(CONFIG_EFI_LOADER_HII) += efi_selftest_hii.o
diff --git a/tools/fit_check_sign.c b/tools/fit_check_sign.c
index 62adc75..4528743 100644
--- a/tools/fit_check_sign.c
+++ b/tools/fit_check_sign.c
@@ -70,10 +70,10 @@
usage(*argv);
}
- ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false);
+ ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false, true);
if (ffd < 0)
return EXIT_FAILURE;
- kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false);
+ kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false, true);
if (kfd < 0)
return EXIT_FAILURE;
diff --git a/tools/fit_common.c b/tools/fit_common.c
index 9506390..cdf987d 100644
--- a/tools/fit_common.c
+++ b/tools/fit_common.c
@@ -41,13 +41,14 @@
}
int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc,
- void **blobp, struct stat *sbuf, bool delete_on_error)
+ void **blobp, struct stat *sbuf, bool delete_on_error,
+ bool read_only)
{
void *ptr;
int fd;
/* Load FIT blob into memory (we need to write hashes/signatures) */
- fd = open(fname, O_RDWR | O_BINARY);
+ fd = open(fname, (read_only ? O_RDONLY : O_RDWR) | O_BINARY);
if (fd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
@@ -71,7 +72,9 @@
}
errno = 0;
- ptr = mmap(0, sbuf->st_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
+ ptr = mmap(0, sbuf->st_size,
+ (read_only ? PROT_READ : PROT_READ | PROT_WRITE), MAP_SHARED,
+ fd, 0);
if ((ptr == MAP_FAILED) || (errno != 0)) {
fprintf(stderr, "%s: Can't read %s: %s\n",
cmdname, fname, strerror(errno));
diff --git a/tools/fit_common.h b/tools/fit_common.h
index 9e09624..1e81d4c 100644
--- a/tools/fit_common.h
+++ b/tools/fit_common.h
@@ -32,9 +32,11 @@
* @blobp: Returns pointer to FDT blob
* @sbuf: File status information is stored here
* @delete_on_error: true to delete the file if we get an error
+ * @read_only: true to open in read-only mode
* @return 0 if OK, -1 on error.
*/
int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc,
- void **blobp, struct stat *sbuf, bool delete_on_error);
+ void **blobp, struct stat *sbuf, bool delete_on_error,
+ bool read_only);
#endif /* _FIT_COMMON_H_ */
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 3b867e0..5aca634 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -33,7 +33,8 @@
void *ptr;
int ret = 0;
- tfd = mmap_fdt(params->cmdname, tmpfile, size_inc, &ptr, &sbuf, true);
+ tfd = mmap_fdt(params->cmdname, tmpfile, size_inc, &ptr, &sbuf, true,
+ false);
if (tfd < 0)
return -EIO;
@@ -41,7 +42,8 @@
struct stat dest_sbuf;
destfd = mmap_fdt(params->cmdname, params->keydest, size_inc,
- &dest_blob, &dest_sbuf, false);
+ &dest_blob, &dest_sbuf, false,
+ false);
if (destfd < 0) {
ret = -EIO;
goto err_keydest;
@@ -420,7 +422,7 @@
int images;
int node;
- fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false);
+ fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false, false);
if (fd < 0)
return -EIO;
fit_size = fdt_totalsize(fdt);
@@ -531,7 +533,7 @@
int images;
int node;
- fd = mmap_fdt(params->cmdname, fname, 0, &old_fdt, &sbuf, false);
+ fd = mmap_fdt(params->cmdname, fname, 0, &old_fdt, &sbuf, false, false);
if (fd < 0)
return -EIO;
fit_size = fdt_totalsize(old_fdt);
diff --git a/tools/fit_info.c b/tools/fit_info.c
index 45e0b31..b2642ec 100644
--- a/tools/fit_info.c
+++ b/tools/fit_info.c
@@ -80,7 +80,7 @@
fprintf(stderr, "%s: Missing property name\n", *argv);
usage(*argv);
}
- ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false);
+ ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false, false);
if (ffd < 0) {
printf("Could not open %s\n", fdtfile);