* Patch by Marc Singer, 29 May 2003:
Fixed rarp boot method for IA32 and other little-endian CPUs.
* Patch by Marc Singer, 28 May 2003:
Added port I/O commands.
* Patch by Matthew McClintock, 28 May 2003
- cpu/mpc824x/start.S: fix relocation code when booting from RAM
- minor patches for utx8245
* Patch by Daniel Engström, 28 May 2003:
x86 update
* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
add nand flash support to SXNI855T configuration
fix/extend nand flash support:
- fix 'nand erase' command so does not erase bad blocks
- fix 'nand write' command so does not write to bad blocks
- fix nand_probe() so handles no flash detected properly
- add doc/README.nand
- add .jffs2 and .oob options to nand read/write
- add 'nand bad' command to list bad blocks
- add 'clean' option to 'nand erase' to write JFFS2 clean markers
- make NAND read/write faster
* Patch by Rune Torgersen, 23 May 2003:
Update for MPC8266ADS board
diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c
index 3e34828..501e610 100644
--- a/board/mpc8266ads/mpc8266ads.c
+++ b/board/mpc8266ads/mpc8266ads.c
@@ -489,10 +489,13 @@
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
-#if 1
+
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_psrt = psrt;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+ memctl->memc_or2 = or;
+
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
*ramaddr = c;
@@ -530,41 +533,7 @@
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
}
-#endif
- /*
- printf("memctl->memc_mptpr = 0x%08x\n", CFG_MPTPR);
- printf("memctl->memc_psrt = 0x%08x\n", psrt);
- printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_PREA);
- printf("ramaddr = 0x%08x\n", ramaddr);
-
- printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_CBRR);
-
- printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_MRW);
-
- printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_NORM | PSDMR_RFEN);
-
- immap->im_siu_conf.sc_ppc_acr = 0x00000002;
- immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
- */
-#if 0
- /* init sdram dimm */
- ramaddr = (uchar *)CFG_SDRAM_BASE;
- memctl->memc_psrt = 0x00000010;
- immap->im_memctl.memc_or2 = 0xFF000CA0;
- immap->im_memctl.memc_br2 = 0x00000041;
- memctl->memc_psdmr = 0x296EB452;
- *ramaddr = c;
- memctl->memc_psdmr = 0x096EB452;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = 0x196EB452;
- *ramaddr = c;
- memctl->memc_psdmr = 0x416EB452;
- *ramaddr = c;
-#endif
/* print info */
printf("SDRAM configuration read from SPD\n");
printf("\tSize per side = %dMB\n", sdram_size >> 20);
@@ -576,6 +545,7 @@
/*return (16 * 1024 * 1024);*/
}
+
#ifdef CONFIG_PCI
struct pci_controller hose;