arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d889ad5..be3358a 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -11,6 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
+#include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
@@ -140,17 +141,6 @@
 	return 66666666;
 }
 
-unsigned int get_soc_major_rev(void)
-{
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	unsigned int svr, major;
-
-	svr = in_be32(&gur->svr);
-	major = SVR_MAJ(svr);
-
-	return major;
-}
-
 int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;
@@ -193,8 +183,6 @@
 int board_early_init_f(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-	unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
 	/* clear BD & FR bits for BE BD's and frame data */
@@ -205,40 +193,7 @@
 	init_early_memctl_regs();
 #endif
 
-#ifdef CONFIG_FSL_QSPI
-	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
-#endif
-
-#ifdef CONFIG_FSL_DCU_FB
-	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-#endif
-
-	/* Configure Little endian for SAI, ASRC and SPDIF */
-	out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
-
-	/*
-	 * Enable snoop requests and DVM message requests for
-	 * Slave insterface S4 (A7 core cluster)
-	 */
-	out_le32(&cci->slave[4].snoop_ctrl,
-		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
-
-	major = get_soc_major_rev();
-	if (major == SOC_MAJOR_VER_1_0) {
-		/*
-		 * Set CCI-400 Slave interface S1, S2 Shareable Override
-		 * Register All transactions are treated as non-shareable
-		 */
-		out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-		out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
-		/* Workaround for the issue that DDR could not respond to
-		 * barrier transaction which is generated by executing DSB/ISB
-		 * instruction. Set CCI-400 control override register to
-		 * terminate the barrier transaction. After DDR is initialized,
-		 * allow barrier transaction to DDR again */
-		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
-	}
+	arch_soc_init();
 
 #if defined(CONFIG_DEEP_SLEEP)
 	if (is_warm_boot())