Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.10-rc1
global:
- Use proper U-Boot project name
Fix sparse warnings in zynqmp-clk, zynqmp handoff, board
cmd:
- Cover incorrect 0 length entries
Versal NET:
- Add bootmode logic
- Support SPP production version
- Add loadpdi command
ZynqMP:
- Clear pmufw node command ID handling
- Change power domain behavior around zynqmp_pmufw_node()
- Fix zynqmp cmd return values and pmufw command
- Fix R5 tcm init and modes
mmc:
- Sync Versal NET emmc DT binding
pcie:
- Add support for ZynqMP PCIe root port
video:
- Add support for ZynqMP DP
tools:
- Fix debug message in relocate-rela
diff --git a/Makefile b/Makefile
index 10bfaa5..e232b7b 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2023
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@@ -423,7 +423,8 @@
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
- -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
+ -Wbitwise -Wno-return-void -Wno-unknown-attribute \
+ -D__CHECK_ENDIAN__ $(CF)
KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
@@ -1032,6 +1033,9 @@
LDFLAGS_u-boot += -Ttext $(CONFIG_TEXT_BASE)
endif
+# make the checker run with the right architecture
+CHECKFLAGS += --arch=$(ARCH)
+
# insure the checker run with the right endianness
CHECKFLAGS += $(if $(CONFIG_CPU_BIG_ENDIAN),-mbig-endian,-mlittle-endian)
@@ -1808,7 +1812,7 @@
rm -f $@; \
touch $@ ; \
fi
-include/generated/env.in: include/generated/env.txt FORCE
+include/generated/env.in: include/generated/env.txt
$(call cmd,gen_envp)
# Regenerate the environment if it changes
@@ -1826,7 +1830,7 @@
touch $@ ; \
fi
-include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE
+include/generated/env.txt: $(wildcard $(ENV_FILE))
$(call cmd,envc)
# Write out the resulting environment, converted to a C string
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269f..204c687 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -451,7 +451,6 @@
am4372-generic.dtb \
am437x-cm-t43.dtb
dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
-dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
@@ -1053,7 +1052,9 @@
r8a77965-ulcb-u-boot.dtb \
r8a77965-salvator-x-u-boot.dtb \
r8a77970-eagle-u-boot.dtb \
+ r8a77970-v3msk-u-boot.dtb \
r8a77980-condor-u-boot.dtb \
+ r8a77980-v3hsk-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
diff --git a/arch/arm/dts/dm8168-evm-u-boot.dtsi b/arch/arm/dts/dm8168-evm-u-boot.dtsi
deleted file mode 100644
index f939df2..0000000
--- a/arch/arm/dts/dm8168-evm-u-boot.dtsi
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * dm8168-evm U-Boot Additions
- *
- * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
- */
-
-/ {
- ocp {
- bootph-all;
- };
-};
diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts
deleted file mode 100644
index 70255ab..0000000
--- a/arch/arm/dts/dm8168-evm.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/dts-v1/;
-
-#include "dm816x.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "DM8168 EVM";
- compatible = "ti,dm8168-evm", "ti,dm8168";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x40000000 /* 1 GB */
- 0xc0000000 0x40000000>; /* 1 GB */
- };
-
- /* FDC6331L controlled by SD_POW pin */
- vmmcsd_fixed: fixedregulator0 {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&dm816x_pinmux {
- mcspi1_pins: pinmux_mcspi1_pins {
- pinctrl-single,pins = <
- DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */
- DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */
- DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */
- DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */
- >;
- };
-
- mmc_pins: pinmux_mmc_pins {
- pinctrl-single,pins = <
- DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
- DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
- DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
- DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
- DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
- DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
- DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
- DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
- DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
- >;
- };
-
- usb0_pins: pinmux_usb0_pins {
- pinctrl-single,pins = <
- DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
- >;
- };
-};
-
-&i2c1 {
- extgpio0: pcf8575@20 {
- compatible = "nxp,pcf8575";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&i2c2 {
- extgpio1: pcf8575@20 {
- compatible = "nxp,pcf8575";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&gpmc {
- ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
-
- nand@0,0 {
- compatible = "ti,omap2-nand";
- linux,mtd-name= "micron,mt29f2g16aadwp";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- interrupt-parent = <&gpmc>;
- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- #address-cells = <1>;
- #size-cells = <1>;
- ti,nand-ecc-opt = "bch8";
- nand-bus-width = <16>;
- gpmc,device-width = <2>;
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-on-ns = <0>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <0>;
- gpmc,clk-activation-ns = <0>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
- partition@0 {
- label = "X-Loader";
- reg = <0 0x80000>;
- };
- partition@80000 {
- label = "U-Boot";
- reg = <0x80000 0x1c0000>;
- };
- partition@1c0000 {
- label = "Environment";
- reg = <0x240000 0x40000>;
- };
- partition@280000 {
- label = "Kernel";
- reg = <0x280000 0x500000>;
- };
- partition@780000 {
- label = "Filesystem";
- reg = <0x780000 0xf880000>;
- };
- };
-};
-
-&mcspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi1_pins>;
-
- flash@0 {
- compatible = "w25x32";
- spi-max-frequency = <48000000>;
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc_pins>;
- vmmc-supply = <&vmmcsd_fixed>;
- bus-width = <4>;
- cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
-};
-
-/* At least dm8168-evm rev c won't support multipoint, later may */
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins>;
- mentor,multipoint = <0>;
-};
-
-&usb1 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
- mentor,multipoint = <0>;
-};
diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi
deleted file mode 100644
index f7a839d..0000000
--- a/arch/arm/dts/dm816x-clocks.dtsi
+++ /dev/null
@@ -1,246 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-&scrm {
- main_fapll: main_fapll {
- #clock-cells = <1>;
- compatible = "ti,dm816-fapll-clock";
- reg = <0x400 0x40>;
- clocks = <&sys_clkin_ck &sys_clkin_ck>;
- clock-indices = <1>, <2>, <3>, <4>, <5>,
- <6>, <7>;
- clock-output-names = "main_pll_clk1",
- "main_pll_clk2",
- "main_pll_clk3",
- "main_pll_clk4",
- "main_pll_clk5",
- "main_pll_clk6",
- "main_pll_clk7";
- };
-
- ddr_fapll: ddr_fapll {
- #clock-cells = <1>;
- compatible = "ti,dm816-fapll-clock";
- reg = <0x440 0x30>;
- clocks = <&sys_clkin_ck &sys_clkin_ck>;
- clock-indices = <1>, <2>, <3>, <4>;
- clock-output-names = "ddr_pll_clk1",
- "ddr_pll_clk2",
- "ddr_pll_clk3",
- "ddr_pll_clk4";
- };
-
- video_fapll: video_fapll {
- #clock-cells = <1>;
- compatible = "ti,dm816-fapll-clock";
- reg = <0x470 0x30>;
- clocks = <&sys_clkin_ck &sys_clkin_ck>;
- clock-indices = <1>, <2>, <3>;
- clock-output-names = "video_pll_clk1",
- "video_pll_clk2",
- "video_pll_clk3";
- };
-
- audio_fapll: audio_fapll {
- #clock-cells = <1>;
- compatible = "ti,dm816-fapll-clock";
- reg = <0x4a0 0x30>;
- clocks = <&main_fapll 7>, < &sys_clkin_ck>;
- clock-indices = <1>, <2>, <3>, <4>, <5>;
- clock-output-names = "audio_pll_clk1",
- "audio_pll_clk2",
- "audio_pll_clk3",
- "audio_pll_clk4",
- "audio_pll_clk5";
- };
-};
-
-&scrm_clocks {
- secure_32k_ck: secure_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- sys_32k_ck: sys_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- tclkin_ck: tclkin_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- sys_clkin_ck: sys_clkin_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <27000000>;
- };
-};
-
-/* 0x48180000 */
-&prcm_clocks {
- clkout_pre_ck: clkout_pre_ck@100 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
- &audio_fapll 1>;
- reg = <0x100>;
- };
-
- clkout_div_ck: clkout_div_ck@100 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout_pre_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <8>;
- reg = <0x100>;
- };
-
- clkout_ck: clkout_ck@100 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout_div_ck>;
- ti,bit-shift = <7>;
- reg = <0x100>;
- };
-
- /* CM_DPLL clocks p1795 */
- sysclk1_ck: sysclk1_ck@300 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&main_fapll 1>;
- ti,max-div = <7>;
- reg = <0x0300>;
- };
-
- sysclk2_ck: sysclk2_ck@304 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&main_fapll 2>;
- ti,max-div = <7>;
- reg = <0x0304>;
- };
-
- sysclk3_ck: sysclk3_ck@308 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&main_fapll 3>;
- ti,max-div = <7>;
- reg = <0x0308>;
- };
-
- sysclk4_ck: sysclk4_ck@30c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&main_fapll 4>;
- ti,max-div = <1>;
- reg = <0x030c>;
- };
-
- sysclk5_ck: sysclk5_ck@310 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sysclk4_ck>;
- ti,max-div = <1>;
- reg = <0x0310>;
- };
-
- sysclk6_ck: sysclk6_ck@314 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&main_fapll 4>;
- ti,dividers = <2>, <4>;
- reg = <0x0314>;
- };
-
- sysclk10_ck: sysclk10_ck@324 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&ddr_fapll 2>;
- ti,max-div = <7>;
- reg = <0x0324>;
- };
-
- sysclk24_ck: sysclk24_ck@3b4 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&main_fapll 5>;
- ti,max-div = <7>;
- reg = <0x03b4>;
- };
-
- mpu_ck: mpu_ck@15dc {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sysclk2_ck>;
- ti,bit-shift = <1>;
- reg = <0x15dc>;
- };
-
- audio_pll_a_ck: audio_pll_a_ck@35c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&audio_fapll 1>;
- ti,max-div = <7>;
- reg = <0x035c>;
- };
-
- sysclk18_ck: sysclk18_ck@378 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
- reg = <0x0378>;
- };
-
- timer1_fck: timer1_fck@390 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
- reg = <0x0390>;
- };
-
- timer2_fck: timer2_fck@394 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
- reg = <0x0394>;
- };
-
- timer3_fck: timer3_fck@398 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
- reg = <0x0398>;
- };
-
- timer4_fck: timer4_fck@39c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
- reg = <0x039c>;
- };
-
- timer5_fck: timer5_fck@3a0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
- reg = <0x03a0>;
- };
-
- timer6_fck: timer6_fck@3a4 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
- reg = <0x03a4>;
- };
-
- timer7_fck: timer7_fck@3a8 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
- reg = <0x03a8>;
- };
-};
diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi
deleted file mode 100644
index c4a8653..0000000
--- a/arch/arm/dts/dm816x.dtsi
+++ /dev/null
@@ -1,517 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/omap.h>
-
-/ {
- compatible = "ti,dm816";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
-
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- ethernet0 = ð0;
- ethernet1 = ð1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "arm,cortex-a8";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a8-pmu";
- interrupts = <3>;
- };
-
- /*
- * The soc node represents the soc top level view. It is used for IPs
- * that are not memory mapped in the MPU view or for the MPU itself.
- */
- soc {
- compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap3-mpu";
- ti,hwmods = "mpu";
- };
- };
-
- /*
- * XXX: Use a flat representation of the dm816x interconnect.
- * The real dm816x interconnect network is quite complex. Since
- * it will not bring real advantage to represent that in DT
- * for the moment, just use a fake OCP bus entry to represent
- * the whole bus hierarchy.
- */
- ocp {
- compatible = "simple-bus";
- reg = <0x44000000 0x10000>;
- interrupts = <9 10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- prcm: prcm@48180000 {
- compatible = "ti,dm816-prcm", "simple-bus";
- reg = <0x48180000 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x48180000 0x4000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scrm: scrm@48140000 {
- compatible = "ti,dm816-scrm", "simple-bus";
- reg = <0x48140000 0x21000>;
- #address-cells = <1>;
- #size-cells = <1>;
- #pinctrl-cells = <1>;
- ranges = <0 0x48140000 0x21000>;
-
- dm816x_pinmux: pinmux@800 {
- compatible = "pinctrl-single";
- reg = <0x800 0x50a>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xf>;
- };
-
- /* Device Configuration Registers */
- scm_conf: syscon@600 {
- compatible = "syscon", "simple-bus";
- reg = <0x600 0x110>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x600 0x110>;
-
- usb_phy0: usb-phy@20 {
- compatible = "ti,dm8168-usb-phy";
- reg = <0x20 0x8>;
- reg-names = "phy";
- clocks = <&main_fapll 6>;
- clock-names = "refclk";
- #phy-cells = <0>;
- syscon = <&scm_conf>;
- };
-
- usb_phy1: usb-phy@28 {
- compatible = "ti,dm8168-usb-phy";
- reg = <0x28 0x8>;
- reg-names = "phy";
- clocks = <&main_fapll 6>;
- clock-names = "refclk";
- #phy-cells = <0>;
- syscon = <&scm_conf>;
- };
- };
-
- scrm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- scrm_clockdomains: clockdomains {
- };
- };
-
- edma: edma@49000000 {
- compatible = "ti,edma3";
- ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
- reg = <0x49000000 0x10000>,
- <0x44e10f90 0x40>;
- interrupts = <12 13 14>;
- #dma-cells = <1>;
- };
-
- elm: elm@48080000 {
- compatible = "ti,816-elm";
- ti,hwmods = "elm";
- reg = <0x48080000 0x2000>;
- interrupts = <4>;
- };
-
- gpio1: gpio@48032000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio1";
- ti,gpio-always-on;
- reg = <0x48032000 0x1000>;
- interrupts = <96>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@4804c000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio2";
- ti,gpio-always-on;
- reg = <0x4804c000 0x1000>;
- interrupts = <98>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpmc: gpmc@50000000 {
- compatible = "ti,am3352-gpmc";
- ti,hwmods = "gpmc";
- reg = <0x50000000 0x2000>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <100>;
- dmas = <&edma 52>;
- dma-names = "rxtx";
- gpmc,num-cs = <6>;
- gpmc,num-waitpins = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c1: i2c@48028000 {
- compatible = "ti,omap4-i2c";
- ti,hwmods = "i2c1";
- reg = <0x48028000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <70>;
- dmas = <&edma 58 &edma 59>;
- dma-names = "tx", "rx";
- };
-
- i2c2: i2c@4802a000 {
- compatible = "ti,omap4-i2c";
- ti,hwmods = "i2c2";
- reg = <0x4802a000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <71>;
- dmas = <&edma 60 &edma 61>;
- dma-names = "tx", "rx";
- };
-
- intc: interrupt-controller@48200000 {
- compatible = "ti,dm816-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x48200000 0x1000>;
- };
-
- rtc: rtc@480c0000 {
- compatible = "ti,am3352-rtc", "ti,da830-rtc";
- reg = <0x480c0000 0x1000>;
- interrupts = <75 76>;
- ti,hwmods = "rtc";
- };
-
- mailbox: mailbox@480c8000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x480c8000 0x2000>;
- interrupts = <77>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <12>;
- mbox_dsp: mbox-dsp {
- ti,mbox-tx = <3 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
- };
-
- spinbox: spinbox@480ca000 {
- compatible = "ti,omap4-hwspinlock";
- reg = <0x480ca000 0x2000>;
- ti,hwmods = "spinbox";
- #hwlock-cells = <1>;
- };
-
- mdio: mdio@4a100800 {
- compatible = "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x4a100800 0x100>;
- ti,hwmods = "davinci_mdio";
- bus_freq = <1000000>;
- phy0: ethernet-phy@0 {
- reg = <1>;
- };
- phy1: ethernet-phy@1 {
- reg = <2>;
- };
- };
-
- eth0: ethernet@4a100000 {
- compatible = "ti,dm816-emac";
- ti,hwmods = "emac0";
- reg = <0x4a100000 0x800
- 0x4a100900 0x3700>;
- clocks = <&sysclk24_ck>;
- syscon = <&scm_conf>;
- ti,davinci-ctrl-reg-offset = <0>;
- ti,davinci-ctrl-mod-reg-offset = <0x900>;
- ti,davinci-ctrl-ram-offset = <0x2000>;
- ti,davinci-ctrl-ram-size = <0x2000>;
- interrupts = <40 41 42 43>;
- phy-handle = <&phy0>;
- };
-
- eth1: ethernet@4a120000 {
- compatible = "ti,dm816-emac";
- ti,hwmods = "emac1";
- reg = <0x4a120000 0x4000>;
- clocks = <&sysclk24_ck>;
- syscon = <&scm_conf>;
- ti,davinci-ctrl-reg-offset = <0>;
- ti,davinci-ctrl-mod-reg-offset = <0x900>;
- ti,davinci-ctrl-ram-offset = <0x2000>;
- ti,davinci-ctrl-ram-size = <0x2000>;
- interrupts = <44 45 46 47>;
- phy-handle = <&phy1>;
- };
-
- mcspi1: spi@48030000 {
- compatible = "ti,omap4-mcspi";
- reg = <0x48030000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <65>;
- ti,spi-num-cs = <4>;
- ti,hwmods = "mcspi1";
- dmas = <&edma 16 &edma 17
- &edma 18 &edma 19
- &edma 20 &edma 21
- &edma 22 &edma 23>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
-
- mmc1: mmc@48060000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x48060000 0x11000>;
- ti,hwmods = "mmc1";
- interrupts = <64>;
- dmas = <&edma 24 &edma 25>;
- dma-names = "tx", "rx";
- };
-
- timer1: timer@4802e000 {
- compatible = "ti,dm816-timer";
- reg = <0x4802e000 0x2000>;
- interrupts = <67>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- };
-
- timer2: timer@48040000 {
- compatible = "ti,dm816-timer";
- reg = <0x48040000 0x2000>;
- interrupts = <68>;
- ti,hwmods = "timer2";
- };
-
- timer3: timer@48042000 {
- compatible = "ti,dm816-timer";
- reg = <0x48042000 0x2000>;
- interrupts = <69>;
- ti,hwmods = "timer3";
- };
-
- timer4: timer@48044000 {
- compatible = "ti,dm816-timer";
- reg = <0x48044000 0x2000>;
- interrupts = <92>;
- ti,hwmods = "timer4";
- ti,timer-pwm;
- };
-
- timer5: timer@48046000 {
- compatible = "ti,dm816-timer";
- reg = <0x48046000 0x2000>;
- interrupts = <93>;
- ti,hwmods = "timer5";
- ti,timer-pwm;
- };
-
- timer6: timer@48048000 {
- compatible = "ti,dm816-timer";
- reg = <0x48048000 0x2000>;
- interrupts = <94>;
- ti,hwmods = "timer6";
- ti,timer-pwm;
- };
-
- timer7: timer@4804a000 {
- compatible = "ti,dm816-timer";
- reg = <0x4804a000 0x2000>;
- interrupts = <95>;
- ti,hwmods = "timer7";
- ti,timer-pwm;
- };
-
- uart1: serial@48020000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart1";
- reg = <0x48020000 0x2000>;
- clock-frequency = <48000000>;
- interrupts = <72>;
- dmas = <&edma 26 &edma 27>;
- dma-names = "tx", "rx";
- };
-
- uart2: serial@48022000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart2";
- reg = <0x48022000 0x2000>;
- clock-frequency = <48000000>;
- interrupts = <73>;
- dmas = <&edma 28 &edma 29>;
- dma-names = "tx", "rx";
- };
-
- uart3: serial@48024000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart3";
- reg = <0x48024000 0x2000>;
- clock-frequency = <48000000>;
- interrupts = <74>;
- dmas = <&edma 30 &edma 31>;
- dma-names = "tx", "rx";
- };
-
- /* NOTE: USB needs a transceiver driver for phys to work */
- usb: usb_otg_hs@47401000 {
- compatible = "ti,am33xx-usb";
- reg = <0x47401000 0x400000>;
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
- ti,hwmods = "usb_otg_hs";
-
- usb0: usb@47401000 {
- compatible = "ti,musb-dm816";
- reg = <0x47401400 0x400
- 0x47401000 0x200>;
- reg-names = "mc", "control";
- interrupts = <18>;
- interrupt-names = "mc";
- dr_mode = "host";
- interface-type = <0>;
- phys = <&usb_phy0>;
- phy-names = "usb2-phy";
- mentor,multipoint = <1>;
- mentor,num-eps = <16>;
- mentor,ram-bits = <12>;
- mentor,power = <500>;
-
- dmas = <&cppi41dma 0 0 &cppi41dma 1 0
- &cppi41dma 2 0 &cppi41dma 3 0
- &cppi41dma 4 0 &cppi41dma 5 0
- &cppi41dma 6 0 &cppi41dma 7 0
- &cppi41dma 8 0 &cppi41dma 9 0
- &cppi41dma 10 0 &cppi41dma 11 0
- &cppi41dma 12 0 &cppi41dma 13 0
- &cppi41dma 14 0 &cppi41dma 0 1
- &cppi41dma 1 1 &cppi41dma 2 1
- &cppi41dma 3 1 &cppi41dma 4 1
- &cppi41dma 5 1 &cppi41dma 6 1
- &cppi41dma 7 1 &cppi41dma 8 1
- &cppi41dma 9 1 &cppi41dma 10 1
- &cppi41dma 11 1 &cppi41dma 12 1
- &cppi41dma 13 1 &cppi41dma 14 1>;
- dma-names =
- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
- "rx14", "rx15",
- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
- "tx14", "tx15";
- };
-
- usb1: usb@47401800 {
- compatible = "ti,musb-dm816";
- reg = <0x47401c00 0x400
- 0x47401800 0x200>;
- reg-names = "mc", "control";
- interrupts = <19>;
- interrupt-names = "mc";
- dr_mode = "host";
- interface-type = <0>;
- phys = <&usb_phy1>;
- phy-names = "usb2-phy";
- mentor,multipoint = <1>;
- mentor,num-eps = <16>;
- mentor,ram-bits = <12>;
- mentor,power = <500>;
-
- dmas = <&cppi41dma 15 0 &cppi41dma 16 0
- &cppi41dma 17 0 &cppi41dma 18 0
- &cppi41dma 19 0 &cppi41dma 20 0
- &cppi41dma 21 0 &cppi41dma 22 0
- &cppi41dma 23 0 &cppi41dma 24 0
- &cppi41dma 25 0 &cppi41dma 26 0
- &cppi41dma 27 0 &cppi41dma 28 0
- &cppi41dma 29 0 &cppi41dma 15 1
- &cppi41dma 16 1 &cppi41dma 17 1
- &cppi41dma 18 1 &cppi41dma 19 1
- &cppi41dma 20 1 &cppi41dma 21 1
- &cppi41dma 22 1 &cppi41dma 23 1
- &cppi41dma 24 1 &cppi41dma 25 1
- &cppi41dma 26 1 &cppi41dma 27 1
- &cppi41dma 28 1 &cppi41dma 29 1>;
- dma-names =
- "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
- "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
- "rx14", "rx15",
- "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
- "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
- "tx14", "tx15";
- };
-
- cppi41dma: dma-controller@47402000 {
- compatible = "ti,am3359-cppi41";
- reg = <0x47400000 0x1000
- 0x47402000 0x1000
- 0x47403000 0x1000
- 0x47404000 0x4000>;
- reg-names = "glue", "controller", "scheduler", "queuemgr";
- interrupts = <17>;
- interrupt-names = "glue";
- #dma-cells = <2>;
- #dma-channels = <30>;
- #dma-requests = <256>;
- };
- };
-
- wd_timer2: wd_timer@480c2000 {
- compatible = "ti,omap3-wdt";
- ti,hwmods = "wd_timer";
- reg = <0x480c2000 0x1000>;
- interrupts = <0>;
- };
- };
-};
-
-#include "dm816x-clocks.dtsi"
diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts
index fe1a4aa..70d034c 100644
--- a/arch/arm/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -126,6 +126,8 @@
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f0",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dts b/arch/arm/dts/r8a77970-v3msk-u-boot.dts
new file mode 100644
index 0000000..6ee06d7
--- /dev/null
+++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the V3MSK board
+ *
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#include "r8a77970-v3msk.dts"
+#include "r8a77970-u-boot.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ spi0 = &rpc;
+ };
+
+ cpld {
+ compatible = "renesas,v3msk-cpld";
+ status = "okay";
+ gpio-mdc = <&gpio1 21 0>;
+ gpio-mosi = <&gpio1 22 0>;
+ gpio-miso = <&gpio1 23 0>;
+ gpio-enablez = <&gpio1 19 0>;
+ /* Disable V3MSK Videobox Mini CANFD PHY */
+ gpios = <&gpio0 12 0>, <&gpio0 14 0>;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb0_pins>;
+ pinctrl-names = "default";
+
+};
+
+&phy0 {
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+};
+
+&pfc {
+ avb0_pins: avb {
+ mux {
+ groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
+ function = "avb0";
+ };
+ };
+};
+
+&rpc {
+ num-cs = <1>;
+ status = "okay";
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/r8a77970-v3msk.dts b/arch/arm/dts/r8a77970-v3msk.dts
new file mode 100644
index 0000000..c2b65f8
--- /dev/null
+++ b/arch/arm/dts/r8a77970-v3msk.dts
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the V3M Starter Kit board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77970.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Renesas V3M Starter Kit board";
+ compatible = "renesas,v3msk", "renesas,r8a77970";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ serial0 = &scif0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <&vcc_d3_3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ osc5_clk: osc5-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ vcc_d1_8v: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_D1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_d3_3v: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_D3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_vddq_vin0: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_VDDQ_VIN0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ rx-internal-delay-ps = <1800>;
+ tx-internal-delay-ps = <2000>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&osc5_clk>;
+ clock-names = "du.0", "dclkin.0";
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ hdmi@39{
+ compatible = "adi,adv7511w";
+ #sound-dai-cells = <0>;
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <&vcc_d1_8v>;
+ dvdd-supply = <&vcc_d1_8v>;
+ pvdd-supply = <&vcc_d1_8v>;
+ bgvdd-supply = <&vcc_d1_8v>;
+ dvdd-3v-supply = <&vcc_d3_3v>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in>;
+ };
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-0 = <&mmc_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_d3_3v>;
+ vqmmc-supply = <&vcc_vddq_vin0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pfc {
+ avb_pins: avb0 {
+ groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
+ function = "avb0";
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ mmc_pins: mmc_3_3v {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ power-source = <3300>;
+ };
+
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+};
+
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@40000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@c0000 {
+ reg = <0x000c0000 0x080000>;
+ read-only;
+ };
+ bl2@140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@1c0000 {
+ reg = <0x001c0000 0x460000>;
+ read-only;
+ };
+ uboot@640000 {
+ reg = <0x00640000 0x0c0000>;
+ read-only;
+ };
+ uboot-env@700000 {
+ reg = <0x00700000 0x040000>;
+ read-only;
+ };
+ dtb@740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@7c0000 {
+ reg = <0x007c0000 0x1400000>;
+ };
+ user@1bc0000 {
+ reg = <0x01bc0000 0x2440000>;
+ };
+ };
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
new file mode 100644
index 0000000..d083df6
--- /dev/null
+++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Eagle board
+ *
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#include "r8a77980-v3hsk.dts"
+#include "r8a77980-u-boot.dtsi"
+
+/ {
+ aliases {
+ spi0 = &rpc;
+ };
+};
+
+&rpc {
+ num-cs = <1>;
+ status = "okay";
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ status = "okay";
+ };
+};
+
+&i2c0 {
+ cpld {
+ compatible = "renesas,v3hsk-cpld";
+ reg = <0x70>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts
new file mode 100644
index 0000000..d168b0e
--- /dev/null
+++ b/arch/arm/dts/r8a77980-v3hsk.dts
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the V3H Starter Kit board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Renesas V3H Starter Kit board";
+ compatible = "renesas,v3hsk", "renesas,r8a77980";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &scif0;
+ ethernet0 = &gether;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <&vcc3v3_d5>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0 0x48000000 0 0x78000000>;
+ };
+
+ osc1_clk: osc1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ vcc1v8_d4: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC1V8_D4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc3v3_d5: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3V3_D5";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&osc1_clk>;
+ clock-names = "du.0", "dclkin.0";
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&gether {
+ pinctrl-0 = <&gether_pins>;
+ pinctrl-names = "default";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ #sound-dai-cells = <0>;
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <&vcc1v8_d4>;
+ dvdd-supply = <&vcc1v8_d4>;
+ pvdd-supply = <&vcc1v8_d4>;
+ bgvdd-supply = <&vcc1v8_d4>;
+ dvdd-3v-supply = <&vcc3v3_d5>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in>;
+ };
+ };
+ };
+};
+
+&pfc {
+ gether_pins: gether {
+ groups = "gether_mdio_a", "gether_rgmii",
+ "gether_txcrefclk", "gether_txcrefclk_mega";
+ function = "gether";
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+};
+
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@40000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@c0000 {
+ reg = <0x000c0000 0x080000>;
+ read-only;
+ };
+ bl2@140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@1c0000 {
+ reg = <0x001c0000 0x460000>;
+ read-only;
+ };
+ uboot@640000 {
+ reg = <0x00640000 0x0c0000>;
+ read-only;
+ };
+ uboot-env@700000 {
+ reg = <0x00700000 0x040000>;
+ read-only;
+ };
+ dtb@740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@7c0000 {
+ reg = <0x007c0000 0x1400000>;
+ };
+ user@1bc0000 {
+ reg = <0x01bc0000 0x2440000>;
+ };
+ };
+ };
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
index 9f9837b..9957646 100644
--- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -21,7 +21,7 @@
#size-cells = <0>;
status = "okay";
- flash@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -74,8 +74,24 @@
};
partition@500000 {
- label = "Ex-OPTEE";
- reg = <0x500000 0x200000>;
+ label = "MDATA-Pri";
+ reg = <0x500000 0x1000>;
+ };
+
+ partition@530000 {
+ label = "MDATA-Sec";
+ reg = <0x530000 0x1000>;
+ };
+
+ /* FWU Multi bank update partitions */
+ partition@600000 {
+ label = "FIP-Bank0";
+ reg = <0x600000 0x400000>;
+ };
+
+ partition@a00000 {
+ label = "FIP-Bank1";
+ reg = <0xa00000 0x400000>;
};
};
};
@@ -102,6 +118,33 @@
optee {
status = "okay";
};
+
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-mtd";
+ fwu-mdata-store = <&flash0>;
+ mdata-parts = "MDATA-Pri", "MDATA-Sec";
+
+ fwu-bank0 {
+ id = <0>;
+ label = "FIP-Bank0";
+ fwu-image0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x400000>;
+ uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
+ };
+ };
+ fwu-bank1 {
+ id = <1>;
+ label = "FIP-Bank1";
+ fwu-image0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x400000>;
+ uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0";
+ };
+ };
+ };
};
};
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index ad25b3e..67400c2 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -13,10 +13,6 @@
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/hardware.h>
-#if defined(CONFIG_TI816X)
-#include <asm/arch/clock_ti81xx.h>
-#endif
-
#define LDELAY 1000000
/*CM_<clock_domain>__CLKCTRL */
diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
deleted file mode 100644
index d22d958..0000000
--- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * ti81xx.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- */
-
-#ifndef _CLOCK_TI81XX_H_
-#define _CLOCK_TI81XX_H_
-
-#define PRCM_MOD_EN 0x2
-
-#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
-#define CM_ALWON_BASE (PRCM_BASE + 0x1400)
-
-struct cm_def {
- unsigned int resv0[2];
- unsigned int l3fastclkstctrl;
- unsigned int resv1[1];
- unsigned int pciclkstctrl;
- unsigned int resv2[1];
- unsigned int ducaticlkstctrl;
- unsigned int resv3[1];
- unsigned int emif0clkctrl;
- unsigned int emif1clkctrl;
- unsigned int dmmclkctrl;
- unsigned int fwclkctrl;
- unsigned int resv4[10];
- unsigned int usbclkctrl;
- unsigned int resv5[1];
- unsigned int sataclkctrl;
- unsigned int resv6[4];
- unsigned int ducaticlkctrl;
- unsigned int pciclkctrl;
-};
-
-struct cm_alwon {
- unsigned int l3slowclkstctrl;
- unsigned int ethclkstctrl;
- unsigned int l3medclkstctrl;
- unsigned int mmu_clkstctrl;
- unsigned int mmucfg_clkstctrl;
- unsigned int ocmc0clkstctrl;
-#if defined(CONFIG_TI816X)
- unsigned int ocmc1clkstctrl;
-#endif
- unsigned int mpuclkstctrl;
- unsigned int sysclk4clkstctrl;
- unsigned int sysclk5clkstctrl;
- unsigned int sysclk6clkstctrl;
- unsigned int rtcclkstctrl;
- unsigned int l3fastclkstctrl;
- unsigned int resv0[67];
- unsigned int mcasp0clkctrl;
- unsigned int mcasp1clkctrl;
- unsigned int mcasp2clkctrl;
- unsigned int mcbspclkctrl;
- unsigned int uart0clkctrl;
- unsigned int uart1clkctrl;
- unsigned int uart2clkctrl;
- unsigned int gpio0clkctrl;
- unsigned int gpio1clkctrl;
- unsigned int i2c0clkctrl;
- unsigned int i2c1clkctrl;
-#if defined(CONFIG_TI816X)
- unsigned int resv1[1];
- unsigned int timer1clkctrl;
- unsigned int timer2clkctrl;
- unsigned int timer3clkctrl;
- unsigned int timer4clkctrl;
- unsigned int timer5clkctrl;
- unsigned int timer6clkctrl;
- unsigned int timer7clkctrl;
-#endif
- unsigned int wdtimerclkctrl;
- unsigned int spiclkctrl;
- unsigned int mailboxclkctrl;
- unsigned int spinboxclkctrl;
- unsigned int mmudataclkctrl;
- unsigned int resv2[2];
- unsigned int mmucfgclkctrl;
-#if defined(CONFIG_TI816X)
- unsigned int resv3[1];
- unsigned int sdioclkctrl;
-#endif
- unsigned int ocmc0clkctrl;
-#if defined(CONFIG_TI816X)
- unsigned int ocmc1clkctrl;
-#endif
- unsigned int resv4[2];
- unsigned int controlclkctrl;
- unsigned int resv5[2];
- unsigned int gpmcclkctrl;
- unsigned int ethernet0clkctrl;
- unsigned int ethernet1clkctrl;
- unsigned int mpuclkctrl;
-#if defined(CONFIG_TI816X)
- unsigned int resv6[1];
-#endif
- unsigned int l3clkctrl;
- unsigned int l4hsclkctrl;
- unsigned int l4lsclkctrl;
- unsigned int rtcclkctrl;
- unsigned int tpccclkctrl;
- unsigned int tptc0clkctrl;
- unsigned int tptc1clkctrl;
- unsigned int tptc2clkctrl;
- unsigned int tptc3clkctrl;
-#if defined(CONFIG_TI816X)
- unsigned int sr0clkctrl;
- unsigned int sr1clkctrl;
-#endif
-};
-
-#endif /* _CLOCK_TI81XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 15a5b64..1a03107 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -369,15 +369,9 @@
unsigned int ddrckectrl;
};
-#ifdef CONFIG_TI816X
-void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
- const struct emif_regs *regs,
- const struct dmm_lisa_map_regs *lisa_regs, int nrs);
-#else
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr);
-#endif
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
#endif /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h
deleted file mode 100644
index eb6516d..0000000
--- a/arch/arm/include/asm/arch-am33xx/emac_defs.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Texas Instruments
- *
- * Based on:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.h
- *
- * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#ifdef CONFIG_TI816X
-#define EMAC_BASE_ADDR (0x4A100000)
-#define EMAC_WRAPPER_BASE_ADDR (0x4A100900)
-#define EMAC_WRAPPER_RAM_ADDR (0x4A102000)
-#define EMAC_MDIO_BASE_ADDR (0x4A100800)
-#define EMAC_MDIO_BUS_FREQ (250000000UL)
-#define EMAC_MDIO_CLOCK_FREQ (2000000UL)
-
-typedef volatile unsigned int dv_reg;
-typedef volatile unsigned int *dv_reg_p;
-
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-
-#endif /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 2d7f9da..387f053 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -14,8 +14,6 @@
#include <asm/arch/omap.h>
#ifdef CONFIG_AM33XX
#include <asm/arch/hardware_am33xx.h>
-#elif defined(CONFIG_TI816X)
-#include <asm/arch/hardware_ti816x.h>
#elif defined(CONFIG_AM43XX)
#include <asm/arch/hardware_am43xx.h>
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
deleted file mode 100644
index 78b7948..0000000
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * hardware_ti816x.h
- *
- * TI816x hardware specific header
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- * Based on TI-PSP-04.00.02.14
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __AM33XX_HARDWARE_TI816X_H
-#define __AM33XX_HARDWARE_TI816X_H
-
-/* UART */
-#define UART0_BASE 0x48020000
-#define UART1_BASE 0x48022000
-#define UART2_BASE 0x48024000
-
-/* Watchdog Timer */
-#define WDT_BASE 0x480C2000
-
-/* Control Module Base Address */
-#define CTRL_BASE 0x48140000
-#define CTRL_DEVICE_BASE 0x48140600
-
-/* PRCM Base Address */
-#define PRCM_BASE 0x48180000
-
-#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
-#define PRM_RSTST (PRM_RSTCTRL + 8)
-
-/* VTP Base address */
-#define VTP0_CTRL_ADDR 0x48198358
-#define VTP1_CTRL_ADDR 0x4819A358
-
-/* DDR Base address */
-#define DDR_PHY_CMD_ADDR 0x48198000
-#define DDR_PHY_DATA_ADDR 0x481980C8
-#define DDR_PHY_CMD_ADDR2 0x4819A000
-#define DDR_PHY_DATA_ADDR2 0x4819A0C8
-#define DDR_DATA_REGS_NR 4
-
-
-#define DDRPHY_0_CONFIG_BASE 0x48198000
-#define DDRPHY_1_CONFIG_BASE 0x4819A000
-#define DDRPHY_CONFIG_BASE ((emif == 0) ? \
- DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
-
-/* RTC base address */
-#define RTC_BASE 0x480C0000
-
-#endif /* __AM33XX_HARDWARE_TI816X_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index ed15d15..b1b1896 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -24,9 +24,4 @@
#define OMAP_HSMMC1_BASE 0x48060000
#define OMAP_HSMMC2_BASE 0x481D8000
-#if defined(CONFIG_TI816X)
-#undef MMC_CLOCK_REFERENCE
-#define MMC_CLOCK_REFERENCE 48 /* MHz */
-#endif
-
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 7cf9737..ebb2d30 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -20,8 +20,6 @@
#ifdef CONFIG_AM33XX
#include <asm/arch/mux_am33xx.h>
-#elif defined(CONFIG_TI816X)
-#include <asm/arch/mux_ti816x.h>
#elif defined(CONFIG_AM43XX)
#include <asm/arch/mux_am43xx.h>
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
deleted file mode 100644
index a6a8a98..0000000
--- a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * mux_ti816x.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _MUX_TI816X_H_
-#define _MUX_TI816X_H_
-
-#include <asm/io.h>
-
-#define MUX_CFG(value, offset) \
- __raw_writel(value, (CTRL_BASE + offset));
-
-#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
-#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
-#define PULLUDEN (0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
-#define MODE(val) (val) /* used for Readability */
-
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
- int pincntl1;
- int pincntl2;
- int pincntl3;
- int pincntl4;
- int pincntl5;
- int pincntl6;
- int pincntl7;
- int pincntl8;
- int pincntl9;
- int pincntl10;
- int pincntl11;
- int pincntl12;
- int pincntl13;
- int pincntl14;
- int pincntl15;
- int pincntl16;
- int pincntl17;
- int pincntl18;
- int pincntl19;
- int pincntl20;
- int pincntl21;
- int pincntl22;
- int pincntl23;
- int pincntl24;
- int pincntl25;
- int pincntl26;
- int pincntl27;
- int pincntl28;
- int pincntl29;
- int pincntl30;
- int pincntl31;
- int pincntl32;
- int pincntl33;
- int pincntl34;
- int pincntl35;
- int pincntl36;
- int pincntl37;
- int pincntl38;
- int pincntl39;
- int pincntl40;
- int pincntl41;
- int pincntl42;
- int pincntl43;
- int pincntl44;
- int pincntl45;
- int pincntl46;
- int pincntl47;
- int pincntl48;
- int pincntl49;
- int pincntl50;
- int pincntl51;
- int pincntl52;
- int pincntl53;
- int pincntl54;
- int pincntl55;
- int pincntl56;
- int pincntl57;
- int pincntl58;
- int pincntl59;
- int pincntl60;
- int pincntl61;
- int pincntl62;
- int pincntl63;
- int pincntl64;
- int pincntl65;
- int pincntl66;
- int pincntl67;
- int pincntl68;
- int pincntl69;
- int pincntl70;
- int pincntl71;
- int pincntl72;
- int pincntl73;
- int pincntl74;
- int pincntl75;
- int pincntl76;
- int pincntl77;
- int pincntl78;
- int pincntl79;
- int pincntl80;
- int pincntl81;
- int pincntl82;
- int pincntl83;
- int pincntl84;
- int pincntl85;
- int pincntl86;
- int pincntl87;
- int pincntl88;
- int pincntl89;
- int pincntl90;
- int pincntl91;
- int pincntl92;
- int pincntl93;
- int pincntl94;
- int pincntl95;
- int pincntl96;
- int pincntl97;
- int pincntl98;
- int pincntl99;
- int pincntl100;
- int pincntl101;
- int pincntl102;
- int pincntl103;
- int pincntl104;
- int pincntl105;
- int pincntl106;
- int pincntl107;
- int pincntl108;
- int pincntl109;
- int pincntl110;
- int pincntl111;
- int pincntl112;
- int pincntl113;
- int pincntl114;
- int pincntl115;
- int pincntl116;
- int pincntl117;
- int pincntl118;
- int pincntl119;
- int pincntl120;
- int pincntl121;
- int pincntl122;
- int pincntl123;
- int pincntl124;
- int pincntl125;
- int pincntl126;
- int pincntl127;
- int pincntl128;
- int pincntl129;
- int pincntl130;
- int pincntl131;
- int pincntl132;
- int pincntl133;
- int pincntl134;
- int pincntl135;
- int pincntl136;
- int pincntl137;
- int pincntl138;
- int pincntl139;
- int pincntl140;
- int pincntl141;
- int pincntl142;
- int pincntl143;
- int pincntl144;
- int pincntl145;
- int pincntl146;
- int pincntl147;
- int pincntl148;
- int pincntl149;
- int pincntl150;
- int pincntl151;
- int pincntl152;
- int pincntl153;
- int pincntl154;
- int pincntl155;
- int pincntl156;
- int pincntl157;
- int pincntl158;
- int pincntl159;
- int pincntl160;
- int pincntl161;
- int pincntl162;
- int pincntl163;
- int pincntl164;
- int pincntl165;
- int pincntl166;
- int pincntl167;
- int pincntl168;
- int pincntl169;
- int pincntl170;
- int pincntl171;
- int pincntl172;
- int pincntl173;
- int pincntl174;
- int pincntl175;
- int pincntl176;
- int pincntl177;
- int pincntl178;
- int pincntl179;
- int pincntl180;
- int pincntl181;
- int pincntl182;
- int pincntl183;
- int pincntl184;
- int pincntl185;
- int pincntl186;
- int pincntl187;
- int pincntl188;
- int pincntl189;
- int pincntl190;
- int pincntl191;
- int pincntl192;
- int pincntl193;
- int pincntl194;
- int pincntl195;
- int pincntl196;
- int pincntl197;
- int pincntl198;
- int pincntl199;
- int pincntl200;
- int pincntl201;
- int pincntl202;
- int pincntl203;
- int pincntl204;
- int pincntl205;
- int pincntl206;
- int pincntl207;
- int pincntl208;
- int pincntl209;
- int pincntl210;
- int pincntl211;
- int pincntl212;
- int pincntl213;
- int pincntl214;
- int pincntl215;
- int pincntl216;
- int pincntl217;
- int pincntl218;
- int pincntl219;
- int pincntl220;
- int pincntl221;
- int pincntl222;
- int pincntl223;
- int pincntl224;
- int pincntl225;
- int pincntl226;
- int pincntl227;
- int pincntl228;
- int pincntl229;
- int pincntl230;
- int pincntl231;
- int pincntl232;
- int pincntl233;
- int pincntl234;
- int pincntl235;
- int pincntl236;
- int pincntl237;
- int pincntl238;
- int pincntl239;
- int pincntl240;
- int pincntl241;
- int pincntl242;
- int pincntl243;
- int pincntl244;
- int pincntl245;
- int pincntl246;
- int pincntl247;
- int pincntl248;
- int pincntl249;
- int pincntl250;
- int pincntl251;
- int pincntl252;
- int pincntl253;
- int pincntl254;
- int pincntl255;
- int pincntl256;
- int pincntl257;
- int pincntl258;
- int pincntl259;
- int pincntl260;
- int pincntl261;
- int pincntl262;
- int pincntl263;
- int pincntl264;
- int pincntl265;
- int pincntl266;
- int pincntl267;
- int pincntl268;
- int pincntl269;
- int pincntl270;
- int pincntl271;
- int pincntl272;
- int pincntl273;
- int pincntl274;
- int pincntl275;
- int pincntl276;
- int pincntl277;
- int pincntl278;
- int pincntl279;
- int pincntl280;
- int pincntl281;
- int pincntl282;
- int pincntl283;
- int pincntl284;
- int pincntl285;
- int pincntl286;
- int pincntl287;
- int pincntl288;
- int pincntl289;
- int pincntl290;
- int pincntl291;
- int pincntl292;
- int pincntl293;
- int pincntl294;
- int pincntl295;
- int pincntl296;
- int pincntl297;
- int pincntl298;
- int pincntl299;
- int pincntl300;
- int pincntl301;
- int pincntl302;
- int pincntl303;
- int pincntl304;
- int pincntl305;
- int pincntl306;
- int pincntl307;
- int pincntl308;
- int pincntl309;
- int pincntl310;
- int pincntl311;
- int pincntl312;
- int pincntl313;
- int pincntl314;
- int pincntl315;
- int pincntl316;
- int pincntl317;
- int pincntl318;
- int pincntl319;
- int pincntl320;
- int pincntl321;
- int pincntl322;
- int pincntl323;
-};
-
-#endif /* endif _MUX_TI816X_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 4c71dbf..53046de 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -20,10 +20,6 @@
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define NON_SECURE_SRAM_IMG_END 0x4030B800
-#elif defined(CONFIG_TI816X)
-#define NON_SECURE_SRAM_START 0x40300000
-#define NON_SECURE_SRAM_END 0x40320000
-#define NON_SECURE_SRAM_IMG_END 0x4031B800
#elif defined(CONFIG_AM43XX)
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40340000
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 6bd3ca0..9ddb346 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -9,19 +9,7 @@
#define BOOT_DEVICE_NONE 0x00
#define BOOT_DEVICE_MMC2_2 0xFF
-#if defined(CONFIG_TI816X)
-#define BOOT_DEVICE_XIP 0x01
-#define BOOT_DEVICE_XIPWAIT 0x02
-#define BOOT_DEVICE_NAND 0x03
-#define BOOT_DEVICE_ONENAND 0x04
-#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */
-#define BOOT_DEVICE_MMC1 0x06
-#define BOOT_DEVICE_UART 0x43
-#define BOOT_DEVICE_USB 0x45
-
-#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
-#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
-#elif defined(CONFIG_AM33XX)
+#if defined(CONFIG_AM33XX)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x05
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
deleted file mode 100644
index fd8dad3..0000000
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014-2017 Broadcom.
- */
-
-#ifndef __ARCH_CONFIGS_H
-#define __ARCH_CONFIGS_H
-
-#include <asm/iproc-common/configs.h>
-
-/* uArchitecture specifics */
-
-/* Serial Info */
-#define CFG_SYS_NS16550_CLK 100000000
-#define CFG_SYS_NS16550_CLK_DIV 54
-#define CFG_SYS_NS16550_COM3 0x18023000
-
-#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h
deleted file mode 100644
index 0d4baf3..0000000
--- a/arch/arm/include/asm/arch-bcmnsp/configs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#ifndef __ARCH_CONFIGS_H
-#define __ARCH_CONFIGS_H
-
-#include <asm/iproc-common/configs.h>
-
-/* uArchitecture specifics */
-
-/* Serial Info */
-#define CFG_SYS_NS16550_CLK 0x03b9aca0
-#define CFG_SYS_NS16550_COM1 0x18000300
-
-#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index 55b46af..4ed8e95 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -4,7 +4,7 @@
*/
#ifndef __ARCH_IMX8M_SYS_PROTO_H
-#define __ARCH_NMX8M_SYS_PROTO_H
+#define __ARCH_IMX8M_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch/imx-regs.h>
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 5bbae21..95bf753 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -4,7 +4,7 @@
*/
#ifndef __ARCH_IMX8ULP_SYS_PROTO_H
-#define __ARCH_NMX8ULP_SYS_PROTO_H
+#define __ARCH_IMX8ULP_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index ba97f92..2f7a129 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -4,7 +4,7 @@
*/
#ifndef __ARCH_IMX9_SYS_PROTO_H
-#define __ARCH_NMX9_SYS_PROTO_H
+#define __ARCH_IMX9_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>
diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h
deleted file mode 100644
index 14f7c76..0000000
--- a/arch/arm/include/asm/arch-imxrt/imxrt.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef _ASM_ARCH_IMXRT_H
-#define _ASM_ARCH_IMXRT_H
-
-#endif /* _ASM_ARCH_IMXRT_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
deleted file mode 100644
index 762bbee..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LPC32xx GPIO interface macro for pin mapping.
- *
- * (C) Copyright 2015 DENX Software Engineering GmbH
- * Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
- */
-
-#ifndef _LPC32XX_GPIO_GRP_H
-#define _LPC32XX_GPIO_GRP_H
-
-/*
- * Macro to map the pin for the lpc32xx_gpio driver.
- * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
- * mapping is done per register, as group of 32.
- * (see drivers/gpio/lpc32xx_gpio.c for details).
- * - macros can be use with the following pins:
- * P0.0 - P0.7
- * P1.0 - P1.23
- * P2.0 - P2.12
- * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
- * P3 GPO_0 - GPO_23
- * P3 GPIO_0 - GPIO_5 (output register only)
- */
-#define LPC32XX_GPIO_P0_GRP 0
-#define LPC32XX_GPIO_P1_GRP 32
-#define LPC32XX_GPIO_P2_GRP 64
-#define LPC32XX_GPO_P3_GRP 96
-#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
-#define LPC32XX_GPI_P3_GRP 128
-
-/*
- * A specific GPIO can be selected with this macro
- * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
- * See the LPC32x0 User's guide for GPIO group numbers
- */
-#define LPC32XX_GPIO(x, y) ((x) + (y))
-
-#endif /* _LPC32XX_GPIO_GRP_H */
diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h
deleted file mode 100644
index 52fb0ab..0000000
--- a/arch/arm/include/asm/arch-mx27/mxcmmc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#ifndef ASM_ARCH_MXCMMC_H
-#define ASM_ARCH_MXCMMC_H
-
-int mxc_mmc_init(struct bd_info *bis);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h
deleted file mode 100644
index b55a54c..0000000
--- a/arch/arm/include/asm/arch-mx6/opos6ul.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Armadeus Systems
- */
-
-#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__
-#define __ARCH_ARM_MX6UL_OPOS6UL_H__
-
-int opos6ul_board_late_init(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
deleted file mode 100644
index d89cf27..0000000
--- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Freescale MXS UARTAPP Register Definitions
- *
- * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#ifndef __ARCH_ARM___MXS_UARTAPP_H
-#define __ARCH_ARM___MXS_UARTAPP_H
-
-#include <asm/mach-imx/regs-common.h>
-
-#ifndef __ASSEMBLY__
-struct mxs_uartapp_regs {
- mxs_reg_32(hw_uartapp_ctrl0)
- mxs_reg_32(hw_uartapp_ctrl1)
- mxs_reg_32(hw_uartapp_ctrl2)
- mxs_reg_32(hw_uartapp_linectrl)
- mxs_reg_32(hw_uartapp_linectrl2)
- mxs_reg_32(hw_uartapp_intr)
- mxs_reg_32(hw_uartapp_data)
- mxs_reg_32(hw_uartapp_stat)
- mxs_reg_32(hw_uartapp_debug)
- mxs_reg_32(hw_uartapp_version)
- mxs_reg_32(hw_uartapp_autobaud)
-};
-#endif
-
-#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
-#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
-#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
-#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
-#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
-#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
-#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
-#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
-#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
-
-#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
-
-#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
-#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
-
-#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
-#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
-#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
-#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
-#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
-#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
-#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
-#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
-#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
-#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
-
-#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
-#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
-#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
-#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
-#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
-#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
-#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
-#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
-#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
-#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
-#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
-#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
-#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
-
-#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
-#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
-#define UARTAPP_CTRL2_UARTEN_MASK 0x01
-
-#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
-#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
-#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
-
-#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
-#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
-#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
-
-#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
-#define UARTAPP_LINECTRL_WLEN_OFFSET 5
-#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
-#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
-#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
-#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
-#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
-
-#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
-#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
-#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
-#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
-#define UARTAPP_LINECTRL_BRK_MASK 1
-
-#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
-#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
-#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
-
-#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
-#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
-#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
-
-#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
-#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
-#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
-#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
-#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
-#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
-#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
-
-#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
-#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
-#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
-#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
-
-#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
-#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
-#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
-#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
-#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
-#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
-#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
-#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
-#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
-#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
-#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
-#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
-
-#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
-#define UARTAPP_INTR_OEIS_MASK (1 << 10)
-#define UARTAPP_INTR_BEIS_MASK (1 << 9)
-#define UARTAPP_INTR_PEIS_MASK (1 << 8)
-#define UARTAPP_INTR_FEIS_MASK (1 << 7)
-#define UARTAPP_INTR_RTIS_MASK (1 << 6)
-#define UARTAPP_INTR_TXIS_MASK (1 << 5)
-#define UARTAPP_INTR_RXIS_MASK (1 << 4)
-#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
-#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
-#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
-#define UARTAPP_INTR_RIMIS_MASK 0x1
-
-#define UARTAPP_DATA_DATA_OFFSET 0
-#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
-#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
-#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
-#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
-
-#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
-#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
-#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
-
-#define UARTAPP_STAT_BUSY_MASK (1 << 29)
-#define UARTAPP_STAT_CTS_MASK (1 << 28)
-#define UARTAPP_STAT_TXFE_MASK (1 << 27)
-#define UARTAPP_STAT_RXFF_MASK (1 << 26)
-#define UARTAPP_STAT_TXFF_MASK (1 << 25)
-#define UARTAPP_STAT_RXFE_MASK (1 << 24)
-#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
-#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
-
-#define UARTAPP_STAT_OERR_MASK (1 << 19)
-#define UARTAPP_STAT_BERR_MASK (1 << 18)
-#define UARTAPP_STAT_PERR_MASK (1 << 17)
-#define UARTAPP_STAT_FERR_MASK (1 << 16)
-#define UARTAPP_STAT_RXCOUNT_OFFSET 0
-#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
-
-#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
-#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
-
-#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
-#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
-
-#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
-#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
-#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
-#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
-#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
-#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
-
-#define UARTAPP_VERSION_MAJOR_OFFSET 24
-#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
-
-#define UARTAPP_VERSION_MINOR_OFFSET 16
-#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
-
-#define UARTAPP_VERSION_STEP_OFFSET 0
-#define UARTAPP_VERSION_STEP_MASK 0xFFFF
-
-#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
-#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
-
-#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
-#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
-
-#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
-#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
-#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
-#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
-#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
-#endif /* __ARCH_ARM___UARTAPP_H */
diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h
deleted file mode 100644
index 7b3c6c7..0000000
--- a/arch/arm/include/asm/arch-omap3/omap3-regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
- */
-
-#ifndef _OMAP3_REGS_H
-#define _OMAP3_REGS_H
-
-/*
- * Register definitions for OMAP3 processors.
- */
-
-/*
- * GPMC_CONFIG1 - GPMC_CONFIG7
- */
-
-/* Values for GPMC_CONFIG1 - signal control parameters */
-#define WRAPBURST (1 << 31)
-#define READMULTIPLE (1 << 30)
-#define READTYPE (1 << 29)
-#define WRITEMULTIPLE (1 << 28)
-#define WRITETYPE (1 << 27)
-#define CLKACTIVATIONTIME(x) (((x) & 3) << 25)
-#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23)
-#define WAITREADMONITORING (1 << 22)
-#define WAITWRITEMONITORING (1 << 21)
-#define WAITMONITORINGTIME(x) (((x) & 3) << 18)
-#define WAITPINSELECT(x) (((x) & 3) << 16)
-#define DEVICESIZE(x) (((x) & 3) << 12)
-#define DEVICESIZE_8BIT DEVICESIZE(0)
-#define DEVICESIZE_16BIT DEVICESIZE(1)
-#define DEVICETYPE(x) (((x) & 3) << 10)
-#define DEVICETYPE_NOR DEVICETYPE(0)
-#define DEVICETYPE_NAND DEVICETYPE(2)
-#define MUXADDDATA (1 << 9)
-#define TIMEPARAGRANULARITY (1 << 4)
-#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0)
-
-/* Values for GPMC_CONFIG2 - CS timing */
-#define CSWROFFTIME(x) (((x) & 0x1f) << 16)
-#define CSRDOFFTIME(x) (((x) & 0x1f) << 8)
-#define CSEXTRADELAY (1 << 7)
-#define CSONTIME(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG3 - nADV timing */
-#define ADVWROFFTIME(x) (((x) & 0x1f) << 16)
-#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8)
-#define ADVEXTRADELAY (1 << 7)
-#define ADVONTIME(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG4 - nWE and nOE timing */
-#define WEOFFTIME(x) (((x) & 0x1f) << 24)
-#define WEEXTRADELAY (1 << 23)
-#define WEONTIME(x) (((x) & 0xf) << 16)
-#define OEOFFTIME(x) (((x) & 0x1f) << 8)
-#define OEEXTRADELAY (1 << 7)
-#define OEONTIME(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
-#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24)
-#define RDACCESSTIME(x) (((x) & 0x1f) << 16)
-#define WRCYCLETIME(x) (((x) & 0x1f) << 8)
-#define RDCYCLETIME(x) (((x) & 0x1f) << 0)
-
-/* Values for GPMC_CONFIG6 - misc timings */
-#define WRACCESSTIME(x) (((x) & 0x1f) << 24)
-#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16)
-#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8)
-#define CYCLE2CYCLESAMECSEN (1 << 7)
-#define CYCLE2CYCLEDIFFCSEN (1 << 6)
-#define BUSTURNAROUND(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG7 - CS address mapping configuration */
-#define MASKADDRESS(x) (((x) & 0xf) << 8)
-#define CSVALID (1 << 6)
-#define BASEADDRESS(x) (((x) & 0x3f) << 0)
-
-#endif /* _OMAP3_REGS_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
deleted file mode 100644
index 2460646..0000000
--- a/arch/arm/include/asm/arch-omap5/mux_omap5.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff <r-woodruff2@ti.com>
- * Aneesh V <aneesh@ti.com>
- * Balaji Krishnamoorthy <balajitk@ti.com>
- */
-#ifndef _MUX_OMAP5_H_
-#define _MUX_OMAP5_H_
-
-#include <asm/types.h>
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_PD (1 << 12)
-#define OFF_PU (3 << 12)
-#define OFF_OUT_PTD (0 << 10)
-#define OFF_OUT_PTU (2 << 10)
-#define OFF_IN (1 << 10)
-#define OFF_OUT (0 << 10)
-#define OFF_EN (1 << 9)
-#else
-#define OFF_PD (0 << 12)
-#define OFF_PU (0 << 12)
-#define OFF_OUT_PTD (0 << 10)
-#define OFF_OUT_PTU (0 << 10)
-#define OFF_IN (0 << 10)
-#define OFF_OUT (0 << 10)
-#define OFF_EN (0 << 9)
-#endif
-
-#define IEN (1 << 8)
-#define IDIS (0 << 8)
-#define PTU (3 << 3)
-#define PTD (1 << 3)
-#define EN (1 << 3)
-#define DIS (0 << 3)
-
-#define M0 0
-#define M1 1
-#define M2 2
-#define M3 3
-#define M4 4
-#define M5 5
-#define M6 6
-#define M7 7
-
-#define SAFE_MODE M7
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
-#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
-#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
-#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
-#else
-#define OFF_IN_PD 0
-#define OFF_IN_PU 0
-#define OFF_OUT_PD 0
-#define OFF_OUT_PU 0
-#endif
-
-#define CORE_REVISION 0x0000
-#define CORE_HWINFO 0x0004
-#define CORE_SYSCONFIG 0x0010
-#define EMMC_CLK 0x0040
-#define EMMC_CMD 0x0042
-#define EMMC_DATA0 0x0044
-#define EMMC_DATA1 0x0046
-#define EMMC_DATA2 0x0048
-#define EMMC_DATA3 0x004a
-#define EMMC_DATA4 0x004c
-#define EMMC_DATA5 0x004e
-#define EMMC_DATA6 0x0050
-#define EMMC_DATA7 0x0052
-#define C2C_CLKOUT0 0x0054
-#define C2C_CLKOUT1 0x0056
-#define C2C_CLKIN0 0x0058
-#define C2C_CLKIN1 0x005a
-#define C2C_DATAIN0 0x005c
-#define C2C_DATAIN1 0x005e
-#define C2C_DATAIN2 0x0060
-#define C2C_DATAIN3 0x0062
-#define C2C_DATAIN4 0x0064
-#define C2C_DATAIN5 0x0066
-#define C2C_DATAIN6 0x0068
-#define C2C_DATAIN7 0x006a
-#define C2C_DATAOUT0 0x006c
-#define C2C_DATAOUT1 0x006e
-#define C2C_DATAOUT2 0x0070
-#define C2C_DATAOUT3 0x0072
-#define C2C_DATAOUT4 0x0074
-#define C2C_DATAOUT5 0x0076
-#define C2C_DATAOUT6 0x0078
-#define C2C_DATAOUT7 0x007a
-#define C2C_DATA8 0x007c
-#define C2C_DATA9 0x007e
-#define C2C_DATA10 0x0080
-#define C2C_DATA11 0x0082
-#define C2C_DATA12 0x0084
-#define C2C_DATA13 0x0086
-#define C2C_DATA14 0x0088
-#define C2C_DATA15 0x008a
-#define LLIA_WAKEREQOUT 0x008c
-#define LLIB_WAKEREQOUT 0x008e
-#define HSI1_ACREADY 0x0090
-#define HSI1_CAREADY 0x0092
-#define HSI1_ACWAKE 0x0094
-#define HSI1_CAWAKE 0x0096
-#define HSI1_ACFLAG 0x0098
-#define HSI1_ACDATA 0x009a
-#define HSI1_CAFLAG 0x009c
-#define HSI1_CADATA 0x009e
-#define UART1_TX 0x00a0
-#define UART1_CTS 0x00a2
-#define UART1_RX 0x00a4
-#define UART1_RTS 0x00a6
-#define HSI2_CAREADY 0x00a8
-#define HSI2_ACREADY 0x00aa
-#define HSI2_CAWAKE 0x00ac
-#define HSI2_ACWAKE 0x00ae
-#define HSI2_CAFLAG 0x00b0
-#define HSI2_CADATA 0x00b2
-#define HSI2_ACFLAG 0x00b4
-#define HSI2_ACDATA 0x00b6
-#define UART2_RTS 0x00b8
-#define UART2_CTS 0x00ba
-#define UART2_RX 0x00bc
-#define UART2_TX 0x00be
-#define USBB1_HSIC_STROBE 0x00c0
-#define USBB1_HSIC_DATA 0x00c2
-#define USBB2_HSIC_STROBE 0x00c4
-#define USBB2_HSIC_DATA 0x00c6
-#define TIMER10_PWM_EVT 0x00c8
-#define DSIPORTA_TE0 0x00ca
-#define DSIPORTA_LANE0X 0x00cc
-#define DSIPORTA_LANE0Y 0x00ce
-#define DSIPORTA_LANE1X 0x00d0
-#define DSIPORTA_LANE1Y 0x00d2
-#define DSIPORTA_LANE2X 0x00d4
-#define DSIPORTA_LANE2Y 0x00d6
-#define DSIPORTA_LANE3X 0x00d8
-#define DSIPORTA_LANE3Y 0x00da
-#define DSIPORTA_LANE4X 0x00dc
-#define DSIPORTA_LANE4Y 0x00de
-#define DSIPORTC_LANE0X 0x00e0
-#define DSIPORTC_LANE0Y 0x00e2
-#define DSIPORTC_LANE1X 0x00e4
-#define DSIPORTC_LANE1Y 0x00e6
-#define DSIPORTC_LANE2X 0x00e8
-#define DSIPORTC_LANE2Y 0x00ea
-#define DSIPORTC_LANE3X 0x00ec
-#define DSIPORTC_LANE3Y 0x00ee
-#define DSIPORTC_LANE4X 0x00f0
-#define DSIPORTC_LANE4Y 0x00f2
-#define DSIPORTC_TE0 0x00f4
-#define TIMER9_PWM_EVT 0x00f6
-#define I2C4_SCL 0x00f8
-#define I2C4_SDA 0x00fa
-#define MCSPI2_CLK 0x00fc
-#define MCSPI2_SIMO 0x00fe
-#define MCSPI2_SOMI 0x0100
-#define MCSPI2_CS0 0x0102
-#define RFBI_DATA15 0x0104
-#define RFBI_DATA14 0x0106
-#define RFBI_DATA13 0x0108
-#define RFBI_DATA12 0x010a
-#define RFBI_DATA11 0x010c
-#define RFBI_DATA10 0x010e
-#define RFBI_DATA9 0x0110
-#define RFBI_DATA8 0x0112
-#define RFBI_DATA7 0x0114
-#define RFBI_DATA6 0x0116
-#define RFBI_DATA5 0x0118
-#define RFBI_DATA4 0x011a
-#define RFBI_DATA3 0x011c
-#define RFBI_DATA2 0x011e
-#define RFBI_DATA1 0x0120
-#define RFBI_DATA0 0x0122
-#define RFBI_WE 0x0124
-#define RFBI_CS0 0x0126
-#define RFBI_A0 0x0128
-#define RFBI_RE 0x012a
-#define RFBI_HSYNC0 0x012c
-#define RFBI_TE_VSYNC0 0x012e
-#define GPIO6_182 0x0130
-#define GPIO6_183 0x0132
-#define GPIO6_184 0x0134
-#define GPIO6_185 0x0136
-#define GPIO6_186 0x0138
-#define GPIO6_187 0x013a
-#define HDMI_CEC 0x013c
-#define HDMI_HPD 0x013e
-#define HDMI_DDC_SCL 0x0140
-#define HDMI_DDC_SDA 0x0142
-#define CSIPORTC_LANE0X 0x0144
-#define CSIPORTC_LANE0Y 0x0146
-#define CSIPORTC_LANE1X 0x0148
-#define CSIPORTC_LANE1Y 0x014a
-#define CSIPORTB_LANE0X 0x014c
-#define CSIPORTB_LANE0Y 0x014e
-#define CSIPORTB_LANE1X 0x0150
-#define CSIPORTB_LANE1Y 0x0152
-#define CSIPORTB_LANE2X 0x0154
-#define CSIPORTB_LANE2Y 0x0156
-#define CSIPORTA_LANE0X 0x0158
-#define CSIPORTA_LANE0Y 0x015a
-#define CSIPORTA_LANE1X 0x015c
-#define CSIPORTA_LANE1Y 0x015e
-#define CSIPORTA_LANE2X 0x0160
-#define CSIPORTA_LANE2Y 0x0162
-#define CSIPORTA_LANE3X 0x0164
-#define CSIPORTA_LANE3Y 0x0166
-#define CSIPORTA_LANE4X 0x0168
-#define CSIPORTA_LANE4Y 0x016a
-#define CAM_SHUTTER 0x016c
-#define CAM_STROBE 0x016e
-#define CAM_GLOBALRESET 0x0170
-#define TIMER11_PWM_EVT 0x0172
-#define TIMER5_PWM_EVT 0x0174
-#define TIMER6_PWM_EVT 0x0176
-#define TIMER8_PWM_EVT 0x0178
-#define I2C3_SCL 0x017a
-#define I2C3_SDA 0x017c
-#define GPIO8_233 0x017e
-#define GPIO8_234 0x0180
-#define ABE_CLKS 0x0182
-#define ABEDMIC_DIN1 0x0184
-#define ABEDMIC_DIN2 0x0186
-#define ABEDMIC_DIN3 0x0188
-#define ABEDMIC_CLK1 0x018a
-#define ABEDMIC_CLK2 0x018c
-#define ABEDMIC_CLK3 0x018e
-#define ABESLIMBUS1_CLOCK 0x0190
-#define ABESLIMBUS1_DATA 0x0192
-#define ABEMCBSP2_DR 0x0194
-#define ABEMCBSP2_DX 0x0196
-#define ABEMCBSP2_FSX 0x0198
-#define ABEMCBSP2_CLKX 0x019a
-#define ABEMCPDM_UL_DATA 0x019c
-#define ABEMCPDM_DL_DATA 0x019e
-#define ABEMCPDM_FRAME 0x01a0
-#define ABEMCPDM_LB_CLK 0x01a2
-#define WLSDIO_CLK 0x01a4
-#define WLSDIO_CMD 0x01a6
-#define WLSDIO_DATA0 0x01a8
-#define WLSDIO_DATA1 0x01aa
-#define WLSDIO_DATA2 0x01ac
-#define WLSDIO_DATA3 0x01ae
-#define UART5_RX 0x01b0
-#define UART5_TX 0x01b2
-#define UART5_CTS 0x01b4
-#define UART5_RTS 0x01b6
-#define I2C2_SCL 0x01b8
-#define I2C2_SDA 0x01ba
-#define MCSPI1_CLK 0x01bc
-#define MCSPI1_SOMI 0x01be
-#define MCSPI1_SIMO 0x01c0
-#define MCSPI1_CS0 0x01c2
-#define MCSPI1_CS1 0x01c4
-#define I2C5_SCL 0x01c6
-#define I2C5_SDA 0x01c8
-#define PERSLIMBUS2_CLOCK 0x01ca
-#define PERSLIMBUS2_DATA 0x01cc
-#define UART6_TX 0x01ce
-#define UART6_RX 0x01d0
-#define UART6_CTS 0x01d2
-#define UART6_RTS 0x01d4
-#define UART3_CTS_RCTX 0x01d6
-#define UART3_RTS_IRSD 0x01d8
-#define UART3_TX_IRTX 0x01da
-#define UART3_RX_IRRX 0x01dc
-#define USBB3_HSIC_STROBE 0x01de
-#define USBB3_HSIC_DATA 0x01e0
-#define SDCARD_CLK 0x01e2
-#define SDCARD_CMD 0x01e4
-#define SDCARD_DATA2 0x01e6
-#define SDCARD_DATA3 0x01e8
-#define SDCARD_DATA0 0x01ea
-#define SDCARD_DATA1 0x01ec
-#define USBD0_HS_DP 0x01ee
-#define USBD0_HS_DM 0x01f0
-#define I2C1_PMIC_SCL 0x01f2
-#define I2C1_PMIC_SDA 0x01f4
-#define USBD0_SS_RX 0x01f6
-
-#define LLIA_WAKEREQIN 0x0040
-#define LLIB_WAKEREQIN 0x0042
-#define DRM_EMU0 0x0044
-#define DRM_EMU1 0x0046
-#define JTAG_NTRST 0x0048
-#define JTAG_TCK 0x004a
-#define JTAG_RTCK 0x004c
-#define JTAG_TMSC 0x004e
-#define JTAG_TDI 0x0050
-#define JTAG_TDO 0x0052
-#define SYS_32K 0x0054
-#define FREF_CLK_IOREQ 0x0056
-#define FREF_CLK0_OUT 0x0058
-#define FREF_CLK1_OUT 0x005a
-#define FREF_CLK2_OUT 0x005c
-#define FREF_CLK2_REQ 0x005e
-#define FREF_CLK1_REQ 0x0060
-#define SYS_NRESPWRON 0x0062
-#define SYS_NRESWARM 0x0064
-#define SYS_PWR_REQ 0x0066
-#define SYS_NIRQ1 0x0068
-#define SYS_NIRQ2 0x006a
-#define SR_PMIC_SCL 0x006c
-#define SR_PMIC_SDA 0x006e
-#define SYS_BOOT0 0x0070
-#define SYS_BOOT1 0x0072
-#define SYS_BOOT2 0x0074
-#define SYS_BOOT3 0x0076
-#define SYS_BOOT4 0x0078
-#define SYS_BOOT5 0x007a
-
-#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/boot0-linux-kernel-header.h b/arch/arm/include/asm/boot0-linux-kernel-header.h
index c6cd76f..c930fea 100644
--- a/arch/arm/include/asm/boot0-linux-kernel-header.h
+++ b/arch/arm/include/asm/boot0-linux-kernel-header.h
@@ -31,8 +31,6 @@
.long \sym\()_hi32
.endm
-.globl _start
-_start:
/*
* DO NOT MODIFY. Image header expected by Linux boot-loaders.
*/
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
deleted file mode 100644
index ce831bc..0000000
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#ifndef __IPROC_COMMON_CONFIGS_H
-#define __IPROC_COMMON_CONFIGS_H
-
-#include <linux/stringify.h>
-
-/* Memory Info */
-#define CFG_SYS_SDRAM_BASE 0x61000000
-
-#endif /* __IPROC_COMMON_CONFIGS_H */
diff --git a/arch/arm/include/asm/iproc-common/iproc_sdhci.h b/arch/arm/include/asm/iproc-common/iproc_sdhci.h
deleted file mode 100644
index 4e29921..0000000
--- a/arch/arm/include/asm/iproc-common/iproc_sdhci.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: <SPDX License Expression> */
-/*
- * Copyright 2019 Broadcom
- *
- */
-
-#ifndef __IPROC_SDHCI_H
-#define __IPROC_SDHCI_H
-
-int iproc_sdhci_init(int dev_index, u32 quirks);
-
-#endif
diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h
deleted file mode 100644
index 22db651..0000000
--- a/arch/arm/include/asm/kona-common/kona_sdhci.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#ifndef __KONA_SDHCI_H
-#define __KONA_SDHCI_H
-
-int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
-
-#endif
diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h
index dbe4b4e..73bf25b 100644
--- a/arch/arm/include/asm/linkage.h
+++ b/arch/arm/include/asm/linkage.h
@@ -1,7 +1,7 @@
#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
-#define __ALIGN .align 0
-#define __ALIGN_STR ".align 0"
+#define __ALIGN .p2align 2
+#define __ALIGN_STR ".p2align 2"
#endif
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
index 0a228fb..7fb482a 100644
--- a/arch/arm/include/asm/unaligned.h
+++ b/arch/arm/include/asm/unaligned.h
@@ -1,19 +1,2 @@
-#ifndef _ASM_ARM_UNALIGNED_H
-#define _ASM_ARM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-/*
- * Select endianness
- */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-#else
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-#endif
-
-#endif /* _ASM_ARM_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h
deleted file mode 100644
index ba88c44..0000000
--- a/arch/arm/mach-at91/include/mach/at91_rtt.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Real-time Timer
- * Based on AT91SAM9XE datasheet
- */
-
-#ifndef AT91_RTT_H
-#define AT91_RTT_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rtt {
- u32 mr; /* Mode Register RW 0x00008000 */
- u32 ar; /* Alarm Register RW 0xFFFFFFFF */
- u32 vr; /* Value Register RO 0x00000000 */
- u32 sr; /* Status Register RO 0x00000000 */
-} at91_rtt_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RTT_MR_RTPRES 0x0000ffff
-#define AT91_RTT_MR_ALMIEN 0x00010000
-#define AT91_RTT_RTTINCIEN 0x00020000
-#define AT91_RTT_RTTRST 0x00040000
-
-#define AT91_RTT_SR_ALMS 0x00000001
-#define AT91_RTT_SR_RTTINC 0x00000002
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h
deleted file mode 100644
index 7419a58..0000000
--- a/arch/arm/mach-davinci/include/mach/aintc_defs.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-#ifndef _DV_AINTC_DEFS_H_
-#define _DV_AINTC_DEFS_H_
-
-struct dv_aintc_regs {
- unsigned int fiq0; /* 0x00 */
- unsigned int fiq1; /* 0x04 */
- unsigned int irq0; /* 0x08 */
- unsigned int irq1; /* 0x0c */
- unsigned int fiqentry; /* 0x10 */
- unsigned int irqentry; /* 0x14 */
- unsigned int eint0; /* 0x18 */
- unsigned int eint1; /* 0x1c */
- unsigned int intctl; /* 0x20 */
- unsigned int eabase; /* 0x24 */
- unsigned char rsvd0[8]; /* 0x28 */
- unsigned int intpri0; /* 0x30 */
- unsigned int intpri1; /* 0x34 */
- unsigned int intpri2; /* 0x38 */
- unsigned int intpri3; /* 0x3c */
- unsigned int intpri4; /* 0x40 */
- unsigned int intpri5; /* 0x44 */
- unsigned int intpri6; /* 0x48 */
- unsigned int intpri7; /* 0x4c */
-};
-
-#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
-
-#define DV_AINTC_INTCTL_IDMODE (1 << 2)
-
-#endif /* _DV_AINTC_DEFS_H_ */
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 906f538..00d6ad8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -54,7 +54,7 @@
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
-obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_$(SPL_)SATA) += sata.o
obj-$(CONFIG_IMX_HAB) += hab.o
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 026c4f9..787fe92 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -15,6 +15,15 @@
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
+#define RTC_BASE_ADDRESS 0x2b1f0000
+#define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18)
+#define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70)
+#define REG_K3RTC_KICK1 (RTC_BASE_ADDRESS + 0x74)
+
+/* Magic values for lock/unlock */
+#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13
+#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -71,6 +80,42 @@
writel(stat, CTRLMMR_MCU_RST_CTRL);
}
+#if defined(CONFIG_CPU_V7R)
+
+/*
+ * RTC Erratum i2327 Workaround for Silicon Revision 1
+ *
+ * Due to a bug in initial synchronization out of cold power on,
+ * IRQ status can get locked infinitely if we do not unlock RTC
+ *
+ * This workaround *must* be applied within 1 second of power on,
+ * So, this is closest point to be able to guarantee the max
+ * timing.
+ *
+ * https://www.ti.com/lit/er/sprz487c/sprz487c.pdf
+ */
+void rtc_erratumi2327_init(void)
+{
+ u32 counter;
+
+ /*
+ * If counter has gone past 1, nothing we can do, leave
+ * system locked! This is the only way we know if RTC
+ * can be used for all practical purposes.
+ */
+ counter = readl(REG_K3RTC_S_CNT_LSW);
+ if (counter > 1)
+ return;
+ /*
+ * Need to set this up at the very start
+ * MUST BE DONE under 1 second of boot.
+ */
+ writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0);
+ writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1);
+ return;
+}
+#endif
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
@@ -78,6 +123,7 @@
#if defined(CONFIG_CPU_V7R)
setup_k3_mpu_regions();
+ rtc_erratumi2327_init();
#endif
/*
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 88687c2..f8087d2 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -222,11 +222,59 @@
#endif /* CONFIG_SOC_K3_J721S2 */
-#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \
- defined(CONFIG_SOC_K3_AM62A7)
+#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
+
+/* ToDo: Add 64bit IO */
+struct mm_region am62_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x1E780000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xA0000000UL,
+ .phys = 0xA0000000UL,
+ .size = 0x60000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+
+ }, {
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x500000000UL,
+ .phys = 0x500000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = am62_mem_map;
+#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+
+#ifdef CONFIG_SOC_K3_AM642
+
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
/* ToDo: Add 64bit IO */
struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
@@ -240,7 +288,13 @@
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
- .size = 0x80000000UL,
+ .size = 0x1E800000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xA0000000UL,
+ .phys = 0xA0000000UL,
+ .size = 0x60000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -263,4 +317,4 @@
};
struct mm_region *mem_map = am64_mem_map;
-#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+#endif /* CONFIG_SOC_K3_AM642 */
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 34737a4..bda0152 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -568,39 +568,51 @@
}
#endif
-void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions,
+ enum k3_firewall_region_type fwl_type)
{
- struct ti_sci_msg_fwl_region region;
struct ti_sci_fwl_ops *fwl_ops;
struct ti_sci_handle *ti_sci;
- size_t i, j;
+ struct ti_sci_msg_fwl_region region;
+ size_t j;
ti_sci = get_ti_sci_handle();
fwl_ops = &ti_sci->ops.fwl_ops;
- for (i = 0; i < fwl_data_size; i++) {
- for (j = 0; j < fwl_data[i].regions; j++) {
- region.fwl_id = fwl_data[i].fwl_id;
- region.region = j;
- region.n_permission_regs = 3;
- fwl_ops->get_fwl_region(ti_sci, ®ion);
+ for (j = 0; j < fwl_data.regions; j++) {
+ region.fwl_id = fwl_data.fwl_id;
+ region.region = j;
+ region.n_permission_regs = 3;
- /* Don't disable the background regions */
- if (region.control != 0 &&
- ((region.control & K3_BACKGROUND_FIREWALL_BIT) ==
- 0)) {
- pr_debug("Attempting to disable firewall %5d (%25s)\n",
- region.fwl_id, fwl_data[i].name);
- region.control = 0;
+ fwl_ops->get_fwl_region(ti_sci, ®ion);
- if (fwl_ops->set_fwl_region(ti_sci, ®ion))
- pr_err("Could not disable firewall %5d (%25s)\n",
- region.fwl_id, fwl_data[i].name);
- }
+ /* Don't disable the background regions */
+ if (region.control != 0 &&
+ ((region.control & K3_FIREWALL_BACKGROUND_BIT) ==
+ fwl_type)) {
+ pr_debug("Attempting to disable firewall %5d (%25s)\n",
+ region.fwl_id, fwl_data.name);
+ region.control = 0;
+
+ if (fwl_ops->set_fwl_region(ti_sci, ®ion))
+ pr_err("Could not disable firewall %5d (%25s)\n",
+ region.fwl_id, fwl_data.name);
}
}
}
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+{
+ size_t i;
+
+ for (i = 0; i < fwl_data_size; i++) {
+ remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
+ K3_FIREWALL_REGION_FOREGROUND);
+ remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
+ K3_FIREWALL_REGION_BACKGROUND);
+ }
+}
+
void spl_enable_dcache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 899be64..6cffbd4 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -9,9 +9,7 @@
#include <asm/armv7_mpu.h>
#include <asm/hardware.h>
-#define J721E 0xbb64
-#define J7200 0xbb6d
-#define K3_BACKGROUND_FIREWALL_BIT BIT(8)
+#define K3_FIREWALL_BACKGROUND_BIT BIT(8)
struct fwl_data {
const char *name;
@@ -19,6 +17,11 @@
u16 regions;
};
+enum k3_firewall_region_type {
+ K3_FIREWALL_REGION_FOREGROUND,
+ K3_FIREWALL_REGION_BACKGROUND
+};
+
enum k3_device_type {
K3_DEVICE_TYPE_BAD,
K3_DEVICE_TYPE_GP,
diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c
index 0437e30..9b45786 100644
--- a/arch/arm/mach-k3/j7200/clk-data.c
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -379,6 +379,7 @@
CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
@@ -534,6 +535,8 @@
DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"),
+ DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -546,7 +549,7 @@
const struct ti_k3_clk_platdata j7200_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 108,
+ .clk_list_cnt = 109,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 127,
+ .soc_dev_clk_data_cnt = 129,
};
diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c
index d3194ae..c1a4dab 100644
--- a/arch/arm/mach-k3/j7200/dev-data.c
+++ b/arch/arm/mach-k3/j7200/dev-data.c
@@ -53,6 +53,7 @@
PSC_DEV(92, &soc_lpsc_list[5]),
PSC_DEV(91, &soc_lpsc_list[6]),
PSC_DEV(146, &soc_lpsc_list[7]),
+ PSC_DEV(278, &soc_lpsc_list[7]),
PSC_DEV(4, &soc_lpsc_list[8]),
PSC_DEV(4, &soc_lpsc_list[9]),
PSC_DEV(202, &soc_lpsc_list[10]),
@@ -77,5 +78,5 @@
.num_psc = 2,
.num_pd = 6,
.num_lpsc = 17,
- .num_devs = 22,
+ .num_devs = 23,
};
diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c
index 5ab7951..e451109 100644
--- a/arch/arm/mach-k3/j721e/clk-data.c
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@@ -553,6 +553,7 @@
CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 48000000),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
@@ -760,6 +761,8 @@
DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"),
+ DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -780,7 +783,7 @@
const struct ti_k3_clk_platdata j721e_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 156,
+ .clk_list_cnt = 157,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 171,
+ .soc_dev_clk_data_cnt = 173,
};
diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c
index 300d998..f0afa35 100644
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -46,6 +46,7 @@
PSC_DEV(30, &soc_lpsc_list[0]),
PSC_DEV(61, &soc_lpsc_list[0]),
PSC_DEV(146, &soc_lpsc_list[1]),
+ PSC_DEV(279, &soc_lpsc_list[1]),
PSC_DEV(90, &soc_lpsc_list[2]),
PSC_DEV(47, &soc_lpsc_list[3]),
PSC_DEV(288, &soc_lpsc_list[4]),
@@ -75,5 +76,5 @@
.num_psc = 2,
.num_pd = 5,
.num_lpsc = 16,
- .num_devs = 22,
+ .num_devs = 23,
};
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 0c5d41a..b616457 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -294,7 +294,7 @@
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
- return MMCSD_MODE_EMMCBOOT;
+ return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS);
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:
diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/j721s2/clk-data.c
index ad6bd99..0c5c321 100644
--- a/arch/arm/mach-k3/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/j721s2/clk-data.c
@@ -247,6 +247,7 @@
CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+ CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
@@ -383,6 +384,8 @@
DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
+ DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"),
DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -397,7 +400,7 @@
const struct ti_k3_clk_platdata j721s2_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 104,
+ .clk_list_cnt = 105,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 122,
+ .soc_dev_clk_data_cnt = 124,
};
diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c
index e36f1ed..35e8b17 100644
--- a/arch/arm/mach-k3/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/j721s2/dev-data.c
@@ -67,6 +67,7 @@
PSC_DEV(99, &soc_lpsc_list[12]),
PSC_DEV(98, &soc_lpsc_list[13]),
PSC_DEV(146, &soc_lpsc_list[14]),
+ PSC_DEV(354, &soc_lpsc_list[15]),
PSC_DEV(357, &soc_lpsc_list[15]),
PSC_DEV(4, &soc_lpsc_list[16]),
PSC_DEV(202, &soc_lpsc_list[17]),
@@ -81,5 +82,5 @@
.num_psc = 2,
.num_pd = 6,
.num_lpsc = 19,
- .num_devs = 24,
+ .num_devs = 25,
};
diff --git a/arch/arm/mach-keystone/include/mach/xhci-keystone.h b/arch/arm/mach-keystone/include/mach/xhci-keystone.h
deleted file mode 100644
index 989b0c3..0000000
--- a/arch/arm/mach-keystone/include/mach/xhci-keystone.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * USB 3.0 DRD Controller
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-#endif
-
-#define USB3_PHY_REF_SSP_EN BIT(29)
-#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16)
-
-/* KEYSTONE2 XHCI PHY register structure */
-struct keystone_xhci_phy {
- unsigned int phy_utmi; /* ctl0 */
- unsigned int phy_pipe; /* ctl1 */
- unsigned int phy_param_ctrl_1; /* ctl2 */
- unsigned int phy_param_ctrl_2; /* ctl3 */
- unsigned int phy_clock; /* ctl4 */
- unsigned int phy_pll; /* ctl5 */
-};
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 309b967..8465b54 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -77,16 +77,6 @@
imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
-config TI816X
- bool "TI816X SoC"
- select SPECIFY_CONSOLE_INDEX
- imply NAND_OMAP_ELM
- imply NAND_OMAP_GPMC
- help
- Support for AM335x SOC from Texas Instruments.
- The AM335x high performance SOC features a Cortex-A8
- ARM core and more.
-
config AM43XX
bool "AM43XX SoC"
select SPECIFY_CONSOLE_INDEX
@@ -203,7 +193,6 @@
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
-source "board/ti/ti816x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/compulab/cm_t43/Kconfig"
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 1299aec..8cb0c57 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -1,13 +1,3 @@
-if TI816X
-
-config TARGET_TI816X_EVM
- bool "Support ti816x_evm"
- help
- This option specifies support for the TI8168 EVM development platform
- with PG2.0 silicon and DDR3 DRAM.
-
-endif
-
if AM33XX
config AM33XX_CHILISOM
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index bf94d34..2aa8013 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -9,13 +9,11 @@
obj-y += clock.o
endif
-obj-$(CONFIG_TI816X) += clock_ti816x.o
obj-y += sys_info.o
obj-y += ddr.o
-ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y += emif4.o
endif
-obj-$(CONFIG_TI816X) += ti816x_emif4.o
obj-y += board.o
obj-y += mux.o
obj-y += prcm-regs.o
diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
deleted file mode 100644
index ec4cc75..0000000
--- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * clock_ti816x.c
- *
- * Clocks for TI816X based boards
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * Based on TI-PSP-04.00.02.14 :
- *
- * Copyright (C) 2009, Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-
-#include <asm/emif.h>
-
-#define CM_PLL_BASE (CTRL_BASE + 0x0400)
-
-/* Main PLL */
-#define MAIN_N 64
-#define MAIN_P 0x1
-#define MAIN_INTFREQ1 0x8
-#define MAIN_FRACFREQ1 0x800000
-#define MAIN_MDIV1 0x2
-#define MAIN_INTFREQ2 0xE
-#define MAIN_FRACFREQ2 0x0
-#define MAIN_MDIV2 0x1
-#define MAIN_INTFREQ3 0x8
-#define MAIN_FRACFREQ3 0xAAAAB0
-#define MAIN_MDIV3 0x3
-#define MAIN_INTFREQ4 0x9
-#define MAIN_FRACFREQ4 0x55554F
-#define MAIN_MDIV4 0x3
-#define MAIN_INTFREQ5 0x9
-#define MAIN_FRACFREQ5 0x374BC6
-#define MAIN_MDIV5 0xC
-#define MAIN_MDIV6 0x48
-#define MAIN_MDIV7 0x4
-
-/* DDR PLL */
-#define DDR_N 59
-#define DDR_P 0x1
-#define DDR_MDIV1 0x2
-#define DDR_INTFREQ2 0x8
-#define DDR_FRACFREQ2 0xD99999
-#define DDR_MDIV2 0x1E
-#define DDR_INTFREQ3 0x8
-#define DDR_FRACFREQ3 0x0
-#define DDR_MDIV3 0x4
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-
-#define CONTROL_STATUS (CTRL_BASE + 0x40)
-#define DDR_RCD (CTRL_BASE + 0x070C)
-#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
-#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
-
-#define INTCPS_SYSCONFIG 0x48200010
-#define CM_SYSCLK10_CLKSEL 0x48180324
-
-struct cm_pll {
- unsigned int mainpll_ctrl; /* offset 0x400 */
- unsigned int mainpll_pwd;
- unsigned int mainpll_freq1;
- unsigned int mainpll_div1;
- unsigned int mainpll_freq2;
- unsigned int mainpll_div2;
- unsigned int mainpll_freq3;
- unsigned int mainpll_div3;
- unsigned int mainpll_freq4;
- unsigned int mainpll_div4;
- unsigned int mainpll_freq5;
- unsigned int mainpll_div5;
- unsigned int resv0[1];
- unsigned int mainpll_div6;
- unsigned int resv1[1];
- unsigned int mainpll_div7;
- unsigned int ddrpll_ctrl; /* offset 0x440 */
- unsigned int ddrpll_pwd;
- unsigned int resv2[1];
- unsigned int ddrpll_div1;
- unsigned int ddrpll_freq2;
- unsigned int ddrpll_div2;
- unsigned int ddrpll_freq3;
- unsigned int ddrpll_div3;
- unsigned int ddrpll_freq4;
- unsigned int ddrpll_div4;
- unsigned int ddrpll_freq5;
- unsigned int ddrpll_div5;
- unsigned int videopll_ctrl; /* offset 0x470 */
- unsigned int videopll_pwd;
- unsigned int videopll_freq1;
- unsigned int videopll_div1;
- unsigned int videopll_freq2;
- unsigned int videopll_div2;
- unsigned int videopll_freq3;
- unsigned int videopll_div3;
- unsigned int resv3[4];
- unsigned int audiopll_ctrl; /* offset 0x4A0 */
- unsigned int audiopll_pwd;
- unsigned int resv4[2];
- unsigned int audiopll_freq2;
- unsigned int audiopll_div2;
- unsigned int audiopll_freq3;
- unsigned int audiopll_div3;
- unsigned int audiopll_freq4;
- unsigned int audiopll_div4;
- unsigned int audiopll_freq5;
- unsigned int audiopll_div5;
-};
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
-const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
-void enable_dmm_clocks(void)
-{
- writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
- /* Wait for dmm to be fully functional, including OCP */
- while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
- ;
-}
-
-void enable_emif_clocks(void)
-{
- writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
- writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
- writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
- writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
-
- /* Wait for clocks to be active */
- while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
- ;
- /* Wait for emif0 to be fully functional, including OCP */
- while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
- ;
- /* Wait for emif1 to be fully functional, including OCP */
- while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
- ;
-}
-
-/* assume delay is aprox at least 1us */
-static void ddr_delay(int d)
-{
- int i;
-
- /*
- * read a control register.
- * this is a bit more delay and cannot be optimized by the compiler
- * assuming one read takes 200 cycles and A8 is runing 1 GHz
- * somewhat conservative setting
- */
- for (i = 0; i < 50*d; i++)
- readl(CONTROL_STATUS);
-}
-
-static void main_pll_init_ti816x(void)
-{
- u32 main_pll_ctrl = 0;
-
- /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFFB;
- main_pll_ctrl |= BIT(2);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Enable PLL by setting BIT3 in its ctrl reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFF7;
- main_pll_ctrl |= BIT(3);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Write the values of N,P in the CTRL reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFF;
- main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Power up clock1-7 */
- writel(0x0, &cmpll->mainpll_pwd);
-
- /* Program the freq and divider values for clock1-7 */
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
- &cmpll->mainpll_freq1);
- writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
- &cmpll->mainpll_freq2);
- writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
- &cmpll->mainpll_freq3);
- writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
- &cmpll->mainpll_freq4);
- writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
- &cmpll->mainpll_freq5);
- writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
-
- writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
-
- writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
-
- /* Wait for PLL to lock */
- while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
- ;
-
- /* Put the PLL in normal mode, disable bypass */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFFB;
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-}
-
-static void ddr_pll_bypass_ti816x(void)
-{
- u32 ddr_pll_ctrl = 0;
-
- /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFFFFFFFB;
- ddr_pll_ctrl |= BIT(2);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-}
-
-static void ddr_pll_init_ti816x(void)
-{
- u32 ddr_pll_ctrl = 0;
- /* Enable PLL by setting BIT3 in its ctrl reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFFFFFFF7;
- ddr_pll_ctrl |= BIT(3);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
- /* Write the values of N,P in the CTRL reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFF;
- ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
- ddr_delay(10);
-
- /* Power up clock1-5 */
- writel(0x0, &cmpll->ddrpll_pwd);
-
- /* Program the freq and divider values for clock1-3 */
- writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
- ddr_delay(1);
- writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
- writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
- &cmpll->ddrpll_freq2);
- writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
- writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
- ddr_delay(1);
- writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
- ddr_delay(1);
- writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
- &cmpll->ddrpll_freq3);
- ddr_delay(1);
- writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
- &cmpll->ddrpll_freq3);
-
- ddr_delay(5);
-
- /* Wait for PLL to lock */
- while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
- ;
-
- /* Power up RCD */
- writel(BIT(0), DDR_RCD);
-}
-
-static void peripheral_enable(void)
-{
- /* Wake-up the l3_slow clock */
- writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
-
- /*
- * Note on Timers:
- * There are 8 timers(0-7) out of which timer 0 is a secure timer.
- * Timer 0 mux should not be changed
- *
- * To access the timer registers we need the to be
- * enabled which is what we do in the first step
- */
-
- /* Enable timer1 */
- writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
- /* Select timer1 clock to be CLKIN (27MHz) */
- writel(BIT(1), CM_TIMER1_CLKSEL);
-
- /* Wait for timer1 to be ON-ACTIVE */
- while (((readl(&cmalwon->l3slowclkstctrl)
- & (0x80000<<1))>>20) != 1)
- ;
- /* Wait for timer1 to be enabled */
- while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
- ;
- /* Active posted mode */
- writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
- while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
- ;
- /* Start timer1 */
- writel(BIT(0), (DM_TIMER1_BASE + 0x38));
-
- /* eFuse */
- writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
- while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
- ;
-
- /* Enable gpio0 */
- writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
- while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
- ;
- writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
-
- /* Enable gpio1 */
- writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
- while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
- ;
- writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
-
- /* Enable spi */
- writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
- while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable i2c0 */
- writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
- while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable ethernet0 */
- writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
-
- /* Enable hsmmc */
- writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
- while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
- ;
-}
-
-void setup_clocks_for_console(void)
-{
- /* Fix ROM code bug - from TI-PSP-04.00.02.14 */
- writel(0x0, CM_SYSCLK10_CLKSEL);
-
- ddr_pll_bypass_ti816x();
-
- /* Enable uart0-2 */
- writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
- while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
- while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
- while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
- ;
- while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
- ;
-}
-
-void setup_early_clocks(void)
-{
- setup_clocks_for_console();
-}
-
-void prcm_init(void)
-{
- /* Enable the control */
- writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
- main_pll_init_ti816x();
- ddr_pll_init_ti816x();
-
- /*
- * With clk freqs setup to desired values,
- * enable the required peripherals
- */
- peripheral_enable();
-}
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index f8434ec..5f970d9 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -182,14 +182,6 @@
*/
void config_sdram(const struct emif_regs *regs, int nr)
{
-#ifdef CONFIG_TI816X
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
- writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
- writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */
- writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-#else
if (regs->zq_config) {
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
@@ -211,7 +203,6 @@
/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
if (regs->ocp_config)
writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
-#endif
}
/**
diff --git a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c b/arch/arm/mach-omap2/am33xx/ti816x_emif4.c
deleted file mode 100644
index 707ea80..0000000
--- a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c
+++ /dev/null
@@ -1,165 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * ti816x_emif4.c
- *
- * TI816x emif4 configuration file
- *
- * Copyright (C) 2017, Konsulko Group
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <linux/delay.h>
-
-/*********************************************************************
- * Init DDR3 on TI816X EVM
- *********************************************************************/
-static void ddr_init_settings(const struct cmd_control *ctrl, int emif)
-{
- /*
- * setup use_rank_delays to 1. This is only necessary when
- * multiple ranks are in use. Though the EVM does not have
- * multiple ranks, this is a good value to set.
- */
- writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS
- writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS
- writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS
- writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS
-
- config_cmd_ctrl(ctrl, emif);
-
- /* for ddr3 this needs to be set to 1 */
- writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
- writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
- writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
- writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
- writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
- writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
- writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
- writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);
-
- /*
- * This represents the initial value for the leveling process. The
- * value is a ratio - so 0x100 represents one cycle. The real delay
- * is determined through the leveling process.
- *
- * During the leveling process, 0x20 is subtracted from the value, so
- * we have added that to the value we want to set. We also set the
- * values such that byte3 completes leveling after byte2 and byte1
- * after byte0.
- */
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */
-
-
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
- writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */
- writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);
-
- writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */
- writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */
- writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */
- writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */
- writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */
- writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */
- writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */
-}
-
-static void ddr3_sw_levelling(const struct ddr_data *data, int emif)
-{
- /* Set the correct value to DDR_VTP_CTRL_0 */
- writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
-
- writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108));
- writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC));
- writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250));
- writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4));
-
- writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC));
- writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180));
- writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224));
- writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8));
-
- writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120));
- writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4));
- writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268));
- writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C));
-
- writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8));
- writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C));
- writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210));
- writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4));
-}
-
-static struct dmm_lisa_map_regs *hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)DMM_BASE;
-
-#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
-void config_dmm(const struct dmm_lisa_map_regs *regs)
-{
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
- writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
- /* Enable Tiled Access */
- writel(0x80000000, DMM_PAT_BASE_ADDR);
-}
-
-void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
- const struct emif_regs *regs,
- const struct dmm_lisa_map_regs *lisa_regs, int nrs)
-{
- int i;
-
- enable_emif_clocks();
-
- for (i = 0; i < nrs; i++)
- ddr_init_settings(ctrl, i);
-
- enable_dmm_clocks();
-
- /* Program the DMM to for non-interleaved configuration */
- config_dmm(lisa_regs);
-
- /* Program EMIF CFG Registers */
- for (i = 0; i < nrs; i++) {
- set_sdram_timings(regs, i);
- config_sdram(regs, i);
- }
-
- udelay(1000);
- for (i = 0; i < nrs; i++)
- ddr3_sw_levelling(data, i);
-
- udelay(50000); /* Some delay needed */
-}
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index 9a342a1..a2dd5f6 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -75,23 +75,6 @@
if (boot_device == BOOT_DEVICE_QSPI_4)
boot_device = BOOT_DEVICE_SPI;
#endif
-#ifdef CONFIG_TI816X
- /*
- * On PG2.0 and later TI816x the values we get when booting are not the
- * same as on PG1.0, which is what the defines are based on. Update
- * them as needed.
- */
- if (get_cpu_rev() != 1) {
- if (boot_device == 0x05) {
- omap_boot_params->boot_device = BOOT_DEVICE_NAND;
- boot_device = BOOT_DEVICE_NAND;
- }
- if (boot_device == 0x08) {
- omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
- boot_device = BOOT_DEVICE_MMC1;
- }
- }
-#endif
/*
* When booting from peripheral booting, the boot device is not usable
* as-is (unless there is support for it), so the boot device is instead
@@ -183,8 +166,7 @@
gd->arch.omap_boot_mode = boot_mode;
-#if !defined(CONFIG_TI816X) && \
- !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
/* CH flags */
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-rmobile/Kconfig.rcar3
index 5f33821..ad35d10 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar3
+++ b/arch/arm/mach-rmobile/Kconfig.rcar3
@@ -99,6 +99,11 @@
help
Support for Renesas R-Car Gen3 Condor platform
+config TARGET_V3HSK
+ bool "V3HSK board"
+ help
+ Support for Renesas R-Car Gen3 V3HSK platform
+
config TARGET_DRAAK
bool "Draak board"
imply R8A77995
@@ -111,6 +116,11 @@
help
Support for Renesas R-Car Gen3 Eagle platform
+config TARGET_V3MSK
+ bool "V3MSK board"
+ help
+ Support for Renesas R-Car Gen3 V3MSK platform
+
config TARGET_EBISU
bool "Ebisu board"
imply R8A77990
@@ -166,6 +176,8 @@
source "board/renesas/ebisu/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
+source "board/renesas/v3hsk/Kconfig"
+source "board/renesas/v3msk/Kconfig"
source "board/beacon/beacon-rzg2m/Kconfig"
source "board/hoperun/hihope-rzg2/Kconfig"
source "board/silinux/ek874/Kconfig"
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 45d9eae..8d7b39b 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -41,7 +41,7 @@
uuid_str_to_bin(info->type_guid, image_type_guid.b,
UUID_STR_FORMAT_GUID);
- for (i = 0; i < num_image_type_guids; i++) {
+ for (i = 0; i < update_info.num_images; i++) {
if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
ret = true;
break;
@@ -59,7 +59,7 @@
uuid_str_to_bin(info->type_guid, image_type_guid.b,
UUID_STR_FORMAT_GUID);
- for (i = 0; i < num_image_type_guids; i++) {
+ for (i = 0; i < update_info.num_images; i++) {
if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
fw_images[i].image_index = index;
break;
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-init.h b/arch/arm/mach-uniphier/dram/ddrphy-init.h
index 09981f6..4431f5c 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-init.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-init.h
@@ -4,7 +4,7 @@
*/
#ifndef ARCH_DDRPHY_INIT_H
-#define ARCH_DDRPHY_INTT_H
+#define ARCH_DDRPHY_INIT_H
#include <linux/compiler.h>
#include <linux/types.h>
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
index 328aa0c..7fb482a 100644
--- a/arch/m68k/include/asm/unaligned.h
+++ b/arch/m68k/include/asm/unaligned.h
@@ -1,15 +1,2 @@
-#ifndef _ASM_M68K_UNALIGNED_H
-#define _ASM_M68K_UNALIGNED_H
-
-#ifdef CONFIG_COLDFIRE
-#include <linux/unaligned/be_byteshift.h>
-#else
-#include <linux/unaligned/access_ok.h>
-#endif
-
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-
-#endif /* _ASM_M68K_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
index debb9cf..7fb482a 100644
--- a/arch/mips/include/asm/unaligned.h
+++ b/arch/mips/include/asm/unaligned.h
@@ -1,23 +1,2 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_MIPS_UNALIGNED_H
-#define _ASM_MIPS_UNALIGNED_H
-
-#include <linux/compiler.h>
-#if defined(__MIPSEB__)
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-#elif defined(__MIPSEL__)
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-#else
-#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#endif /* _ASM_MIPS_UNALIGNED_H */
+#include <asm-generic/unaligned.h>
diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h
deleted file mode 100644
index 5f806c4..0000000
--- a/arch/powerpc/include/asm/mc146818rtc.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef __ASM_PPC_MC146818RTC_H
-#define __ASM_PPC_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x) (0x70 + (x))
-#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#endif /* __ASM_PPC_MC146818RTC_H */
diff --git a/arch/powerpc/include/asm/pci_io.h b/arch/powerpc/include/asm/pci_io.h
deleted file mode 100644
index 9b738c3..0000000
--- a/arch/powerpc/include/asm/pci_io.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* originally from linux source (asm-ppc/io.h).
- * Sanity added by Rob Taylor, Flying Pig Systems, 2000
- */
-#ifndef _PCI_IO_H_
-#define _PCI_IO_H_
-
-#include "io.h"
-
-
-#define pci_read_le16(addr, dest) \
- __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \
- "r" (addr), "m" (*addr));
-
-#define pci_write_le16(addr, val) \
- __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \
- "r" (val), "r" (addr));
-
-
-#define pci_read_le32(addr, dest) \
- __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \
- "r" (addr), "m" (*addr));
-
-#define pci_write_le32(addr, val) \
-__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \
- "r" (val), "r" (addr));
-
-#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr))
-#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
-
-#if !defined(__BIG_ENDIAN)
-#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr))
-#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr))
-#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
-#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
-#else
-#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b))
-#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b))
-#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b))
-#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b))
-#endif
-
-
-#endif /* _PCI_IO_H_ */
diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h
index 5f1b1e3..7fb482a 100644
--- a/arch/powerpc/include/asm/unaligned.h
+++ b/arch/powerpc/include/asm/unaligned.h
@@ -1,16 +1,2 @@
-#ifndef _ASM_POWERPC_UNALIGNED_H
-#define _ASM_POWERPC_UNALIGNED_H
-
-#ifdef __KERNEL__
-
-/*
- * The PowerPC can do unaligned accesses itself in big endian mode.
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/riscv/include/asm/arch-fu740/eeprom.h b/arch/riscv/include/asm/arch-fu740/eeprom.h
deleted file mode 100644
index 0e1220e..0000000
--- a/arch/riscv/include/asm/arch-fu740/eeprom.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 SiFive, Inc.
- *
- * Zong Li <zong.li@sifve.com>
- */
-
-#ifndef _ASM_RISCV_EEPROM_H
-#define _ASM_RISCV_EEPROM_H
-
-#define PCB_REVISION_REV3 0x3
-
-u8 get_pcb_revision_from_eeprom(void);
-
-#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/arch/sandbox/include/asm/axi.h b/arch/sandbox/include/asm/axi.h
index d483f7b..5b94bed 100644
--- a/arch/sandbox/include/asm/axi.h
+++ b/arch/sandbox/include/asm/axi.h
@@ -14,8 +14,8 @@
* @bus: The AXI bus from which to retrieve a emulation device
* @address: The address of a transfer that should be handled by a emulation
* device
- * @length: The data width of a transfer that should be handled by a emulation
- * device
+ * @size: A constant indicating the data width of the transfer that
+ * should be handled by an emulation device
* @emulp: Pointer to a buffer receiving the emulation device that handles
* the transfer specified by the address and length parameters
*
@@ -45,8 +45,8 @@
* Return: 0 of OK, -ENODEV if no device capable of handling the specified
* transfer exists or the device could not be retrieved
*/
-int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length,
- struct udevice **emulp);
+int axi_sandbox_get_emul(struct udevice *bus, ulong address,
+ const enum axi_size_t size, struct udevice **emulp);
/**
* axi_get_store() - Get address of internal storage of a emulated AXI device
* @dev: Emulated AXI device to get the pointer of the internal storage
diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h
deleted file mode 100644
index 5732b2b..0000000
--- a/arch/sh/include/asm/mmc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Renesas SuperH MMCIF driver.
- *
- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- */
-#ifndef _SH_MMC_H_
-#define _SH_MMC_H_
-
-int mmcif_mmc_init(void);
-
-#endif /* _SH_MMC_H_ */
diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h
index 5acf081..7fb482a 100644
--- a/arch/sh/include/asm/unaligned.h
+++ b/arch/sh/include/asm/unaligned.h
@@ -1,20 +1,2 @@
-#ifndef _ASM_SH_UNALIGNED_H
-#define _ASM_SH_UNALIGNED_H
-
-/* Copy from linux-kernel. */
-
-/* Other than SH4A, SH can't handle unaligned accesses. */
-#include <linux/compiler.h>
-#if defined(__BIG_ENDIAN__)
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-#elif defined(__LITTLE_ENDIAN__)
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-#endif
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#endif /* _ASM_SH_UNALIGNED_H */
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/unaligned.h>
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index e54082d..274978c0 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -97,7 +97,7 @@
}
}
-#if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
+#if CONFIG_IS_ENABLED(X86_32BIT_INIT)
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index 4661746..b79a238 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -54,10 +54,10 @@
struct efi_capsule_update_info update_info = {
.dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1",
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 770f3d7..4dcf3f3 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -30,7 +30,6 @@
#include <bmp_logo.h>
#include <dm/root.h>
#include <env.h>
-#include <env_internal.h>
#include <i2c_eeprom.h>
#include <i2c.h>
#include <micrel.h>
@@ -529,22 +528,3 @@
return 0;
}
#endif
-
-enum env_location env_get_location(enum env_operation op, int prio)
-{
- if (op == ENVOP_SAVE || op == ENVOP_ERASE)
- return ENVL_SPI_FLASH;
-
- switch (prio) {
- case 0:
- return ENVL_NOWHERE;
-
- case 1:
- return ENVL_SPI_FLASH;
-
- default:
- return ENVL_UNKNOWN;
- }
-
- return ENVL_UNKNOWN;
-}
diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
index 62388b3..7c49b20 100644
--- a/board/bosch/acc/acc.c
+++ b/board/bosch/acc/acc.c
@@ -12,7 +12,6 @@
#include <dm/platform_data/serial_mxc.h>
#include <dm/device-internal.h>
#include <env.h>
-#include <env_internal.h>
#include <hang.h>
#include <init.h>
#include <linux/delay.h>
@@ -236,22 +235,6 @@
gpio_set_value(GPIO_TOUCH_RESET, 1);
}
-enum env_location env_get_location(enum env_operation op, int prio)
-{
- if (op == ENVOP_SAVE || op == ENVOP_ERASE)
- return ENVL_MMC;
-
- switch (prio) {
- case 0:
- return ENVL_NOWHERE;
-
- case 1:
- return ENVL_MMC;
- }
-
- return ENVL_UNKNOWN;
-}
-
int board_late_init(void)
{
struct board_info *binfo = detect_board();
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
index b373e45..af070ec 100644
--- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
+++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -50,10 +50,10 @@
struct efi_capsule_update_info update_info = {
.dfu_string = "mmc 2=flash-bin raw 0x42 0x1D00 mmcpart 1",
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
int board_phys_sdram_size(phys_size_t *size)
diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index 34ed3e8..dfea0d9 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -47,10 +47,10 @@
};
struct efi_capsule_update_info update_info = {
+ .num_images = ARRAY_SIZE(fw_images)
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
static struct mm_region qemu_arm64_mem_map[] = {
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 6dca229..a928882 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -91,7 +91,7 @@
return p;
}
-#else
+#elif defined(CONFIG_DM_PMIC)
int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h
index 49a684f..8d343ba 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -4,7 +4,7 @@
*/
#ifndef __VSC_CROSSBAR_H_
-#define __VSC_CROSSBAR_H 1_
+#define __VSC_CROSSBAR_H_
#include <common.h>
#include <i2c.h>
diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c
index fcda86b..4548e7c 100644
--- a/board/kontron/pitx_imx8m/pitx_imx8m.c
+++ b/board/kontron/pitx_imx8m/pitx_imx8m.c
@@ -43,10 +43,10 @@
struct efi_capsule_update_info update_info = {
.dfu_string = "mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1",
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
int board_early_init_f(void)
diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c
index 2501956..ddb509e 100644
--- a/board/kontron/sl-mx8mm/sl-mx8mm.c
+++ b/board/kontron/sl-mx8mm/sl-mx8mm.c
@@ -29,10 +29,10 @@
struct efi_capsule_update_info update_info = {
.dfu_string = "sf 0:0=flash-bin raw 0x400 0x1f0000",
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
int board_phys_sdram_size(phys_size_t *size)
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index 89948e0..4ab221c 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -40,10 +40,10 @@
struct efi_capsule_update_info update_info = {
.dfu_string = "sf 0:0=u-boot-bin raw 0x210000 0x1d0000;"
"u-boot-env raw 0x3e0000 0x20000",
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
int board_early_init_f(void)
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 14324c7..ca3b81c 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -264,6 +264,7 @@
gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
}
+#if CONFIG_IS_ENABLED(OF_LIBFDT)
int ft_board_setup(void *blob, struct bd_info *bd)
{
if (lvds_compat_string)
@@ -272,6 +273,7 @@
return 0;
}
+#endif
struct display_info_t const displays[] = {
{
diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile
index cf6d566..19e6038 100644
--- a/board/renesas/condor/Makefile
+++ b/board/renesas/condor/Makefile
@@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
-obj-y := condor.o ../rcar-common/common.o
+obj-y := ../rcar-common/common.o
endif
diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
deleted file mode 100644
index 2dd2c15..0000000
--- a/board/renesas/condor/condor.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/condor/condor.c
- * This file is Condor board support.
- *
- * Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- return 0;
-}
-
-#define RST_BASE 0xE6160000
-#define RST_CA57RESCNT (RST_BASE + 0x40)
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CA57_CODE 0xA5A5000F
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- unsigned long midr, cputype;
-
- asm volatile("mrs %0, midr_el1" : "=r" (midr));
- cputype = (midr >> 4) & 0xfff;
-
- if (cputype == 0xd03)
- writel(RST_CA53_CODE, RST_CA53RESCNT);
- else if (cputype == 0xd07)
- writel(RST_CA57_CODE, RST_CA57RESCNT);
- else
- hang();
-}
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 71efeaf..1ed72d3 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -67,12 +67,3 @@
return 0;
}
-
-#define RST_BASE 0xE6160000
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- writel(RST_CA53_CODE, RST_CA53RESCNT);
-}
diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig
index 1e0710e..4d12843 100644
--- a/board/renesas/eagle/Kconfig
+++ b/board/renesas/eagle/Kconfig
@@ -10,6 +10,6 @@
default "renesas"
config SYS_CONFIG_NAME
- default "eagle"
+ default "rcar-gen3-common"
endif
diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile
index 062c46b..9fb6a7c 100644
--- a/board/renesas/eagle/Makefile
+++ b/board/renesas/eagle/Makefile
@@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
-obj-y := eagle.o ../rcar-common/common.o
+obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
endif
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
deleted file mode 100644
index 9af935c..0000000
--- a/board/renesas/eagle/eagle.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/eagle/eagle.c
- * This file is Eagle board support.
- *
- * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <dm.h>
-#include <asm/global_data.h>
-#include <dm/platform_data/serial_sh.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-#include <asm/arch/sh_sdhi.h>
-#include <i2c.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CPGWPR 0xE6150900
-#define CPGWPCR 0xE6150904
-
-/* PLL */
-#define PLL0CR 0xE61500D8
-#define PLL0_STC_MASK 0x7F000000
-#define PLL0_STC_OFFSET 24
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
-void s_init(void)
-{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
- u32 stc;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- /* CPU frequency setting. Set to 0.8GHz */
- stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
- clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
-}
-
-int board_early_init_f(void)
-{
- /* Unlock CPG access */
- writel(0xA5A5FFFF, CPGWPR);
- writel(0x5A5A0000, CPGWPCR);
-
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-#define RST_BASE 0xE6160000
-#define RST_CA57RESCNT (RST_BASE + 0x40)
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CA57_CODE 0xA5A5000F
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- unsigned long midr, cputype;
-
- asm volatile("mrs %0, midr_el1" : "=r" (midr));
- cputype = (midr >> 4) & 0xfff;
-
- if (cputype == 0xd03)
- writel(RST_CA53_CODE, RST_CA53RESCNT);
- else if (cputype == 0xd07)
- writel(RST_CA57_CODE, RST_CA57RESCNT);
- else
- hang();
-}
diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile
index 1fd9a03..956ce8a 100644
--- a/board/renesas/ebisu/Makefile
+++ b/board/renesas/ebisu/Makefile
@@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
-obj-y := ebisu.o ../rcar-common/common.o
+obj-y := ../rcar-common/common.o
endif
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
deleted file mode 100644
index 9a70192..0000000
--- a/board/renesas/ebisu/ebisu.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/ebisu/ebisu.c
- * This file is Ebisu board support.
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <dm.h>
-#include <asm/global_data.h>
-#include <dm/platform_data/serial_sh.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-#include <asm/arch/sh_sdhi.h>
-#include <i2c.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- return 0;
-}
-
-#define RST_BASE 0xE6160000
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- writel(RST_CA53_CODE, RST_CA53RESCNT);
-}
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index ab7464d..0aa0f1a 100644
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -84,8 +84,6 @@
}
#define RST_BASE 0xE6160000 /* Domain0 */
-#define RST_SRESCR0 (RST_BASE + 0x18)
-#define RST_SPRES 0x5AA58000
#define RST_WDTRSTCR (RST_BASE + 0x10)
#define RST_RWDT 0xA55A8002
@@ -103,8 +101,3 @@
return 0;
}
-
-void reset_cpu(void)
-{
- writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index f38453a..ed3f093 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -10,8 +10,10 @@
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
+#include <hang.h>
#include <init.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <asm/arch/rmobile.h>
#include <linux/libfdt.h>
@@ -25,12 +27,17 @@
#define FDT_RPC_PATH "/soc/spi@ee200000"
-int fdtdec_board_setup(const void *fdt_blob)
+static void apply_atf_overlay(void *fdt_blob)
{
void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
- fdt_overlay_apply_node((void *)fdt_blob, 0, atf_fdt_blob, 0);
+ fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0);
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ apply_atf_overlay((void *)fdt_blob);
return 0;
}
@@ -47,6 +54,46 @@
return 0;
}
+int __weak board_init(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_RCAR_GEN3)
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void __weak reset_cpu(void)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}
+#elif defined(CONFIG_RCAR_GEN4)
+#define RST_BASE 0xE6160000 /* Domain0 */
+#define RST_SRESCR0 (RST_BASE + 0x18)
+#define RST_SPRES 0x5AA58000
+
+void __weak reset_cpu(void)
+{
+ writel(RST_SPRES, RST_SRESCR0);
+}
+#else
+#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set
+#endif
+
#if defined(CONFIG_OF_BOARD_SETUP)
static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
{
@@ -159,6 +206,7 @@
int ft_board_setup(void *blob, struct bd_info *bd)
{
+ apply_atf_overlay(blob);
scrub_duplicate_memory(blob);
update_rpc_status(blob);
diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/rcar-common/v3-common.c
new file mode 100644
index 0000000..7c6202e
--- /dev/null
+++ b/board/renesas/rcar-common/v3-common.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <asm/io.h>
+
+#define CPGWPR 0xE6150900
+#define CPGWPCR 0xE6150904
+
+/* PLL */
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_OFFSET 24
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 0.8GHz */
+ stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+int board_early_init_f(void)
+{
+ /* Unlock CPG access */
+ writel(0xA5A5FFFF, CPGWPR);
+ writel(0x5A5A0000, CPGWPCR);
+
+ return 0;
+}
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index c27eb3f..939b48e 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -67,21 +67,12 @@
return 0;
}
-#define RST_BASE 0xE6160000
-#define RST_CA57RESCNT (RST_BASE + 0x40)
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CODE 0xA5A5000F
-
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
void reset_cpu(void)
{
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
-#else
- /* only CA57 ? */
- writel(RST_CODE, RST_CA57RESCNT);
-#endif
}
+#endif
#ifdef CONFIG_MULTI_DTB_FIT
int board_fit_config_name_match(const char *name)
diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
index caf88dc..fd83a72 100644
--- a/board/renesas/spider/spider.c
+++ b/board/renesas/spider/spider.c
@@ -65,8 +65,3 @@
return 0;
}
-
-void reset_cpu(void)
-{
- writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig
new file mode 100644
index 0000000..531ceb7
--- /dev/null
+++ b/board/renesas/v3hsk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3HSK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "v3hsk"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "v3hsk"
+
+endif
diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
new file mode 100644
index 0000000..a9d597e
--- /dev/null
+++ b/board/renesas/v3hsk/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/v3hsk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-$(CONFIG_SYSRESET) += cpld.o
+endif
diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c
new file mode 100644
index 0000000..6016f6d
--- /dev/null
+++ b/board/renesas/v3hsk/cpld.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * V3HSK board CPLD access support
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <linux/err.h>
+#include <sysreset.h>
+#include <command.h>
+
+#define CPLD_ADDR_PRODUCT_0 0x0000 /* R */
+#define CPLD_ADDR_PRODUCT_1 0x0001 /* R */
+#define CPLD_ADDR_PRODUCT_2 0x0002 /* R */
+#define CPLD_ADDR_PRODUCT_3 0x0003 /* R */
+#define CPLD_ADDR_CPLD_VERSION_D 0x0004 /* R */
+#define CPLD_ADDR_CPLD_VERSION_M 0x0005 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_0 0x0006 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_1 0x0007 /* R */
+#define CPLD_ADDR_MODE_SET_0 0x0008 /* R */
+#define CPLD_ADDR_MODE_SET_1 0x0009 /* R */
+#define CPLD_ADDR_MODE_SET_2 0x000A /* R */
+#define CPLD_ADDR_MODE_SET_3 0x000B /* R */
+#define CPLD_ADDR_MODE_SET_4 0x000C /* R */
+#define CPLD_ADDR_MODE_LAST_0 0x0018 /* R */
+#define CPLD_ADDR_MODE_LAST_1 0x0019 /* R */
+#define CPLD_ADDR_MODE_LAST_2 0x001A /* R */
+#define CPLD_ADDR_MODE_LAST_3 0x001B /* R */
+#define CPLD_ADDR_MODE_LAST_4 0x001C /* R */
+#define CPLD_ADDR_DIPSW4 0x0020 /* R */
+#define CPLD_ADDR_DIPSW5 0x0021 /* R */
+#define CPLD_ADDR_RESET 0x0024 /* R/W */
+#define CPLD_ADDR_POWER_CFG 0x0025 /* R/W */
+#define CPLD_ADDR_PERI_CFG_0 0x0030 /* R/W */
+#define CPLD_ADDR_PERI_CFG_1 0x0031 /* R/W */
+#define CPLD_ADDR_PERI_CFG_2 0x0032 /* R/W */
+#define CPLD_ADDR_PERI_CFG_3 0x0033 /* R/W */
+#define CPLD_ADDR_LEDS 0x0034 /* R/W */
+#define CPLD_ADDR_LEDS_CFG 0x0035 /* R/W */
+#define CPLD_ADDR_UART_CFG 0x0036 /* R/W */
+#define CPLD_ADDR_UART_STATUS 0x0037 /* R */
+
+#define CPLD_ADDR_PCB_VERSION_0 0x1000 /* R */
+#define CPLD_ADDR_PCB_VERSION_1 0x1001 /* R */
+#define CPLD_ADDR_SOC_VERSION_0 0x1002 /* R */
+#define CPLD_ADDR_SOC_VERSION_1 0x1003 /* R */
+#define CPLD_ADDR_PCB_SN_0 0x1004 /* R */
+#define CPLD_ADDR_PCB_SN_1 0x1005 /* R */
+
+static u16 cpld_read(struct udevice *dev, u16 addr)
+{
+ u8 data[2];
+
+ /* Random flash reads require 2 reads: first read is unreliable */
+ if (addr >= CPLD_ADDR_PCB_VERSION_0)
+ dm_i2c_read(dev, addr, data, 2);
+
+ /* Only the second byte read is valid */
+ dm_i2c_read(dev, addr, data, 2);
+ return data[1];
+}
+
+static void cpld_write(struct udevice *dev, u16 addr, u8 data)
+{
+ dm_i2c_write(dev, addr, &data, 1);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *dev;
+ u16 addr, val;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+ DM_DRIVER_GET(sysreset_renesas_v3hsk),
+ &dev);
+ if (ret)
+ return ret;
+
+ if (argc == 2 && strcmp(argv[1], "info") == 0) {
+ printf("Product: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) |
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) |
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_PRODUCT_0));
+ printf("CPLD version: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) |
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) |
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) |
+ cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
+ printf("Mode setting (MD0..26): 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) |
+ (cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) |
+ (cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_MODE_LAST_0));
+ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
+ cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff,
+ (cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf);
+ printf("Power config: 0x%08x\n",
+ cpld_read(dev, CPLD_ADDR_POWER_CFG));
+ printf("Periferals config: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) |
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) |
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_PERI_CFG_0));
+ printf("PCB version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION_1),
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION_0));
+ printf("SOC version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION_1),
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION_0));
+ printf("PCB S/N: %d\n",
+ (cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_PCB_SN_0));
+ return 0;
+ }
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) {
+ printf("cpld invalid addr\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 3 && strcmp(argv[1], "read") == 0) {
+ printf("0x%x\n", cpld_read(dev, addr));
+ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+ val = simple_strtoul(argv[3], NULL, 16);
+ cpld_write(dev, addr, val);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(cpld, 4, 1, do_cpld,
+ "CPLD access",
+ "info\n"
+ "cpld read addr\n"
+ "cpld write addr val\n"
+);
+
+static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+ return -EINPROGRESS;
+}
+
+static int renesas_v3hsk_sysreset_probe(struct udevice *dev)
+{
+ if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+ return -EPROTONOSUPPORT;
+
+ return 0;
+}
+
+static struct sysreset_ops renesas_v3hsk_sysreset = {
+ .request = renesas_v3hsk_sysreset_request,
+};
+
+static const struct udevice_id renesas_v3hsk_sysreset_ids[] = {
+ { .compatible = "renesas,v3hsk-cpld" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_v3hsk) = {
+ .name = "renesas_v3hsk_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &renesas_v3hsk_sysreset,
+ .probe = renesas_v3hsk_sysreset_probe,
+ .of_match = renesas_v3hsk_sysreset_ids,
+};
diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig
new file mode 100644
index 0000000..fe037fd
--- /dev/null
+++ b/board/renesas/v3msk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3MSK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "v3msk"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rcar-gen3-common"
+
+endif
diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS
new file mode 100644
index 0000000..12822a4
--- /dev/null
+++ b/board/renesas/v3msk/MAINTAINERS
@@ -0,0 +1,6 @@
+V3MSK BOARD
+M: Cogent Embedded, Inc. <source@cogentembedded.com>
+S: Maintained
+F: board/renesas/v3msk/
+F: include/configs/v3msk.h
+F: configs/r8a77970_v3msk_defconfig
diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile
new file mode 100644
index 0000000..ec493e5
--- /dev/null
+++ b/board/renesas/v3msk/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/v3msk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-$(CONFIG_SYSRESET) += cpld.o
+endif
diff --git a/board/renesas/v3msk/cpld.c b/board/renesas/v3msk/cpld.c
new file mode 100644
index 0000000..aed616a
--- /dev/null
+++ b/board/renesas/v3msk/cpld.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * V3MSK board CPLD access support
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <sysreset.h>
+#include <linux/delay.h>
+#include <command.h>
+
+#define CPLD_ADDR_PRODUCT_L 0x000 /* R */
+#define CPLD_ADDR_PRODUCT_H 0x001 /* R */
+#define CPLD_ADDR_CPLD_VERSION_D 0x002 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y 0x003 /* R */
+#define CPLD_ADDR_MODE_SET_L 0x004 /* R/W */
+#define CPLD_ADDR_MODE_SET_H 0x005 /* R/W */
+#define CPLD_ADDR_MODE_APPLIED_L 0x006 /* R */
+#define CPLD_ADDR_MODE_APPLIED_H 0x007 /* R */
+#define CPLD_ADDR_DIPSW 0x008 /* R */
+#define CPLD_ADDR_RESET 0x00A /* R/W */
+#define CPLD_ADDR_POWER_CFG 0x00B /* R/W */
+#define CPLD_ADDR_PERI_CFG1 0x00C /* R/W */
+#define CPLD_ADDR_PERI_CFG2 0x00D /* R/W */
+#define CPLD_ADDR_LEDS 0x00E /* R/W */
+#define CPLD_ADDR_PCB_VERSION 0x300 /* R */
+#define CPLD_ADDR_SOC_VERSION 0x301 /* R */
+#define CPLD_ADDR_PCB_SN_L 0x302 /* R */
+#define CPLD_ADDR_PCB_SN_H 0x303 /* R */
+
+#define MDIO_DELAY 10 /* microseconds */
+
+#define CPLD_MAX_GPIOS 2
+
+struct renesas_v3msk_sysreset_priv {
+ struct gpio_desc miso;
+ struct gpio_desc mosi;
+ struct gpio_desc mdc;
+ struct gpio_desc enablez;
+ /*
+ * V3MSK Videobox Mini board has CANFD PHY connected
+ * we must shutdown this chip to use bb pins
+ */
+ struct gpio_desc gpios[CPLD_MAX_GPIOS];
+};
+
+static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+ dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+ dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN);
+}
+
+static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val)
+{
+ dm_gpio_set_value(&priv->mosi, val);
+}
+
+static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+ return dm_gpio_get_value(&priv->miso);
+}
+
+static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val)
+{
+ dm_gpio_set_value(&priv->mdc, val);
+}
+
+static void mdio_bb_delay(void)
+{
+ udelay(MDIO_DELAY);
+}
+
+/* Send the preamble, address, and register (common to read and write) */
+static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv,
+ u8 op, u8 addr, u8 reg)
+{
+ int i;
+
+ /* 32-bit preamble */
+ mdio_bb_active_mdio(priv);
+ mdio_bb_set_mdio(priv, 1);
+ for (i = 0; i < 32; i++) {
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ }
+ /* send the ST (2-bits of '01') */
+ mdio_bb_set_mdio(priv, 0);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdio(priv, 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* send the OP (2-bits of Opcode: '10'-read, '01'-write) */
+ mdio_bb_set_mdio(priv, op >> 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdio(priv, op & 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* send the PA5 (5-bits of PHY address) */
+ for (i = 0; i < 5; i++) {
+ mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ addr <<= 1;
+ }
+ /* send the RA5 (5-bits of register address) */
+ for (i = 0; i < 5; i++) {
+ mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ reg <<= 1;
+ }
+}
+
+static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv,
+ u8 addr, u8 reg)
+{
+ int i;
+ u16 data = 0;
+
+ mdio_bb_pre(priv, 2, addr, reg);
+ /* tri-state MDIO */
+ mdio_bb_tristate_mdio(priv);
+ /* read TA (2-bits of turn-around, last bit must be '0') */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* check the turnaround bit: the PHY should drive line to zero */
+ if (mdio_bb_get_mdio(priv) != 0) {
+ printf("PHY didn't drive TA low\n");
+ for (i = 0; i < 32; i++) {
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ }
+ /* There is no PHY, set value to 0xFFFF */
+ return 0xFFFF;
+ }
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ /* read 16-bits of data */
+ for (i = 0; i < 16; i++) {
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ data <<= 1;
+ data |= mdio_bb_get_mdio(priv);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ }
+
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+
+ debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data);
+
+ return data;
+}
+
+static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv,
+ u8 addr, u8 reg, u16 val)
+{
+ int i;
+
+ mdio_bb_pre(priv, 1, addr, reg);
+ /* send the TA (2-bits of turn-around '10') */
+ mdio_bb_set_mdio(priv, 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdio(priv, 0);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* write 16-bits of data */
+ for (i = 0; i < 16; i++) {
+ mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ val <<= 1;
+ }
+ /* tri-state MDIO */
+ mdio_bb_tristate_mdio(priv);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+}
+
+static u16 cpld_read(struct udevice *dev, u16 addr)
+{
+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+ /* random flash reads require 2 reads: first read is unreliable */
+ if (addr >= CPLD_ADDR_PCB_VERSION)
+ mdio_bb_read(priv, addr >> 5, addr & 0x1f);
+
+ return mdio_bb_read(priv, addr >> 5, addr & 0x1f);
+}
+
+static void cpld_write(struct udevice *dev, u16 addr, u16 data)
+{
+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+ mdio_bb_write(priv, addr >> 5, addr & 0x1f, data);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *dev;
+ u16 addr, val;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+ DM_DRIVER_GET(sysreset_renesas_v3msk),
+ &dev);
+ if (ret)
+ return ret;
+
+ if (argc == 2 && strcmp(argv[1], "info") == 0) {
+ printf("Product: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) |
+ cpld_read(dev, CPLD_ADDR_PRODUCT_L));
+ printf("CPLD version: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) |
+ cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
+ printf("Mode setting (MD0..26): 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) |
+ cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L));
+ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
+ (cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff,
+ (cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf);
+ printf("Power config: 0x%08x\n",
+ cpld_read(dev, CPLD_ADDR_POWER_CFG));
+ printf("Periferals config: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) |
+ cpld_read(dev, CPLD_ADDR_PERI_CFG1));
+ printf("PCB version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8,
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff);
+ printf("SOC version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8,
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff);
+ printf("PCB S/N: %d\n",
+ (cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) |
+ cpld_read(dev, CPLD_ADDR_PCB_SN_L));
+ return 0;
+ }
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) {
+ printf("cpld invalid addr\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 3 && strcmp(argv[1], "read") == 0) {
+ printf("0x%x\n", cpld_read(dev, addr));
+ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+ val = simple_strtoul(argv[3], NULL, 16);
+ cpld_write(dev, addr, val);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(cpld, 4, 1, do_cpld,
+ "CPLD access",
+ "info\n"
+ "cpld read addr\n"
+ "cpld write addr val\n"
+);
+
+static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+ return -EINPROGRESS;
+}
+
+static int renesas_v3msk_sysreset_probe(struct udevice *dev)
+{
+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+ if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
+ GPIOD_IS_IN))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ /* V3MSK Videobox Mini board has CANFD PHY connected
+ * we must shutdown this chip to use bb pins
+ */
+ gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ return 0;
+}
+
+static struct sysreset_ops renesas_v3msk_sysreset = {
+ .request = renesas_v3msk_sysreset_request,
+};
+
+static const struct udevice_id renesas_v3msk_sysreset_ids[] = {
+ { .compatible = "renesas,v3msk-cpld" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_v3msk) = {
+ .name = "renesas_v3msk_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &renesas_v3msk_sysreset,
+ .probe = renesas_v3msk_sysreset_probe,
+ .of_match = renesas_v3msk_sysreset_ids,
+ .priv_auto = sizeof(struct renesas_v3msk_sysreset_priv),
+};
diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c
index 19f09e0..32284b2 100644
--- a/board/renesas/whitehawk/whitehawk.c
+++ b/board/renesas/whitehawk/whitehawk.c
@@ -65,8 +65,3 @@
return 0;
}
-
-void reset_cpu(void)
-{
- writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index c99ffdd..3c773d0 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -18,10 +18,10 @@
static struct efi_fw_image fw_images[ROCKPI4_UPDATABLE_IMAGES] = {0};
struct efi_capsule_update_info update_info = {
+ .num_images = ROCKPI4_UPDATABLE_IMAGES,
.images = fw_images,
};
-u8 num_image_type_guids = ROCKPI4_UPDATABLE_IMAGES;
#endif
#ifndef CONFIG_SPL_BUILD
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 2e44bdf..c7b6cb7 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -67,10 +67,10 @@
struct efi_capsule_update_info update_info = {
.dfu_string = "sf 0:0=u-boot-bin raw 0x100000 0x50000;"
"u-boot-env raw 0x150000 0x200000",
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile
index 4a46de9..1acd067 100644
--- a/board/socionext/developerbox/Makefile
+++ b/board/socionext/developerbox/Makefile
@@ -7,3 +7,4 @@
#
obj-y := developerbox.o
+obj-$(CONFIG_FWU_MDATA_MTD) += fwu_plat.o
diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
index 16e14d4..204e5a4 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -20,6 +20,13 @@
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
struct efi_fw_image fw_images[] = {
+#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE)
+ {
+ .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
+ .fw_name = u"DEVELOPERBOX-FIP",
+ .image_index = 1,
+ },
+#else
{
.image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
.fw_name = u"DEVELOPERBOX-UBOOT",
@@ -35,16 +42,17 @@
.fw_name = u"DEVELOPERBOX-OPTEE",
.image_index = 3,
},
+#endif
};
struct efi_capsule_update_info update_info = {
.dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;"
"fip.bin raw 180000 78000;"
"optee.bin raw 500000 100000",
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
static struct mm_region sc2a11_mem_map[] = {
diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c
new file mode 100644
index 0000000..e724e70
--- /dev/null
+++ b/board/socionext/developerbox/fwu_plat.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <efi_loader.h>
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <memalign.h>
+#include <mtd.h>
+
+#define DFU_ALT_BUF_LEN 256
+
+/* Generate dfu_alt_info from partitions */
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+ struct mtd_info *mtd;
+ int ret;
+
+ memset(buf, 0, sizeof(buf));
+
+ mtd_probe_devices();
+
+ mtd = get_mtd_device_nm("nor1");
+ if (IS_ERR_OR_NULL(mtd))
+ return;
+
+ ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd);
+ if (ret < 0) {
+ log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret);
+ return;
+ }
+ log_debug("Make dfu_alt_info: '%s'\n", buf);
+
+ env_set("dfu_alt_info", buf);
+}
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 02e6afb..1d63c81 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -13,7 +13,6 @@
#include <common.h>
#include <clock_legacy.h>
#include <env.h>
-#include <env_internal.h>
#include <init.h>
#include <pci.h>
#include <uuid.h>
@@ -222,19 +221,3 @@
{
return 333333330;
}
-
-enum env_location env_get_location(enum env_operation op, int prio)
-{
- if (op == ENVOP_SAVE || op == ENVOP_ERASE)
- return ENVL_FLASH;
-
- switch (prio) {
- case 0:
- return ENVL_NOWHERE;
- case 1:
- return ENVL_FLASH;
- default:
- return ENVL_UNKNOWN;
- }
- return ENVL_UNKNOWN;
-}
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index cb14c2f..6fa5cf4 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -275,9 +275,8 @@
{
setup_iomux_uart();
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
+ if (CONFIG_IS_ENABLED(SATA))
+ setup_sata();
setup_fec();
return 0;
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 1a1b184..5b28ccd 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -92,10 +92,10 @@
struct efi_fw_image fw_images[1];
struct efi_capsule_update_info update_info = {
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
int board_early_init_f(void)
diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig
deleted file mode 100644
index 95973b4..0000000
--- a/board/ti/ti816x/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TI816X_EVM
-
-config SYS_BOARD
- default "ti816x"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "ti816x_evm"
-
-endif
diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS
deleted file mode 100644
index fd9a98f..0000000
--- a/board/ti/ti816x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TI816X BOARD
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-F: board/ti/ti816x/
-F: include/configs/ti816x_evm.h
-F: configs/ti816x_evm_defconfig
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
deleted file mode 100644
index f12712a..0000000
--- a/board/ti/ti816x/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
-# Antoine Tenart, <atenart@adeneo-embedded.com>
-#
-# Based on TI-PSP-04.00.02.14 :
-#
-# Copyright (C) 2009, Texas Instruments, Incorporated
-
-obj-y := evm.o
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
deleted file mode 100644
index 8c70835..0000000
--- a/board/ti/ti816x/evm.c
+++ /dev/null
@@ -1,140 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * evm.c
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <init.h>
-#include <net.h>
-#include <spl.h>
-#include <asm/cache.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_MTD_RAW_NAND)
- gpmc_init();
-#endif
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
- struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
- if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- else
- printf("Unable to read MAC address. Set <ethaddr>\n");
- }
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-static struct module_pin_mux mmc_pin_mux[] = {
- { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
- { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { -1 },
-};
-
-void set_uart_mux_conf(void) {}
-
-void set_mux_conf_regs(void)
-{
- configure_module_pin_mux(mmc_pin_mux);
-}
-
-/*
- * EMIF Paramters. Refer the EMIF register documentation and the
- * memory datasheet for details. This is for 796 MHz.
- */
-#define EMIF_TIM1 0x1779C9FE
-#define EMIF_TIM2 0x50608074
-#define EMIF_TIM3 0x009F857F
-#define EMIF_SDREF 0x10001841
-#define EMIF_SDCFG 0x62A73832
-#define EMIF_PHYCFG 0x00000110
-static const struct emif_regs ddr3_emif_regs = {
- .sdram_config = EMIF_SDCFG,
- .ref_ctrl = EMIF_SDREF,
- .sdram_tim1 = EMIF_TIM1,
- .sdram_tim2 = EMIF_TIM2,
- .sdram_tim3 = EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
-};
-
-static const struct cmd_control ddr3_ctrl = {
- .cmd0csratio = 0x100,
- .cmd0iclkout = 0x001,
- .cmd1csratio = 0x100,
- .cmd1iclkout = 0x001,
- .cmd2csratio = 0x100,
- .cmd2iclkout = 0x001,
-};
-
-/* These values are obtained from the CCS app */
-#define RD_DQS_GATE (0x1B3)
-#define RD_DQS (0x35)
-#define WR_DQS (0x93)
-static struct ddr_data ddr3_data = {
- .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
- .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
- .datawiratio0 = ((0x20<<10) | 0x20<<0),
- .datagiratio0 = ((0x20<<10) | 0x20<<0),
- .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
- .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
-};
-
-static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
- .dmm_lisa_map_0 = 0x00000000,
- .dmm_lisa_map_1 = 0x00000000,
- .dmm_lisa_map_2 = 0x80640300,
- .dmm_lisa_map_3 = 0xC0640320,
-};
-
-void sdram_init(void)
-{
- /*
- * Pass in our DDR3 config information and that we have 2 EMIFs to
- * configure.
- */
- config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
- &evm_lisa_map_regs, 2);
-}
-#endif /* CONFIG_SPL_BUILD */
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index f335d5b..8f23cda 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -76,17 +76,23 @@
static int read_eeprom(BSP_VS_HWPARAM *header)
{
- i2c_set_bus_num(1);
+ int rc;
+ struct udevice *dev;
+ struct udevice *bus;
+
+ rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
+ if (rc)
+ return rc;
/* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ if (dm_i2c_probe(bus, CONFIG_SYS_I2C_EEPROM_ADDR, 0, &dev)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
return -ENODEV;
}
/* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ if (dm_i2c_read(dev, 0, (uchar *)header,
sizeof(BSP_VS_HWPARAM))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
@@ -173,34 +179,28 @@
void am33xx_spl_board_init(void)
{
- int mpu_vdd;
- int sil_rev;
+ int sil_rev, mpu_vdd;
+ int freq;
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
- /*
- * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
- * MPU frequencies we support we use a CORE voltage of
- * 1.1375V. For MPU voltage we need to switch based on
- * the frequency we are running at.
- */
+ enable_i2c1_pin_mux();
i2c_set_bus_num(1);
- printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED);
+ freq = am335x_get_efuse_mpu_max_freq(cdev);
- if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
- puts("i2c: cannot access TPS65910\n");
+ /*
+ * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
+ * MPU frequencies we support we use a CORE voltage of
+ * 1.1375V. For MPU voltage we need to switch based on
+ * the frequency we are running at.
+ */
+ if (power_tps65910_init(1))
return;
- }
-
/*
* Depending on MPU clock and PG we will need a different
* VDD to drive at that speed.
*/
sil_rev = readl(&cdev->deviceid) >> 28;
- mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
- dpll_mpu_opp100.m);
+ mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
/* Tell the TPS65910 to use i2c */
tps65910_set_i2c_control();
@@ -213,12 +213,6 @@
if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
return;
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* Set MPU Frequency to what we detected now that voltages are set */
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-
writel(0x000010ff, PRM_DEVICE_INST + 4);
}
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index da995dd..4891445 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -352,9 +352,8 @@
int board_early_init_f(void)
{
setup_iomux_uart();
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
+ if (CONFIG_IS_ENABLED(SATA))
+ setup_sata();
return 0;
}
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index d071ebf..0328d68 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -52,10 +52,10 @@
};
struct efi_capsule_update_info update_info = {
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-u8 num_image_type_guids = ARRAY_SIZE(fw_images);
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
#define EEPROM_HEADER_MAGIC 0xdaaddeed
diff --git a/cmd/fdt.c b/cmd/fdt.c
index aae3278..2401ea8 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -733,7 +733,7 @@
gd->fdt_blob = blob;
cfg_noffset = fit_conf_get_node(working_fdt, NULL);
- if (!cfg_noffset) {
+ if (cfg_noffset < 0) {
printf("Could not find configuration node: %s\n",
fdt_strerror(cfg_noffset));
return CMD_RET_FAILURE;
diff --git a/cmd/fs.c b/cmd/fs.c
index 5ad1164..6044f73 100644
--- a/cmd/fs.c
+++ b/cmd/fs.c
@@ -20,7 +20,7 @@
"determine a file's size",
"<interface> <dev[:part]> <filename>\n"
" - Find file 'filename' from 'dev' on 'interface'\n"
- " and determine its size."
+ " determine its size, and store in the 'filesize' variable."
);
static int do_load_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c
index f04af27..5ecda45 100644
--- a/cmd/fwu_mdata.c
+++ b/cmd/fwu_mdata.c
@@ -43,23 +43,10 @@
int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
- struct udevice *dev;
int ret = CMD_RET_SUCCESS, res;
- struct fwu_mdata mdata = { 0 };
+ struct fwu_mdata mdata;
- if (uclass_get_device(UCLASS_FWU_MDATA, 0, &dev) || !dev) {
- log_err("Unable to get FWU metadata device\n");
- return CMD_RET_FAILURE;
- }
-
- res = fwu_check_mdata_validity();
- if (res < 0) {
- log_err("FWU Metadata check failed\n");
- ret = CMD_RET_FAILURE;
- goto out;
- }
-
- res = fwu_get_mdata(dev, &mdata);
+ res = fwu_get_mdata(&mdata);
if (res < 0) {
log_err("Unable to get valid FWU metadata\n");
ret = CMD_RET_FAILURE;
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 12eae06..9e4ee4b 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -43,28 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_ENV_IS_IN_EEPROM) || \
- defined(CONFIG_ENV_IS_IN_FLASH) || \
- defined(CONFIG_ENV_IS_IN_MMC) || \
- defined(CONFIG_ENV_IS_IN_FAT) || \
- defined(CONFIG_ENV_IS_IN_EXT4) || \
- defined(CONFIG_ENV_IS_IN_NAND) || \
- defined(CONFIG_ENV_IS_IN_NVRAM) || \
- defined(CONFIG_ENV_IS_IN_ONENAND) || \
- defined(CONFIG_ENV_IS_IN_SPI_FLASH) || \
- defined(CONFIG_ENV_IS_IN_REMOTE) || \
- defined(CONFIG_ENV_IS_IN_UBI)
-
-#define ENV_IS_IN_DEVICE
-
-#endif
-
-#if !defined(ENV_IS_IN_DEVICE) && \
- !defined(CONFIG_ENV_IS_NOWHERE)
-# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\
-NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
-#endif
-
/*
* Maximum expected input data size for import command
*/
@@ -596,7 +574,7 @@
}
#endif /* CONFIG_CMD_EDITENV */
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
static int do_env_save(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -1105,7 +1083,7 @@
int eval_flags = 0;
int eval_results = 0;
bool quiet = false;
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
enum env_location loc;
#endif
@@ -1148,7 +1126,7 @@
/* evaluate whether environment can be persisted */
if (eval_flags & ENV_INFO_IS_PERSISTED) {
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
loc = env_get_location(ENVOP_SAVE, gd->env_load_prio);
if (ENVL_NOWHERE != loc && ENVL_UNKNOWN != loc) {
if (!quiet)
@@ -1229,7 +1207,7 @@
#if defined(CONFIG_CMD_RUN)
U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
#endif
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
U_BOOT_CMD_MKENT(save, 1, 0, do_env_save, "", ""),
#if defined(CONFIG_CMD_ERASEENV)
U_BOOT_CMD_MKENT(erase, 1, 0, do_env_erase, "", ""),
@@ -1320,7 +1298,7 @@
#if defined(CONFIG_CMD_RUN)
"env run var [...] - run commands in an environment variable\n"
#endif
-#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
+#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT)
"env save - save environment\n"
#if defined(CONFIG_CMD_ERASEENV)
"env erase - erase environment\n"
diff --git a/cmd/version.c b/cmd/version.c
index 190ef6a..87e1fa4 100644
--- a/cmd/version.c
+++ b/cmd/version.c
@@ -19,6 +19,8 @@
U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
const char version_string[] = U_BOOT_VERSION_STRING;
+const unsigned short version_num = U_BOOT_VERSION_NUM;
+const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH;
static int do_version(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 171069f..cee8724 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -324,7 +324,7 @@
/* I can almost use ordinary FILE *. Is open_memstream() universally
* available? Where is it documented? */
struct in_str {
- const char *p;
+ const unsigned char *p;
#ifndef __U_BOOT__
char peek_buf[2];
#endif
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2c042ad..6774ba5 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1345,96 +1345,6 @@
automatic power-off when the temperature gets too high or low. Other
devices may be discrete but connected on a suitable bus.
-config SPL_USB_HOST
- bool "Support USB host drivers"
- help
- Enable access to USB (Universal Serial Bus) host devices so that
- SPL can load U-Boot from a connected USB peripheral, such as a USB
- flash stick. While USB takes a little longer to start up than most
- buses, it is very flexible since many different types of storage
- device can be attached. This option enables the drivers in
- drivers/usb/host as part of an SPL build.
-
-config SPL_USB_STORAGE
- bool "Support loading from USB"
- depends on SPL_USB_HOST
- help
- Enable support for USB devices in SPL. This allows use of USB
- devices such as hard drives and flash drivers for loading U-Boot.
- The actual drivers are enabled separately using the normal U-Boot
- config options. This enables loading from USB using a configured
- device.
-
-config SYS_USB_FAT_BOOT_PARTITION
- int "Partition on USB to use to load U-Boot from"
- depends on SPL_USB_STORAGE
- default 1
- help
- Partition on the USB storage device to load U-Boot from
-
-config SPL_USB_GADGET
- bool "Suppport USB Gadget drivers"
- help
- Enable USB Gadget API which allows to enable USB device functions
- in SPL.
-
-if SPL_USB_GADGET
-
-config SPL_USB_ETHER
- bool "Support USB Ethernet drivers"
- depends on SPL_NET
- help
- Enable access to the USB network subsystem and associated
- drivers in SPL. This permits SPL to load U-Boot over a
- USB-connected Ethernet link (such as a USB Ethernet dongle) rather
- than from an onboard peripheral. Environment support is required
- since the network stack uses a number of environment variables.
- See also SPL_NET and SPL_ETH.
-
-config SPL_DFU
- bool "Support DFU (Device Firmware Upgrade)"
- select SPL_HASH
- select SPL_DFU_NO_RESET
- depends on SPL_RAM_SUPPORT
- help
- This feature enables the DFU (Device Firmware Upgrade) in SPL with
- RAM memory device support. The ROM code will load and execute
- the SPL built with dfu. The user can load binaries (u-boot/kernel) to
- selected device partition from host-pc using dfu-utils.
- This feature is useful to flash the binaries to factory or bare-metal
- boards using USB interface.
-
-choice
- bool "DFU device selection"
- depends on SPL_DFU
-
-config SPL_DFU_RAM
- bool "RAM device"
- depends on SPL_DFU && SPL_RAM_SUPPORT
- help
- select RAM/DDR memory device for loading binary images
- (u-boot/kernel) to the selected device partition using
- DFU and execute the u-boot/kernel from RAM.
-
-endchoice
-
-config SPL_USB_SDP_SUPPORT
- bool "Support SDP (Serial Download Protocol)"
- depends on SPL_SERIAL
- help
- Enable Serial Download Protocol (SDP) device support in SPL. This
- allows to download images into memory and execute (jump to) them
- using the same protocol as implemented by the i.MX family's boot ROM.
-
-config SPL_SDP_USB_DEV
- int "SDP USB controller index"
- default 0
- depends on SPL_USB_SDP_SUPPORT
- help
- Some boards have USB controller other than 0. Define this option
- so it can be used in compiled environment.
-endif
-
config SPL_WATCHDOG
bool "Support watchdog drivers"
imply SPL_WDT if !HW_WATCHDOG
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 28124a8..d74acec 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -331,7 +331,7 @@
conf_noffset = fit_conf_get_node((const void *)header,
fit_uname_config);
- if (conf_noffset <= 0)
+ if (conf_noffset < 0)
return 0;
for (idx = 0;
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 090b902..6ef3c78 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -18,7 +18,6 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
@@ -57,10 +56,10 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
+# CONFIG_TI_SYSC is not set
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SPEED=1000
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP_HS_ADMA=y
@@ -79,6 +78,8 @@
CONFIG_DM_MDIO=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_PMIC_CHILDREN is not set
CONFIG_SPL_POWER_TPS65910=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
@@ -94,5 +95,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_ETHER=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_WDT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index c42d2a0..e581acc 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -34,8 +34,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_SPL=y
@@ -89,8 +87,10 @@
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
CONFIG_LZO=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index ffeeb85..a179f1e 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -39,8 +39,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_EXTENSION=y
@@ -115,10 +113,12 @@
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
CONFIG_WDT=y
# CONFIG_SPL_WDT is not set
CONFIG_DYNAMIC_CRC_TABLE=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index ad0fa46..a485cc6 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -45,8 +45,6 @@
CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL"
CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_ASKENV=y
@@ -127,10 +125,12 @@
CONFIG_USB_MUSB_TI=y
# CONFIG_USB_STORAGE is not set
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_BMP_16BPP=y
CONFIG_SPL_WDT=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 34525d6..3238620 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -34,9 +34,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
@@ -97,6 +94,7 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_OMAP=y
@@ -106,8 +104,10 @@
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 64ecd92..406c0fc 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -30,9 +30,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
@@ -98,6 +95,7 @@
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_OMAP=y
@@ -106,7 +104,9 @@
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 6715a25..466b12e 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -34,10 +34,6 @@
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
@@ -95,6 +91,7 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_OMAP=y
@@ -103,9 +100,12 @@
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index fe71738..39fdc05 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -44,8 +44,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -120,7 +118,9 @@
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
CONFIG_LIBAVB=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 41fa6f3..76ec5ed 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -35,6 +35,7 @@
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_MMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 4589624..b817e62 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -59,10 +59,6 @@
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x800000
@@ -153,16 +149,20 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
+CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 023ee63..96cb437 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -65,10 +65,6 @@
CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -159,6 +155,7 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
@@ -166,9 +163,12 @@
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index f294a45..c3a2f09 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -61,10 +61,6 @@
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
@@ -167,15 +163,19 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
+CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 8b01925..88f68aa 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -51,8 +51,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -130,8 +128,10 @@
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig
index 01e46e6..8da49c7 100644
--- a/configs/am65x_evm_r5_usbmsc_defconfig
+++ b/configs/am65x_evm_r5_usbmsc_defconfig
@@ -50,9 +50,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_STORAGE=y
-CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -120,12 +117,15 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index d7342c4..dcee517 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -43,9 +43,6 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=48
CONFIG_SYS_CBSIZE=1024
CONFIG_SYS_PBSIZE=1055
@@ -113,12 +110,15 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index db68b21..d1eb2ab 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -59,7 +59,6 @@
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_EARLY=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig
index d369505..638976d 100644
--- a/configs/aristainetos2ccslb_defconfig
+++ b/configs/aristainetos2ccslb_defconfig
@@ -59,7 +59,6 @@
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_EARLY=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index e25cde9..9d2a201 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -42,9 +42,6 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=48
CONFIG_SYS_CBSIZE=1024
CONFIG_SYS_PBSIZE=1056
@@ -110,12 +107,15 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index a45d3cb..c1094b4 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -42,9 +42,6 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -112,15 +109,18 @@
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="dh"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x17ffffc0
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
CONFIG_BZIP2=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 4b3a4bf..a5396f7 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -48,9 +48,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_CBSIZE=2048
@@ -129,12 +126,15 @@
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Liebherr"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=15000
CONFIG_IMX_WATCHDOG=y
CONFIG_PANIC_HANG=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 371c888..14dff63 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -47,8 +47,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_SPL=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
@@ -148,6 +146,8 @@
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 3165b9b..0d6d9ef 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -44,8 +44,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
@@ -141,6 +139,8 @@
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 6ed98cf..506a65a 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -43,8 +43,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
@@ -128,6 +126,8 @@
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_SPL_DFU=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index 07e357e..faa22f9 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -41,9 +41,6 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -121,15 +118,18 @@
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Congatec"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_IPUV3=y
CONFIG_IMX_VIDEO_SKIP=y
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index 15dc16b..8626918 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig
@@ -52,6 +52,9 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_ETHERNET_ID=y
+CONFIG_DM_ETH_PHY=y
CONFIG_SH_ETHER=y
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index ccccb95..a811653 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -77,7 +77,6 @@
CONFIG_MULTI_DTB_FIT=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_PART=1
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 2bc4679..2814e2c 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -42,9 +42,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x800
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=543
@@ -116,9 +113,12 @@
CONFIG_MXC_UART=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig
index b322083..f3da19d 100644
--- a/configs/imx6ulz_smm_m2_defconfig
+++ b/configs/imx6ulz_smm_m2_defconfig
@@ -27,9 +27,6 @@
CONFIG_SPL_DMA=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
@@ -71,9 +68,12 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="BSH"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x877fffc0
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig
index e18fcf9..c43aed4 100644
--- a/configs/imx7_cm_defconfig
+++ b/configs/imx7_cm_defconfig
@@ -30,9 +30,6 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
@@ -102,13 +99,16 @@
# CONFIG_FSL_QSPI_AHB_FULL_MAP is not set
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index 00f7c54..13bd195 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -51,9 +51,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
@@ -133,14 +130,17 @@
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
# CONFIG_USB_STORAGE is not set
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Menlo"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 4a96bd2..bb02b9b 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -40,9 +40,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -134,13 +131,16 @@
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index dacd473..ac9810f 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -39,9 +39,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
@@ -108,14 +105,17 @@
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
# CONFIG_USB_STORAGE is not set
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig
index 4f988f5..9fdce5c 100644
--- a/configs/imx8mm_phg_defconfig
+++ b/configs/imx8mm_phg_defconfig
@@ -39,9 +39,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
@@ -106,14 +103,17 @@
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
# CONFIG_USB_STORAGE is not set
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index e40900f..cc68a21 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -47,7 +47,7 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
@@ -64,8 +64,6 @@
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
@@ -197,9 +195,11 @@
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
+CONFIG_SPL_DFU=y
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 94a6523..c4dd336 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -43,7 +43,7 @@
CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
@@ -61,8 +61,6 @@
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -160,10 +158,12 @@
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_LIB_RATIONAL=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index eaf83e0..32ac47c 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -62,8 +62,6 @@
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
@@ -201,9 +199,11 @@
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
+CONFIG_SPL_DFU=y
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index afe1f3a..72ca19c 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -69,8 +69,6 @@
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -173,10 +171,12 @@
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_LIB_RATIONAL=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 594c8da..37c1fde 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -62,8 +62,6 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
@@ -205,9 +203,11 @@
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_SPL_DFU=y
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 4ddbe8f..1e66ac2 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -68,8 +68,6 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -169,10 +167,12 @@
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_PANIC_HANG=y
diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig
index 0dbf7ea..d54e603 100644
--- a/configs/kontron-sl-mx6ul_defconfig
+++ b/configs/kontron-sl-mx6ul_defconfig
@@ -36,9 +36,6 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -100,11 +97,14 @@
CONFIG_MXC_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index b846a83..973b2ea 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -50,8 +50,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=1050
@@ -144,8 +142,10 @@
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Purism"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_FUNCTION_ACM=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 503a733..ee518ca 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -35,9 +35,6 @@
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
@@ -101,16 +98,19 @@
CONFIG_MXC_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
# CONFIG_VIDEO_BPP8 is not set
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index a0befcc..0a8b047 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -33,9 +33,6 @@
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
@@ -109,13 +106,16 @@
CONFIG_MXC_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
# CONFIG_VIDEO_BPP8 is not set
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 1572afb..0e03660 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -33,9 +33,6 @@
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
@@ -94,13 +91,16 @@
CONFIG_SOFT_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig
index 637860c..8e3938d 100644
--- a/configs/myir_mys_6ulx_defconfig
+++ b/configs/myir_mys_6ulx_defconfig
@@ -23,8 +23,6 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -70,4 +68,6 @@
CONFIG_SYSINFO_SMBIOS=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 9386d6f..2d06621 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -20,7 +20,6 @@
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -63,6 +62,7 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Phytec"
CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 64ebc9f..327ea56 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -20,7 +20,6 @@
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -54,6 +53,7 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Phytec"
CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig
index ff50909..4fd5880 100644
--- a/configs/pico-dwarf-imx6ul_defconfig
+++ b/configs/pico-dwarf-imx6ul_defconfig
@@ -27,9 +27,6 @@
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
@@ -72,9 +69,12 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig
index 8a5ed1e..2cd906a 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -26,9 +26,6 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index 58d6d14..c430b4d 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -28,9 +28,6 @@
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
@@ -75,9 +72,12 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 3cdb4d3..b63281e 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -26,9 +26,6 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
@@ -79,14 +76,17 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index 821cb97..be7b119 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -31,9 +31,6 @@
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -85,11 +82,14 @@
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
# CONFIG_BACKLIGHT is not set
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 78cd63c..a6cbc51 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -28,9 +28,6 @@
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
@@ -79,12 +76,15 @@
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_VIDEO_MXS=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 74aab86..546e1e6 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -28,9 +28,6 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -77,15 +74,18 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 447342f..f11e1f4 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -26,9 +26,6 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig
index 8a5ed1e..2cd906a 100644
--- a/configs/pico-nymph-imx7d_defconfig
+++ b/configs/pico-nymph-imx7d_defconfig
@@ -26,9 +26,6 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index b7d1ccd..3c822d1 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -28,9 +28,6 @@
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
@@ -75,9 +72,12 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 2f028c2..3e26aae 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -26,9 +26,6 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
@@ -80,14 +77,17 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig
new file mode 100644
index 0000000..74a140a
--- /dev/null
+++ b/configs/r8a77970_v3msk_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=16666666
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77970-v3msk-u-boot"
+CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77970=y
+CONFIG_TARGET_V3MSK=y
+CONFIG_SPL_STACK=0xe6304000
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb"
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0xe631f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2068
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
+CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_SYSRESET=y
diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig
new file mode 100644
index 0000000..564ff2d
--- /dev/null
+++ b/configs/r8a77980_v3hsk_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=16666666
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot"
+CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77980=y
+CONFIG_TARGET_V3HSK=y
+CONFIG_SPL_STACK=0xe6304000
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
+# CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0xe631f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2068
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
+CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_SH_ETHER=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_SYSRESET=y
diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig
index 93031c7..9dec10e 100644
--- a/configs/seeed_npi_imx6ull_defconfig
+++ b/configs/seeed_npi_imx6ull_defconfig
@@ -24,8 +24,6 @@
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -75,4 +73,6 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 6b67021..ba5990b 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -68,7 +68,6 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe000000.nor_flash:13312k(system1),13312k(system2),5120k(data),128k(env),128k(env-red),768k(u-boot);socrates_nand:256M(ubi-data1),-(ubi-data2)"
# CONFIG_CMD_IRQ is not set
CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR_REDUND=0xFFF00000
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 93494f8..430d0bc 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -55,8 +55,6 @@
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_TARGET="u-boot.itb"
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
@@ -166,11 +164,13 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="dh"
CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_FAT_WRITE=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index b54ff93..f23875f 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -53,8 +53,6 @@
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
CONFIG_SPL_TARGET="u-boot.itb"
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
@@ -165,11 +163,13 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="dh"
CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_FAT_WRITE=y
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
index 68f7bac..8e7236b 100644
--- a/configs/synquacer_developerbox_defconfig
+++ b/configs/synquacer_developerbox_defconfig
@@ -1,13 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_SYNQUACER=y
-CONFIG_TEXT_BASE=0x08200000
+CONFIG_POSITION_INDEPENDENT=y
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe0000000
CONFIG_SF_DEFAULT_SPEED=31250000
CONFIG_ENV_SIZE=0x30000
-CONFIG_ENV_OFFSET=0x300000
+CONFIG_ENV_OFFSET=0x580000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
@@ -97,3 +97,11 @@
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_FWU_MULTI_BANK_UPDATE=y
+CONFIG_FWU_MDATA=y
+CONFIG_FWU_MDATA_MTD=y
+CONFIG_FWU_NUM_BANKS=2
+CONFIG_FWU_NUM_IMAGES_PER_BANK=1
+CONFIG_CMD_FWU_METADATA=y
+CONFIG_TOOLS_MKFWUMDATA=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
deleted file mode 100644
index a4bc993..0000000
--- a/configs/ti816x_evm_defconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x1C0000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm"
-CONFIG_SPL_TEXT_BASE=0x40400000
-CONFIG_TI816X=y
-CONFIG_TARGET_TI816X_EVM=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x1E0000
-CONFIG_SYS_CLK_FREQ=27000000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk"
-CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr}"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_SPL_MAX_SIZE=0xfff1b400
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_DNS2=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RETRY_COUNT=10
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
-CONFIG_SYS_NAND_PAGE_SIZE=0x800
-CONFIG_SYS_NAND_OOBSIZE=0x40
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-# CONFIG_USE_PRIVATE_LIBGCC is not set
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index 698a41d..1cfa342 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -20,7 +20,6 @@
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_USB_HOST=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
@@ -59,6 +58,7 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Variscite"
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 2aa272f..cbb8259 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -37,9 +37,6 @@
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
@@ -96,13 +93,16 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Softing"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
diff --git a/doc/README.rmobile b/doc/README.rmobile
index ea170a2..524d839 100644
--- a/doc/README.rmobile
+++ b/doc/README.rmobile
@@ -35,6 +35,7 @@
| R8A77965 M3-N | Renesas Electronics ULCB | r8a77965_ulcb
|---------------+----------------------------------------+-------------------
| R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig
+| R8A77970 V3M | Renesas Electronics V3MSK | r8a77970_v3msk_defconfig
|---------------+----------------------------------------+-------------------
| R8A77995 D3 | Renesas Electronics Draak | r8a77995_draak_defconfig
'===============+========================================+===================
diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst
index 2d943c2..aa7080e 100644
--- a/doc/board/socionext/developerbox.rst
+++ b/doc/board/socionext/developerbox.rst
@@ -57,14 +57,20 @@
You can install the SNI_NOR_UBOOT.fd via NOR flash writer.
-Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port.
-Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing.
+Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine
+or other mezzanine which can connect to the LS-UART0 port.
+Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the
+board on again. The flash writer program will be started automatically;
+don't forget to turn the DSW2-7 off again after flashing.
-*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail*
+*!!CAUTION!! If you write the U-Boot image on wrong address, the board can
+be bricked. See below page if you need to recover the bricked board. See
+the following page for more details*
https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html
-When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0::
+When the serial flasher is running correctly it will show the following boot
+messages printed to the LS-UART0 console::
/*------------------------------------------*/
@@ -81,7 +87,143 @@
flash rawwrite 200000 100000
>> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) <<
-*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).*
+*!!NOTE!! The flasher command parameter is different from the command for
+board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the
+size 100000 (1-five-0, 1M in hex).*
-After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board.
+After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and
+reset the board.
+
+Enable FWU Multi Bank Update
+============================
+
+DeveloperBox supports the FWU Multi Bank Update. You *MUST* update both
+*SCP firmware* and *TF-A* for this feature. This will change the layout and
+the boot process but you can switch back to the normal one by changing
+the DSW 1-4 off.
+
+Configure U-Boot
+----------------
+
+To enable the FWU Multi Bank Update on the DeveloperBox board the
+configs/synquacer_developerbox_defconfig enables default FWU configuration ::
+
+ CONFIG_FWU_MULTI_BANK_UPDATE=y
+ CONFIG_FWU_MDATA=y
+ CONFIG_FWU_MDATA_MTD=y
+ CONFIG_FWU_NUM_BANKS=2
+ CONFIG_FWU_NUM_IMAGES_PER_BANK=1
+ CONFIG_CMD_FWU_METADATA=y
+
+And build it::
+
+ cd u-boot/
+ export ARCH=arm64
+ export CROSS_COMPILE=aarch64-linux-gnu-
+ make synquacer_developerbox_defconfig
+ make -j `noproc`
+ cd ../
+
+By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are
+set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image
+which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional).
+You can use fiptool to compose the FIP image from those firmware images.
+
+Rebuild SCP firmware
+--------------------
+
+Rebuild SCP firmware which supports FWU Multi Bank Update as below::
+
+ cd SCP-firmware/
+ OUT=./build/product/synquacer
+ ROMFW_FILE=$OUT/scp_romfw/$SCP_BUILD_MODE/bin/scp_romfw.bin
+ RAMFW_FILE=$OUT/scp_ramfw/$SCP_BUILD_MODE/bin/scp_ramfw.bin
+ ROMRAMFW_FILE=scp_romramfw_release.bin
+
+ make CC=arm-none-eabi-gcc PRODUCT=synquacer MODE=release
+ tr "\000" "\377" < /dev/zero | dd of=${ROMRAMFW_FILE} bs=1 count=196608
+ dd if=${ROMFW_FILE} of=${ROMRAMFW_FILE} bs=1 conv=notrunc seek=0
+ dd if=${RAMFW_FILE} of=${ROMRAMFW_FILE} bs=1 seek=65536
+ cd ../
+
+And you can get the `scp_romramfw_release.bin` file.
+
+Rebuild OPTEE firmware
+----------------------
+
+Rebuild OPTEE to use in new-layout FIP as below::
+
+ cd optee_os/
+ make -j`nproc` PLATFORM=synquacer ARCH=arm \
+ CROSS_COMPILE64=aarch64-linux-gnu- CFG_ARM64_core=y \
+ CFG_CRYPTO_WITH_CE=y CFG_CORE_HEAP_SIZE=524288 CFG_CORE_DYN_SHM=y \
+ CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 CFG_TEE_TA_LOG_LEVEL=1
+ cp out/arm-plat-synquacer/core/tee-pager_v2.bin ../arm-trusted-firmware/
+
+The produced `tee-pager_v2.bin` is to be used while building TF-A next.
+
+
+Rebuild TF-A and FIP
+--------------------
+
+Rebuild TF-A which supports FWU Multi Bank Update as below::
+
+ cd arm-trusted-firmware/
+ make CROSS_COMPILE=aarch64-linux-gnu- -j`nproc` PLAT=synquacer \
+ TRUSTED_BOARD_BOOT=1 SPD=opteed SQ_RESET_TO_BL2=1 GENERATE_COT=1 \
+ MBEDTLS_DIR=../mbedtls BL32=tee-pager_v2.bin \
+ BL33=../u-boot/u-boot.bin all fip fiptool
+
+And make a FIP image.::
+
+ cp build/synquacer/release/fip.bin SPI_NOR_NEWFIP.fd
+ tools/fiptool/fiptool update --tb-fw build/synquacer/release/bl2.bin SPI_NOR_NEWFIP.fd
+
+UUIDs for the FWU Multi Bank Update
+-----------------------------------
+
+FWU multi-bank update requires some UUIDs. The DeveloperBox platform uses
+following UUIDs.
+
+ - Location UUID for the FIP image: 17e86d77-41f9-4fd7-87ec-a55df9842de5
+ - Image type UUID for the FIP image: 10c36d7d-ca52-b843-b7b9-f9d6c501d108
+ - Image UUID for Bank0 : 5a66a702-99fd-4fef-a392-c26e261a2828
+ - Image UUID for Bank1 : a8f868a1-6e5c-4757-878d-ce63375ef2c0
+
+These UUIDs are used for making a FWU metadata image.
+
+u-boot$ ./tools/mkfwumdata -i 1 -b 2 \
+ 17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \
+ ../devbox-fwu-mdata.img
+
+Create Accept & Revert capsules
+
+u-boot$ ./tools/mkeficapsule -A -g 7d6dc310-52ca-43b8-b7b9-f9d6c501d108 NEWFIP_accept.Cap
+u-boot$ ./tools/mkeficapsule -R NEWFIP_revert.Cap
+
+Install via flash writer
+------------------------
+
+As explained in above section, the new FIP image and the FWU metadata image
+can be installed via NOR flash writer.
+
+Once the flasher tool is running we are ready to flash the images.::
+Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.::
+
+ flash rawwrite 600000 180000
+ flash rawwrite a00000 180000
+ >> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) <<
+
+ flash rawwrite 500000 1000
+ flash rawwrite 530000 1000
+ >> Send devbox-fwu-mdata.img via XMODEM (Control-A S in minicom) <<
+
+And write the new SCP firmware.::
+
+ flash write cm3
+ >> Send scp_romramfw_release.bin via XMODEM (Control-A S in minicom) <<
+
+At last, turn on the DSW 3-4 on the board, and reboot.
+Note that if DSW 3-4 is turned off, the DeveloperBox will boot from
+the original EDK2 firmware (or non-FWU U-Boot if you already installed).
diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst
new file mode 100644
index 0000000..0d3a526
--- /dev/null
+++ b/doc/board/ti/j7200_evm.rst
@@ -0,0 +1,332 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Udit Kumar <u-kumar1@ti.com>
+
+J7200 Platforms
+===============
+
+Introduction:
+-------------
+The J7200 family of SoCs are part of K3 Multicore SoC architecture platform
+targeting automotive applications. They are designed as a low power, high
+performance and highly integrated device architecture, adding significant
+enhancement on processing power, graphics capability, video and imaging
+processing, virtualization and coherent memory support.
+
+The device is partitioned into three functional domains, each containing
+specific processing cores and peripherals:
+
+1. Wake-up (WKUP) domain:
+ * Device Management and Security Controller (DMSC)
+
+2. Microcontroller (MCU) domain:
+ * Dual Core ARM Cortex-R5F processor
+
+3. MAIN domain:
+ * Dual core 64-bit ARM Cortex-A72
+
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. code-block:: text
+
+ +------------------------------------------------------------------------+-----------------------+
+ | DMSC | MCU R5 | A72 | MAIN R5/C7x |
+ +------------------------------------------------------------------------+-----------------------+
+ | +--------+ | | | |
+ | | Reset | | | | |
+ | +--------+ | | | |
+ | : | | | |
+ | +--------+ | +-----------+ | | |
+ | | *ROM* |----------|-->| Reset rls | | | |
+ | +--------+ | +-----------+ | | |
+ | | | | : | | |
+ | | ROM | | : | | |
+ | |services| | : | | |
+ | | | | +-------------+ | | |
+ | | | | | *R5 ROM* | | | |
+ | | | | +-------------+ | | |
+ | | |<---------|---|Load and auth| | | |
+ | | | | | tiboot3.bin | | | |
+ | | Start | | +-------------+ | | |
+ | | TIFS |<---------|---| Start | | | |
+ | | | | | TIFS | | | |
+ | +--------+ | +-------------+ | | |
+ | : | | | | | |
+ | +---------+ | | Load | | | |
+ | | *TIFS* | | | system | | | |
+ | +---------+ | | Config data | | | |
+ | | |<--------|---| | | | |
+ | | | | +-------------+ | | |
+ | | | | : | | |
+ | | | | : | | |
+ | | | | : | | |
+ | | | | +-------------+ | | |
+ | | | | | *R5 SPL* | | | |
+ | | | | +-------------+ | | |
+ | | | | | DDR | | | |
+ | | | | | config | | | |
+ | | | | +-------------+ | | |
+ | | | | | Load | | | |
+ | | | | | tispl.bin | | | |
+ | | | | +-------------+ | | |
+ | | | | | Load R5 | | | |
+ | | | | | firmware | | | |
+ | | | | +-------------+ | | |
+ | | |<--------|---| Start A72 | | | |
+ | | | | | and jump to | | | |
+ | | | | | DM fw image | | | |
+ | | | | +-------------+ | | |
+ | | | | | +-----------+ | |
+ | | |---------|-----------------------|---->| Reset rls | | |
+ | | | | | +-----------+ | |
+ | | TIFS | | | : | |
+ | |Services | | | +-----------+ | |
+ | | |<--------|-----------------------|---->|*ATF/OPTEE*| | |
+ | | | | | +-----------+ | |
+ | | | | | : | |
+ | | | | | +-----------+ | |
+ | | |<--------|-----------------------|---->| *A72 SPL* | | |
+ | | | | | +-----------+ | |
+ | | | | | | Load | | |
+ | | | | | | u-boot.img| | |
+ | | | | | +-----------+ | |
+ | | | | | : | |
+ | | | | | +-----------+ | |
+ | | |<--------|-----------------------|---->| *U-Boot* | | |
+ | | | | | +-----------+ | |
+ | | | | | | prompt | | |
+ | | | | | +-----------+ | |
+ | | | | | | Load R5 | | |
+ | | | | | | Firmware | | |
+ | | | | | +-----------+ | |
+ | | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
+ | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
+ | | | | | | Load C7 | | +-----------+ |
+ | | | | | | Firmware | | |
+ | | | | | +-----------+ | |
+ | | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
+ | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
+ | | | | | | +-----------+ |
+ | | | | | | |
+ | +---------+ | | | |
+ | | | | |
+ +------------------------------------------------------------------------+-----------------------+
+
+- Here DMSC acts as master and provides all the critical services. R5/A72
+ requests DMSC to get these services done as shown in the above diagram.
+
+Sources:
+--------
+1. SYSFW:
+ Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
+ Branch: master
+
+2. ATF:
+ Tree: https://github.com/ARM-software/arm-trusted-firmware.git
+ Branch: master
+
+3. OPTEE:
+ Tree: https://github.com/OP-TEE/optee_os.git
+ Branch: master
+
+4. DM Firmware:
+ Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
+ Branch: ti-linux-firmware
+
+5. U-Boot:
+ Tree: https://source.denx.de/u-boot/u-boot
+ Branch: master
+
+Build procedure:
+----------------
+1. SYSFW:
+
+.. code-block:: bash
+
+ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=j7200 SBL=u-boot-spl.bin SYSFW_PATH=<path to sysfw>/ti-fs-firmware-j7200-gp.bin
+ u-boot-spl.bin is generated at step 4.
+
+2. ATF:
+
+.. code-block:: bash
+
+ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
+
+3. OPTEE:
+
+.. code-block:: bash
+
+ make PLATFORM=k3-j7200 CFG_ARM64_core=y
+
+4. U-Boot:
+
+* 4.1 R5:
+
+.. code-block:: bash
+
+ make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5
+ make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5
+
+* 4.2 A72:
+
+.. code-block:: bash
+
+ make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72
+ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<ATF dir>/build/k3/generic/release/bl31.bin TEE=<OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<DM firmware>/ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72
+
+Target Images
+--------------
+Copy the below images to an SD card and boot:
+ - tiboot3.bin from step 1
+ - tispl.bin, u-boot.img from 4.2
+
+Image formats:
+--------------
+
+- tiboot3.bin:
+
+.. code-block:: console
+
+ +-----------------------+
+ | X.509 |
+ | Certificate |
+ | +-------------------+ |
+ | | | |
+ | | R5 | |
+ | | u-boot-spl.bin | |
+ | | | |
+ | +-------------------+ |
+ | | | |
+ | | FIT header | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | DTB 1...N | | |
+ | | +---------------+ | |
+ | +-------------------+ |
+ | | | |
+ | | FIT HEADER | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | sysfw.bin | | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | board config | | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | PM config | | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | RM config | | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | Secure config | | |
+ | | +---------------+ | |
+ | +-------------------+ |
+ +-----------------------+
+
+- tispl.bin
+
+.. code-block:: console
+
+ +-----------------------+
+ | |
+ | FIT HEADER |
+ | +-------------------+ |
+ | | | |
+ | | A72 ATF | |
+ | +-------------------+ |
+ | | | |
+ | | A72 OPTEE | |
+ | +-------------------+ |
+ | | | |
+ | | R5 DM FW | |
+ | +-------------------+ |
+ | | | |
+ | | A72 SPL | |
+ | +-------------------+ |
+ | | | |
+ | | SPL DTB 1...N | |
+ | +-------------------+ |
+ +-----------------------+
+
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on J7200 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section.
+
+
+*Boot Modes*
+
+============ ============= =============
+Switch Label SW9: 12345678 SW8: 12345678
+============ ============= =============
+SD 00000000 10000010
+EMMC 01000000 10000000
+OSPI 01000000 00000110
+UART 01110000 00000000
+USB DFU 00100000 10000000
+============ ============= =============
+
+For SW8 and SW9, the switch state in the "ON" position = 1.
+
+eMMC:
+-----
+ROM supports booting from eMMC raw read or UDA FS mode.
+
+Below is memory layout in case of booting from
+boot 0/1 partition in raw mode.
+
+Current allocated size for tiboot3 size is 1MB, tispl is 2MB.
+
+Size of u-boot.img is taken 4MB for refernece,
+But this is subject to change depending upon atf, optee size
+
+.. code-block:: console
+
+ boot0/1 partition (8 MB) user partition
+ 0x0+----------------------------------+ 0x0+------------------------+
+ | tiboot3.bin (1 MB) | | |
+ 0x800+----------------------------------+ | |
+ | tispl.bin (2 MB) | | |
+ 0x1800+----------------------------------+ | |
+ | u-boot.img (4MB) | | |
+ 0x3800+----------------------------------+ | |
+ | | | |
+ 0x3900+ environment | | |
+ | | | |
+ 0x3A00+----------------------------------+ +-------------------------+
+
+In case of UDA FS mode booting, following is layout.
+
+All boot images tiboot3.bin, tispl and u-boot should be written to
+fat formatted UDA FS as file.
+
+.. code-block:: console
+
+ boot0/1 partition (8 MB) user partition
+ 0x0+---------------------------------+ 0x0+-------------------------+
+ | | | tiboot3.bin* |
+ 0x800+----------------------------------+ | |
+ | | | tispl.bin |
+ 0x1800+----------------------------------+ | |
+ | | | u-boot.img |
+ 0x3800+----------------------------------+ | |
+ | | | |
+ 0x3900+ | | environment |
+ | | | |
+ 0x3A00+----------------------------------+ +-------------------------+
+
+
+
+In case of booting from eMMC, write above images into raw or UDA FS.
+and set mmc partconf accordingly.
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index b49a60c..2b2f4bb 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -31,6 +31,7 @@
:maxdepth: 1
j721e_evm
+ j7200_evm
am62x_sk
Boot Flow Overview
diff --git a/doc/build/clang.rst b/doc/build/clang.rst
index 1d35616..cc26550 100644
--- a/doc/build/clang.rst
+++ b/doc/build/clang.rst
@@ -74,3 +74,39 @@
#!/bin/sh
exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd "$@"
+
+
+Known Issues
+------------
+
+When build U-boot for `xenguest_arm64_defconfig` target, it reports linkage
+error:
+
+.. code-block:: bash
+
+ aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `do_hypervisor_callback':
+ /home/leoy/Dev2/u-boot/drivers/xen/hypervisor.c:188: undefined reference to `__aarch64_swp8_acq_rel'
+ aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit':
+ /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel'
+ aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit':
+ /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel'
+ aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit':
+ /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel'
+ aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit':
+ /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel'
+ aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_clear_bit':
+ /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel'
+ aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_set_bit':
+ /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel'
+ aarch64-linux-gnu-ld.bfd: drivers/xen/gnttab.o: in function `gnttab_end_access':
+ /home/leoy/Dev2/u-boot/drivers/xen/gnttab.c:109: undefined reference to `__aarch64_cas2_acq_rel'
+ Segmentation fault
+
+To fix the failure, we need to append option `-mno-outline-atomics` in Clang
+command to not generate local calls to out-of-line atomic operations:
+
+.. code-block:: bash
+
+ make HOSTCC=clang xenguest_arm64_defconfig
+ make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \
+ CC="clang -target aarch64-linux-gnueabi -mno-outline-atomics" -j8
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index c00cfaa..2c82783 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -70,7 +70,7 @@
* U-Boot v2023.07-rc3 was released on Mon 29 May 2023.
-.. * U-Boot v2023.07-rc4 was released on Mon 05 June 2023.
+* U-Boot v2023.07-rc4 was released on Mon 12 June 2023.
.. * U-Boot v2023.07-rc5 was released on Mon 19 June 2023.
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index ef0987c..6626cee 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -318,6 +318,33 @@
--guid <image GUID> \
<capsule_file_name>
+The UEFI specification does not define the firmware versioning mechanism.
+EDK II reference implementation inserts the FMP Payload Header right before
+the payload. It coutains the fw_version and lowest supported version,
+EDK II reference implementation uses these information to implement the
+firmware versioning and anti-rollback protection, the firmware version and
+lowest supported version is stored into EFI non-volatile variable.
+
+In U-Boot, the firmware versioning is implemented utilizing
+the FMP Payload Header same as EDK II reference implementation,
+reads the FMP Payload Header and stores the firmware version into
+"FmpStateXXXX" EFI non-volatile variable. XXXX indicates the image index,
+since FMP protocol handles multiple image indexes.
+
+To add the fw_version into the FMP Payload Header,
+add --fw-version option in mkeficapsule tool.
+
+.. code-block:: console
+
+ $ mkeficapsule \
+ --index <index> --instance 0 \
+ --guid <image GUID> \
+ --fw-version 5 \
+ <capsule_file_name>
+
+If the --fw-version option is not set, FMP Payload Header is not inserted
+and fw_version is set as 0.
+
Performing the update
*********************
@@ -510,6 +537,45 @@
};
};
+Anti-rollback Protection
+************************
+
+Anti-rollback prevents unintentional installation of outdated firmware.
+To enable anti-rollback, you must add the lowest-supported-version property
+to dtb and specify --fw-version when creating a capsule file with the
+mkeficapsule tool.
+When executing capsule update, U-Boot checks if fw_version is greater than
+or equal to lowest-supported-version. If fw_version is less than
+lowest-supported-version, the update will fail.
+For example, if lowest-supported-version is set to 7 and you run capsule
+update using a capsule file with --fw-version of 5, the update will fail.
+When the --fw-version in the capsule file is updated, lowest-supported-version
+in the dtb might be updated accordingly.
+
+To insert the lowest supported version into a dtb
+
+.. code-block:: console
+
+ $ dtc -@ -I dts -O dtb -o version.dtbo version.dts
+ $ fdtoverlay -i orig.dtb -o new.dtb -v version.dtbo
+
+where version.dts looks like::
+
+ /dts-v1/;
+ /plugin/;
+ &{/} {
+ firmware-version {
+ image1 {
+ image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+ image-index = <1>;
+ lowest-supported-version = <3>;
+ };
+ };
+ };
+
+The properties of image-type-id and image-index must match the value
+defined in the efi_fw_image array as image_type_id and image_index.
+
Executing the boot manager
~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/device-tree-bindings/firmware/firmware-version.txt b/doc/device-tree-bindings/firmware/firmware-version.txt
new file mode 100644
index 0000000..ee90ce3
--- /dev/null
+++ b/doc/device-tree-bindings/firmware/firmware-version.txt
@@ -0,0 +1,22 @@
+firmware-version bindings
+-------------------------------
+
+Required properties:
+- image-type-id : guid for image blob type
+- image-index : image index
+- lowest-supported-version : lowest supported version
+
+Example:
+
+ firmware-version {
+ image1 {
+ image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+ image-index = <1>;
+ lowest-supported-version = <3>;
+ };
+ image2 {
+ image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0";
+ image-index = <2>;
+ lowest-supported-version = <7>;
+ };
+ };
diff --git a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
index 4f5404f..6a22aee 100644
--- a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
+++ b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
@@ -1,13 +1,13 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-sf.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
+$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-mtd.yaml#
+$schema: http://devicetree.org/meta-schemas/base.yaml#
title: FWU metadata on MTD device without GPT
maintainers:
- - Masami Hiramatsu <masami.hiramatsu@linaro.org>
+ - Jassi Brar <jaswinder.singh@linaro.org>
properties:
compatible:
@@ -15,24 +15,101 @@
- const: u-boot,fwu-mdata-mtd
fwu-mdata-store:
- maxItems: 1
- description: Phandle of the MTD device which contains the FWU medatata.
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle of the MTD device which contains the FWU MetaData and Banks.
- mdata-offsets:
+ mdata-parts:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
minItems: 2
- description: Offsets of the primary and secondary FWU metadata in the NOR flash.
+ maxItems: 2
+ description: labels of the primary and secondary FWU metadata partitions in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node.
+
+ patternProperties:
+ "fwu-bank[0-9]":
+ type: object
+ description: List of FWU mtd-backed banks. Typically two banks.
+
+ properties:
+ id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Index of the bank.
+
+ label:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ minItems: 1
+ maxItems: 1
+ description: label of the partition, in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node, that holds this bank.
+
+ patternProperties:
+ "fwu-image[0-9]":
+ type: object
+ description: List of images in the FWU mtd-backed bank.
+
+ properties:
+ id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Index of the bank.
+
+ offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset, from start of the bank, where the image is located.
+
+ size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Size reserved for the image.
+
+ uuid:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ minItems: 1
+ maxItems: 1
+ description: UUID of the image.
+
+ required:
+ - id
+ - offset
+ - size
+ - uuid
+ additionalProperties: false
+
+ required:
+ - id
+ - label
+ - fwu-images
+ additionalProperties: false
required:
- compatible
- fwu-mdata-store
- - mdata-offsets
-
+ - mdata-parts
+ - fwu-banks
additionalProperties: false
examples:
- |
- fwu-mdata {
- compatible = "u-boot,fwu-mdata-mtd";
- fwu-mdata-store = <&spi-flash>;
- mdata-offsets = <0x500000 0x530000>;
- };
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-mtd";
+ fwu-mdata-store = <&flash0>;
+ mdata-parts = "MDATA-Pri", "MDATA-Sec";
+
+ fwu-bank0 {
+ id = <0>;
+ label = "FIP-Bank0";
+ fwu-image0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x400000>;
+ uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
+ };
+ };
+ fwu-bank1 {
+ id = <1>;
+ label = "FIP-Bank1";
+ fwu-image0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x400000>;
+ uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0";
+ };
+ };
+ };
+...
diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1
index 1ca245a..c4c2057 100644
--- a/doc/mkeficapsule.1
+++ b/doc/mkeficapsule.1
@@ -62,6 +62,16 @@
Specify a hardware instance
.PP
+FMP Payload Header is inserted right before the payload if
+.BR --fw-version
+is specified
+
+
+.TP
+.BI "-v\fR,\fB --fw-version " firmware-version
+Specify a firmware version, 0 if omitted
+
+.PP
For generation of firmware accept empty capsule
.BR --guid
is mandatory
diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1
new file mode 100644
index 0000000..7dd718b
--- /dev/null
+++ b/doc/mkfwumdata.1
@@ -0,0 +1,89 @@
+.\" SPDX-License-Identifier: GPL-2.0-or-later
+.\" Copyright (C) 2023 Jassi Brar <jaswinder.singh@linaro.org>
+.TH MKFWUMDATA 1 2023-04-10 U-Boot
+.SH NAME
+mkfwumdata \- create FWU metadata image
+.
+.SH SYNOPSIS
+.SY mkfwumdata
+.OP \-a activeidx
+.OP \-p previousidx
+.OP \-g
+.BI \-i\~ imagecount
+.BI \-b\~ bankcount
+.I UUIDs
+.I outputimage
+.YS
+.SY mkfwumdata
+.B \-h
+.YS
+.
+.SH DESCRIPTION
+.B mkfwumdata
+creates metadata info to be used with FWU.
+.
+.SH OPTIONS
+.TP
+.B \-h
+Print usage information and exit.
+.
+.TP
+.B \-a
+Set
+.IR activeidx
+as the currently active Bank. Default is 0.
+.
+.TP
+.B \-p
+Set
+.IR previousidx
+as the previous active Bank. Default is
+.IR activeidx "-1"
+or
+.IR bankcount "-1,"
+whichever is non-negative.
+.
+.TP
+.B \-g
+Convert the
+.IR UUIDs
+as GUIDs before use.
+.
+.TP
+.B \-i
+Specify there are
+.IR imagecount
+images in each bank.
+.
+.TP
+.B \-b
+Specify there are a total of
+.IR bankcount
+banks.
+.
+.TP
+.IR UUIDs
+Comma-separated list of UUIDs required to create the metadata :-
+location_uuid,image_type_uuid,<images per bank uuid list of all banks>
+.
+.TP
+.IR outputimage
+Specify the name of the metadata image file to be created.
+.
+.SH BUGS
+Please report bugs to the
+.UR https://\:source\:.denx\:.de/\:u-boot/\:u-boot/\:issues
+U-Boot bug tracker
+.UE .
+.SH EXAMPLES
+Create a metadata image with 2 banks and 1 image/bank, BankAct=0, BankPrev=1:
+.PP
+.EX
+.in +4
+$ \c
+.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \\\\\&
+.in +6
+.B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\\\\\&
+.B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\\\\\&
+.B 5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \\\\\&
+.B fwu-mdata.img
diff --git a/drivers/axi/axi-emul-uclass.c b/drivers/axi/axi-emul-uclass.c
index 793336d..e6f3ef0 100644
--- a/drivers/axi/axi-emul-uclass.c
+++ b/drivers/axi/axi-emul-uclass.c
@@ -14,7 +14,7 @@
#include <asm/axi.h>
int axi_sandbox_get_emul(struct udevice *bus, ulong address,
- enum axi_size_t size, struct udevice **emulp)
+ const enum axi_size_t size, struct udevice **emulp)
{
struct udevice *dev;
u32 reg[2];
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 516dda6..b2ee5f1 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -135,6 +135,7 @@
a = s;
do {
part = strsep(&a, ";");
+ part = skip_spaces(part);
ret = dfu_alt_add(dfu, i, d, part);
if (ret)
return ret;
@@ -629,6 +630,7 @@
for (i = 0; i < dfu_alt_num; i++) {
s = strsep(&env, ";");
+ s = skip_spaces(s);
ret = dfu_alt_add(dfu, interface, devstr, s);
if (ret) {
/* We will free "dfu" in dfu_free_entities() */
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index 621146b..4e9d9b7 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -135,7 +135,7 @@
s = env_get("fastboot_bootcmd");
if (s) {
run_command(s, CMD_FLAG_ENV);
- } else {
+ } else if (IS_ENABLED(CONFIG_CMD_BOOTM)) {
static char boot_addr_start[20];
static char *const bootm_args[] = {
"bootm", boot_addr_start, NULL
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index bd7379a..72f572d 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -265,7 +265,7 @@
if (xfer->rx_len) {
ret = ti_sci_get_response(info, xfer, &info->chan_rx);
if (!ti_sci_is_response_ack(xfer->tx_message.buf)) {
- dev_err(info->dev, "Message not acknowledged");
+ dev_err(info->dev, "Message not acknowledged\n");
ret = -ENODEV;
}
}
diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig
index 36c4479..42736a5 100644
--- a/drivers/fwu-mdata/Kconfig
+++ b/drivers/fwu-mdata/Kconfig
@@ -6,6 +6,11 @@
FWU Metadata partitions reside on the same storage device
which contains the other FWU updatable firmware images.
+choice
+ prompt "Storage Layout Scheme"
+ depends on FWU_MDATA
+ default FWU_MDATA_GPT_BLK
+
config FWU_MDATA_GPT_BLK
bool "FWU Metadata access for GPT partitioned Block devices"
select PARTITION_TYPE_GUID
@@ -14,3 +19,13 @@
help
Enable support for accessing FWU Metadata on GPT partitioned
block devices.
+
+config FWU_MDATA_MTD
+ bool "Raw MTD devices"
+ depends on MTD
+ help
+ Enable support for accessing FWU Metadata on non-partitioned
+ (or non-GPT partitioned, e.g. partition nodes in devicetree)
+ MTD devices.
+
+endchoice
diff --git a/drivers/fwu-mdata/Makefile b/drivers/fwu-mdata/Makefile
index 3fee64c..06c4974 100644
--- a/drivers/fwu-mdata/Makefile
+++ b/drivers/fwu-mdata/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_FWU_MDATA) += fwu-mdata-uclass.o
obj-$(CONFIG_FWU_MDATA_GPT_BLK) += gpt_blk.o
+obj-$(CONFIG_FWU_MDATA_MTD) += raw_mtd.o
diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c
index b477e96..0a8edaa 100644
--- a/drivers/fwu-mdata/fwu-mdata-uclass.c
+++ b/drivers/fwu-mdata/fwu-mdata-uclass.c
@@ -14,170 +14,39 @@
#include <linux/errno.h>
#include <linux/types.h>
-#include <u-boot/crc.h>
/**
- * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers
- * @dev: FWU metadata device
- * @mdata_parts: array for storing the metadata partition numbers
- *
- * Get the partition numbers on the storage device on which the
- * FWU metadata is stored. Two partition numbers will be returned.
+ * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata()
*
* Return: 0 if OK, -ve on error
- *
*/
-int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts)
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
{
const struct fwu_mdata_ops *ops = device_get_ops(dev);
- if (!ops->get_mdata_part_num) {
- log_debug("get_mdata_part_num() method not defined\n");
+ if (!ops->read_mdata) {
+ log_debug("read_mdata() method not defined\n");
return -ENOSYS;
}
- return ops->get_mdata_part_num(dev, mdata_parts);
+ return ops->read_mdata(dev, mdata, primary);
}
/**
- * fwu_read_mdata_partition() - Read the FWU metadata from a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number from which FWU metadata is to be read
- *
- * Read the FWU metadata from the specified partition number
+ * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata()
*
* Return: 0 if OK, -ve on error
- *
*/
-int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
- uint part_num)
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
{
const struct fwu_mdata_ops *ops = device_get_ops(dev);
- if (!ops->read_mdata_partition) {
- log_debug("read_mdata_partition() method not defined\n");
+ if (!ops->write_mdata) {
+ log_debug("write_mdata() method not defined\n");
return -ENOSYS;
}
- return ops->read_mdata_partition(dev, mdata, part_num);
-}
-
-/**
- * fwu_write_mdata_partition() - Write the FWU metadata to a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number to which FWU metadata is to be written
- *
- * Write the FWU metadata to the specified partition number
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
- uint part_num)
-{
- const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
- if (!ops->write_mdata_partition) {
- log_debug("write_mdata_partition() method not defined\n");
- return -ENOSYS;
- }
-
- return ops->write_mdata_partition(dev, mdata, part_num);
-}
-
-/**
- * fwu_mdata_check() - Check if the FWU metadata is valid
- * @dev: FWU metadata device
- *
- * Validate both copies of the FWU metadata. If one of the copies
- * has gone bad, restore it from the other copy.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_mdata_check(struct udevice *dev)
-{
- const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
- if (!ops->check_mdata) {
- log_debug("check_mdata() method not defined\n");
- return -ENOSYS;
- }
-
- return ops->check_mdata(dev);
-}
-
-/**
- * fwu_get_mdata() - Get a FWU metadata copy
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Get a valid copy of the FWU metadata.
- *
- * Note: This function is to be called first when modifying any fields
- * in the metadata. The sequence of calls to modify any field in the
- * metadata would be 1) fwu_get_mdata 2) Modify metadata, followed by
- * 3) fwu_update_mdata
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata)
-{
- const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
- if (!ops->get_mdata) {
- log_debug("get_mdata() method not defined\n");
- return -ENOSYS;
- }
-
- return ops->get_mdata(dev, mdata);
-}
-
-/**
- * fwu_update_mdata() - Update the FWU metadata
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Update the FWU metadata structure by writing to the
- * FWU metadata partitions.
- *
- * Note: This function is not to be called directly to update the
- * metadata fields. The sequence of function calls should be
- * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata()
- *
- * The sequence of updating the partitions should be, update the
- * primary metadata partition (first partition encountered), followed
- * by updating the secondary partition. With this update sequence, in
- * the rare scenario that the two metadata partitions are valid but do
- * not match, maybe due to power outage at the time of updating the
- * metadata copies, the secondary partition can be updated from the
- * primary.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata)
-{
- void *buf;
- const struct fwu_mdata_ops *ops = device_get_ops(dev);
-
- if (!ops->update_mdata) {
- log_debug("get_mdata() method not defined\n");
- return -ENOSYS;
- }
-
- /*
- * Calculate the crc32 for the updated FWU metadata
- * and put the updated value in the FWU metadata crc32
- * field
- */
- buf = &mdata->version;
- mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
-
- return ops->update_mdata(dev, mdata);
+ return ops->write_mdata(dev, mdata, primary);
}
UCLASS_DRIVER(fwu_mdata) = {
diff --git a/drivers/fwu-mdata/gpt_blk.c b/drivers/fwu-mdata/gpt_blk.c
index d35ce49..c728491 100644
--- a/drivers/fwu-mdata/gpt_blk.c
+++ b/drivers/fwu-mdata/gpt_blk.c
@@ -24,38 +24,40 @@
MDATA_WRITE,
};
-static int gpt_get_mdata_partitions(struct blk_desc *desc,
- uint mdata_parts[2])
+static uint g_mdata_part[2]; /* = {0, 0} to check against uninit parts */
+
+static int gpt_get_mdata_partitions(struct blk_desc *desc)
{
- int i, ret;
+ int i;
u32 nparts;
efi_guid_t part_type_guid;
struct disk_partition info;
const efi_guid_t fwu_mdata_guid = FWU_MDATA_GUID;
+ /* if primary and secondary partitions already found */
+ if (g_mdata_part[0] && g_mdata_part[1])
+ return 0;
+
nparts = 0;
- for (i = 1; i < MAX_SEARCH_PARTITIONS; i++) {
+ for (i = 1; i < MAX_SEARCH_PARTITIONS && nparts < 2; i++) {
if (part_get_info(desc, i, &info))
continue;
uuid_str_to_bin(info.type_guid, part_type_guid.b,
UUID_STR_FORMAT_GUID);
- if (!guidcmp(&fwu_mdata_guid, &part_type_guid)) {
- if (nparts < 2)
- mdata_parts[nparts] = i;
- ++nparts;
- }
+ if (!guidcmp(&fwu_mdata_guid, &part_type_guid))
+ g_mdata_part[nparts++] = i;
}
if (nparts != 2) {
log_debug("Expect two copies of the FWU metadata instead of %d\n",
nparts);
- ret = -EINVAL;
- } else {
- ret = 0;
+ g_mdata_part[0] = 0;
+ g_mdata_part[1] = 0;
+ return -EINVAL;
}
- return ret;
+ return 0;
}
static int gpt_get_mdata_disk_part(struct blk_desc *desc,
@@ -123,112 +125,6 @@
return 0;
}
-static int fwu_gpt_update_mdata(struct udevice *dev, struct fwu_mdata *mdata)
-{
- int ret;
- struct blk_desc *desc;
- uint mdata_parts[2];
- struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
- desc = dev_get_uclass_plat(priv->blk_dev);
-
- ret = gpt_get_mdata_partitions(desc, mdata_parts);
- if (ret < 0) {
- log_debug("Error getting the FWU metadata partitions\n");
- return -ENOENT;
- }
-
- /* First write the primary partition */
- ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, mdata_parts[0]);
- if (ret < 0) {
- log_debug("Updating primary FWU metadata partition failed\n");
- return ret;
- }
-
- /* And now the replica */
- ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, mdata_parts[1]);
- if (ret < 0) {
- log_debug("Updating secondary FWU metadata partition failed\n");
- return ret;
- }
-
- return 0;
-}
-
-static int gpt_get_mdata(struct blk_desc *desc, struct fwu_mdata *mdata)
-{
- int ret;
- uint mdata_parts[2];
-
- ret = gpt_get_mdata_partitions(desc, mdata_parts);
-
- if (ret < 0) {
- log_debug("Error getting the FWU metadata partitions\n");
- return -ENOENT;
- }
-
- ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, mdata_parts[0]);
- if (ret < 0) {
- log_debug("Failed to read the FWU metadata from the device\n");
- return -EIO;
- }
-
- ret = fwu_verify_mdata(mdata, 1);
- if (!ret)
- return 0;
-
- /*
- * Verification of the primary FWU metadata copy failed.
- * Try to read the replica.
- */
- memset(mdata, '\0', sizeof(struct fwu_mdata));
- ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, mdata_parts[1]);
- if (ret < 0) {
- log_debug("Failed to read the FWU metadata from the device\n");
- return -EIO;
- }
-
- ret = fwu_verify_mdata(mdata, 0);
- if (!ret)
- return 0;
-
- /* Both the FWU metadata copies are corrupted. */
- return -EIO;
-}
-
-static int fwu_gpt_get_mdata(struct udevice *dev, struct fwu_mdata *mdata)
-{
- struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
- return gpt_get_mdata(dev_get_uclass_plat(priv->blk_dev), mdata);
-}
-
-static int fwu_gpt_get_mdata_partitions(struct udevice *dev, uint *mdata_parts)
-{
- struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
- return gpt_get_mdata_partitions(dev_get_uclass_plat(priv->blk_dev),
- mdata_parts);
-}
-
-static int fwu_gpt_read_mdata_partition(struct udevice *dev,
- struct fwu_mdata *mdata, uint part_num)
-{
- struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
- return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev),
- mdata, MDATA_READ, part_num);
-}
-
-static int fwu_gpt_write_mdata_partition(struct udevice *dev,
- struct fwu_mdata *mdata, uint part_num)
-{
- struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
-
- return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev),
- mdata, MDATA_WRITE, part_num);
-}
-
static int fwu_get_mdata_device(struct udevice *dev, struct udevice **mdata_dev)
{
u32 phandle;
@@ -267,12 +163,43 @@
return 0;
}
+static int fwu_gpt_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary)
+{
+ struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
+ int ret;
+
+ ret = gpt_get_mdata_partitions(desc);
+ if (ret < 0) {
+ log_debug("Error getting the FWU metadata partitions\n");
+ return -ENOENT;
+ }
+
+ return gpt_read_write_mdata(desc, mdata, MDATA_READ,
+ primary ? g_mdata_part[0] : g_mdata_part[1]);
+}
+
+static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary)
+{
+ struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
+ int ret;
+
+ ret = gpt_get_mdata_partitions(desc);
+ if (ret < 0) {
+ log_debug("Error getting the FWU metadata partitions\n");
+ return -ENOENT;
+ }
+
+ return gpt_read_write_mdata(desc, mdata, MDATA_WRITE,
+ primary ? g_mdata_part[0] : g_mdata_part[1]);
+}
+
static const struct fwu_mdata_ops fwu_gpt_blk_ops = {
- .get_mdata = fwu_gpt_get_mdata,
- .update_mdata = fwu_gpt_update_mdata,
- .get_mdata_part_num = fwu_gpt_get_mdata_partitions,
- .read_mdata_partition = fwu_gpt_read_mdata_partition,
- .write_mdata_partition = fwu_gpt_write_mdata_partition,
+ .read_mdata = fwu_gpt_read_mdata,
+ .write_mdata = fwu_gpt_write_mdata,
};
static const struct udevice_id fwu_mdata_ids[] = {
diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c
new file mode 100644
index 0000000..17e4517
--- /dev/null
+++ b/drivers/fwu-mdata/raw_mtd.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#define LOG_CATEGORY UCLASS_FWU_MDATA
+
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <memalign.h>
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+/* Internal helper structure to move data around */
+struct fwu_mdata_mtd_priv {
+ struct mtd_info *mtd;
+ char pri_label[50];
+ char sec_label[50];
+ u32 pri_offset;
+ u32 sec_offset;
+};
+
+enum fwu_mtd_op {
+ FWU_MTD_READ,
+ FWU_MTD_WRITE,
+};
+
+extern struct fwu_mtd_image_info fwu_mtd_images[];
+
+static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size)
+{
+ return !do_div(size, mtd->erasesize);
+}
+
+static int mtd_io_data(struct mtd_info *mtd, u32 offs, u32 size, void *data,
+ enum fwu_mtd_op op)
+{
+ struct mtd_oob_ops io_op = {};
+ u64 lock_len;
+ size_t len;
+ void *buf;
+ int ret;
+
+ if (!mtd_is_aligned_with_block_size(mtd, offs)) {
+ log_err("Offset unaligned with a block (0x%x)\n", mtd->erasesize);
+ return -EINVAL;
+ }
+
+ /* This will expand erase size to align with the block size */
+ lock_len = round_up(size, mtd->erasesize);
+
+ ret = mtd_unlock(mtd, offs, lock_len);
+ if (ret && ret != -EOPNOTSUPP)
+ return ret;
+
+ if (op == FWU_MTD_WRITE) {
+ struct erase_info erase_op = {};
+
+ erase_op.mtd = mtd;
+ erase_op.addr = offs;
+ erase_op.len = lock_len;
+ erase_op.scrub = 0;
+
+ ret = mtd_erase(mtd, &erase_op);
+ if (ret)
+ goto lock;
+ }
+
+ /* Also, expand the write size to align with the write size */
+ len = round_up(size, mtd->writesize);
+
+ buf = memalign(ARCH_DMA_MINALIGN, len);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto lock;
+ }
+ memset(buf, 0xff, len);
+
+ io_op.mode = MTD_OPS_AUTO_OOB;
+ io_op.len = len;
+ io_op.datbuf = buf;
+
+ if (op == FWU_MTD_WRITE) {
+ memcpy(buf, data, size);
+ ret = mtd_write_oob(mtd, offs, &io_op);
+ } else {
+ ret = mtd_read_oob(mtd, offs, &io_op);
+ if (!ret)
+ memcpy(data, buf, size);
+ }
+ free(buf);
+
+lock:
+ mtd_lock(mtd, offs, lock_len);
+
+ return ret;
+}
+
+static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+{
+ struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+ struct mtd_info *mtd = mtd_priv->mtd;
+ u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
+
+ return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_READ);
+}
+
+static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+{
+ struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+ struct mtd_info *mtd = mtd_priv->mtd;
+ u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
+
+ return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE);
+}
+
+static int flash_partition_offset(struct udevice *dev, const char *part_name, fdt_addr_t *offset)
+{
+ ofnode node, parts_node;
+ fdt_addr_t size = 0;
+
+ parts_node = ofnode_by_compatible(dev_ofnode(dev), "fixed-partitions");
+ node = ofnode_by_prop_value(parts_node, "label", part_name, strlen(part_name) + 1);
+ if (!ofnode_valid(node)) {
+ log_err("Warning: Failed to find partition by label <%s>\n", part_name);
+ return -ENOENT;
+ }
+
+ *offset = ofnode_get_addr_size_index_notrans(node, 0, &size);
+
+ return (int)size;
+}
+
+static int fwu_mdata_mtd_of_to_plat(struct udevice *dev)
+{
+ struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+ const fdt32_t *phandle_p = NULL;
+ struct udevice *mtd_dev;
+ struct mtd_info *mtd;
+ const char *label;
+ fdt_addr_t offset;
+ int ret, size;
+ u32 phandle;
+ ofnode bank;
+ int off_img;
+
+ /* Find the FWU mdata storage device */
+ phandle_p = ofnode_get_property(dev_ofnode(dev),
+ "fwu-mdata-store", &size);
+ if (!phandle_p) {
+ log_err("FWU meta data store not defined in device-tree\n");
+ return -ENOENT;
+ }
+
+ phandle = fdt32_to_cpu(*phandle_p);
+
+ ret = device_get_global_by_ofnode(ofnode_get_by_phandle(phandle),
+ &mtd_dev);
+ if (ret) {
+ log_err("FWU: failed to get mtd device\n");
+ return ret;
+ }
+
+ mtd_probe_devices();
+
+ mtd_for_each_device(mtd) {
+ if (mtd->dev == mtd_dev) {
+ mtd_priv->mtd = mtd;
+ log_debug("Found the FWU mdata mtd device %s\n", mtd->name);
+ break;
+ }
+ }
+ if (!mtd_priv->mtd) {
+ log_err("Failed to find mtd device by fwu-mdata-store\n");
+ return -ENODEV;
+ }
+
+ /* Get the offset of primary and secondary mdata */
+ ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 0, &label);
+ if (ret)
+ return ret;
+ strncpy(mtd_priv->pri_label, label, 50);
+
+ ret = flash_partition_offset(mtd_dev, mtd_priv->pri_label, &offset);
+ if (ret <= 0)
+ return ret;
+ mtd_priv->pri_offset = offset;
+
+ ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 1, &label);
+ if (ret)
+ return ret;
+ strncpy(mtd_priv->sec_label, label, 50);
+
+ ret = flash_partition_offset(mtd_dev, mtd_priv->sec_label, &offset);
+ if (ret <= 0)
+ return ret;
+ mtd_priv->sec_offset = offset;
+
+ off_img = 0;
+
+ ofnode_for_each_subnode(bank, dev_ofnode(dev)) {
+ int bank_num, bank_offset, bank_size;
+ const char *bank_name;
+ ofnode image;
+
+ ofnode_read_u32(bank, "id", &bank_num);
+ bank_name = ofnode_read_string(bank, "label");
+ bank_size = flash_partition_offset(mtd_dev, bank_name, &offset);
+ if (bank_size <= 0)
+ return bank_size;
+ bank_offset = offset;
+ log_debug("Bank%d: %s [0x%x - 0x%x]\n",
+ bank_num, bank_name, bank_offset, bank_offset + bank_size);
+
+ ofnode_for_each_subnode(image, bank) {
+ int image_num, image_offset, image_size;
+ const char *uuid;
+
+ if (off_img == CONFIG_FWU_NUM_BANKS *
+ CONFIG_FWU_NUM_IMAGES_PER_BANK) {
+ log_err("DT provides more images than configured!\n");
+ break;
+ }
+
+ uuid = ofnode_read_string(image, "uuid");
+ ofnode_read_u32(image, "id", &image_num);
+ ofnode_read_u32(image, "offset", &image_offset);
+ ofnode_read_u32(image, "size", &image_size);
+
+ fwu_mtd_images[off_img].start = bank_offset + image_offset;
+ fwu_mtd_images[off_img].size = image_size;
+ fwu_mtd_images[off_img].bank_num = bank_num;
+ fwu_mtd_images[off_img].image_num = image_num;
+ strcpy(fwu_mtd_images[off_img].uuidbuf, uuid);
+ log_debug("\tImage%d: %s @0x%x\n\n",
+ image_num, uuid, bank_offset + image_offset);
+ off_img++;
+ }
+ }
+
+ return 0;
+}
+
+static int fwu_mdata_mtd_probe(struct udevice *dev)
+{
+ /* Ensure the metadata can be read. */
+ return fwu_get_mdata(NULL);
+}
+
+static struct fwu_mdata_ops fwu_mtd_ops = {
+ .read_mdata = fwu_mtd_read_mdata,
+ .write_mdata = fwu_mtd_write_mdata,
+};
+
+static const struct udevice_id fwu_mdata_ids[] = {
+ { .compatible = "u-boot,fwu-mdata-mtd" },
+ { }
+};
+
+U_BOOT_DRIVER(fwu_mdata_mtd) = {
+ .name = "fwu-mdata-mtd",
+ .id = UCLASS_FWU_MDATA,
+ .of_match = fwu_mdata_ids,
+ .ops = &fwu_mtd_ops,
+ .probe = fwu_mdata_mtd_probe,
+ .of_to_plat = fwu_mdata_mtd_of_to_plat,
+ .priv_auto = sizeof(struct fwu_mdata_mtd_priv),
+};
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 9ffb4a5..d6cfbd2 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -130,20 +130,9 @@
return GPIOF_INPUT;
}
-static int rcar_gpio_request(struct udevice *dev, unsigned offset,
- const char *label)
-{
- return pinctrl_gpio_request(dev, offset, label);
-}
-
-static int rcar_gpio_free(struct udevice *dev, unsigned offset)
-{
- return pinctrl_gpio_free(dev, offset);
-}
-
static const struct dm_gpio_ops rcar_gpio_ops = {
- .request = rcar_gpio_request,
- .rfree = rcar_gpio_free,
+ .request = pinctrl_gpio_request,
+ .rfree = pinctrl_gpio_free,
.direction_input = rcar_gpio_direction_input,
.direction_output = rcar_gpio_direction_output,
.get_value = rcar_gpio_get_value,
diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c
index 8afd57f..98e5dc7 100644
--- a/drivers/gpio/npcm_gpio.c
+++ b/drivers/gpio/npcm_gpio.c
@@ -37,14 +37,14 @@
{
struct npcm_gpio_priv *priv = dev_get_priv(dev);
- clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
- writel(BIT(offset), priv->base + GPIO_OES);
-
if (value)
setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
else
clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
+ clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
+ writel(BIT(offset), priv->base + GPIO_OES);
+
return 0;
}
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 05b14d2..5e81698 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -744,7 +744,6 @@
config SYS_I2C_BUS_MAX
int "Max I2C busses"
depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
- default 2 if TI816X
default 3 if OMAP34XX || AM33XX || AM43XX
default 4 if ARCH_SOCFPGA || OMAP44XX
default 5 if OMAP54XX
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1af6af8..72c1076 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2262,7 +2262,7 @@
return 0;
if (!mmc->ext_csd)
- memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
+ memset(ext_csd_bkup, 0, MMC_MAX_BLOCK_LEN);
err = mmc_send_ext_csd(mmc, ext_csd);
if (err)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a2..7d482cb 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -695,6 +695,7 @@
config SH_ETHER
bool "Renesas SH Ethernet MAC"
select PHYLIB
+ select PHY_ETHERNET_ID
help
This driver supports the Ethernet for Renesas SH and ARM SoCs.
@@ -764,6 +765,7 @@
bool "Renesas Ethernet AVB MAC"
depends on RCAR_64
select PHYLIB
+ select PHY_ETHERNET_ID
help
This driver implements support for the Ethernet AVB block in
Renesas M3 and H3 SoCs.
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
index 912d28f..e234093 100644
--- a/drivers/net/altera_tse.c
+++ b/drivers/net/altera_tse.c
@@ -430,17 +430,11 @@
static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
{
struct phy_device *phydev;
- unsigned int mask = 0xffffffff;
- if (priv->phyaddr)
- mask = 1 << priv->phyaddr;
-
- phydev = phy_find_by_mask(priv->bus, mask);
+ phydev = phy_connect(priv->bus, -1, dev, priv->interface);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev, priv->interface);
-
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
index 27b7744..9d1e8d3 100644
--- a/drivers/net/eth-phy-uclass.c
+++ b/drivers/net/eth-phy-uclass.c
@@ -144,10 +144,18 @@
uc_priv->reset_assert_delay = dev_read_u32_default(dev, "reset-assert-us", 0);
uc_priv->reset_deassert_delay = dev_read_u32_default(dev, "reset-deassert-us", 0);
+ /* These are used by some DTs, try these as a fallback. */
+ if (!uc_priv->reset_assert_delay && !uc_priv->reset_deassert_delay) {
+ uc_priv->reset_assert_delay =
+ dev_read_u32_default(dev, "reset-delay-us", 0);
+ uc_priv->reset_deassert_delay =
+ dev_read_u32_default(dev, "reset-post-delay-us", 0);
+ }
+
return 0;
}
-void eth_phy_reset(struct udevice *dev, int value)
+static void eth_phy_reset(struct udevice *dev, int value)
{
struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev);
u32 delay;
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 29067e9..13fad81 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -608,18 +608,16 @@
static int ethoc_phy_init(struct ethoc *priv, void *dev)
{
struct phy_device *phydev;
- int mask = 0xffffffff;
+ int mask = -1;
#ifdef CONFIG_PHY_ADDR
- mask = 1 << CONFIG_PHY_ADDR;
+ mask = CONFIG_PHY_ADDR;
#endif
- phydev = phy_find_by_mask(priv->bus, mask);
+ phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev, PHY_INTERFACE_MODE_MII);
-
phydev->supported &= PHY_BASIC_FEATURES;
phydev->advertising = phydev->supported;
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
index ad7b5b8..ecf8c28 100644
--- a/drivers/net/pch_gbe.c
+++ b/drivers/net/pch_gbe.c
@@ -414,16 +414,13 @@
struct pch_gbe_priv *priv = dev_get_priv(dev);
struct eth_pdata *plat = dev_get_plat(dev);
struct phy_device *phydev;
- int mask = 0xffffffff;
- phydev = phy_find_by_mask(priv->bus, mask);
+ phydev = phy_connect(priv->bus, -1, dev, plat->phy_interface);
if (!phydev) {
printf("pch_gbe: cannot find the phy\n");
return -1;
}
- phy_connect_dev(phydev, dev, plat->phy_interface);
-
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c
index a715e83..877a51c 100644
--- a/drivers/net/phy/ethernet_id.c
+++ b/drivers/net/phy/ethernet_id.c
@@ -7,6 +7,8 @@
#include <common.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <phy.h>
#include <linux/delay.h>
#include <asm/gpio.h>
@@ -17,6 +19,8 @@
struct phy_device *phydev;
struct ofnode_phandle_args phandle_args;
struct gpio_desc gpio;
+ const char *node_name;
+ struct udevice *pdev;
ofnode node;
u32 id, assert, deassert;
u16 vendor, device;
@@ -72,5 +76,18 @@
if (phydev)
phydev->node = node;
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY) && ofnode_valid(node)) {
+ node_name = ofnode_get_name(node);
+ ret = device_bind_driver_to_node(dev, "eth_phy_generic_drv",
+ node_name, node,
+ &pdev);
+ if (ret)
+ return NULL;
+
+ ret = device_probe(pdev);
+ if (ret)
+ return NULL;
+ }
+
return phydev;
}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 0eeb0cb..ae21acb 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -812,8 +812,8 @@
return get_phy_device_by_mask(bus, phy_mask);
}
-void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
- phy_interface_t interface)
+static void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
+ phy_interface_t interface)
{
/* Soft Reset the PHY */
phy_reset(phydev);
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index c74c8a8..0bcd6cf 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -131,7 +131,6 @@
struct mii_dev *bus;
void __iomem *iobase;
struct clk_bulk clks;
- struct gpio_desc reset_gpio;
};
static inline void ravb_flush_dcache(u32 addr, u32 len)
@@ -312,13 +311,6 @@
struct phy_device *phydev;
int reg;
- if (dm_gpio_is_valid(ð->reset_gpio)) {
- dm_gpio_set_value(ð->reset_gpio, 1);
- mdelay(20);
- dm_gpio_set_value(ð->reset_gpio, 0);
- mdelay(1);
- }
-
phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
if (!phydev)
return -ENODEV;
@@ -503,7 +495,6 @@
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct ravb_priv *eth = dev_get_priv(dev);
- struct ofnode_phandle_args phandle_args;
struct mii_dev *mdiodev;
void __iomem *iobase;
int ret;
@@ -515,17 +506,6 @@
if (ret < 0)
goto err_mdio_alloc;
- ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
- if (!ret) {
- gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
- ð->reset_gpio, GPIOD_IS_OUT);
- }
-
- if (!dm_gpio_is_valid(ð->reset_gpio)) {
- gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
- GPIOD_IS_OUT);
- }
-
mdiodev = mdio_alloc();
if (!mdiodev) {
ret = -ENOMEM;
@@ -576,8 +556,6 @@
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
- if (dm_gpio_is_valid(ð->reset_gpio))
- dm_gpio_free(dev, ð->reset_gpio);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8f162ca..7b1f59d 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -129,11 +129,11 @@
/* Check if the rx descriptor is ready */
invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
if (port_info->rx_desc_cur->rd0 & RD_RACT)
- return -EINVAL;
+ return -EAGAIN;
/* Check for errors */
if (port_info->rx_desc_cur->rd0 & RD_RFE)
- return -EINVAL;
+ return 0;
return port_info->rx_desc_cur->rd1 & 0xffff;
}
@@ -142,6 +142,8 @@
{
struct sh_eth_info *port_info = ð->port_info[eth->port];
+ invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE);
+
/* Make current descriptor available again */
if (port_info->rx_desc_cur->rd0 & RD_RDLE)
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
@@ -210,8 +212,6 @@
goto err;
}
- flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
-
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base =
(struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
@@ -229,6 +229,7 @@
cur_tx_desc--;
cur_tx_desc->td0 |= TD_TDLE;
+ flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
/*
* Point the controller to the tx descriptor list. Must use physical
* addresses
@@ -264,8 +265,6 @@
goto err;
}
- flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
-
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base =
(struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
@@ -299,6 +298,9 @@
cur_rx_desc--;
cur_rx_desc->rd0 |= RD_RDLE;
+ invalidate_cache(port_info->rx_buf_alloc, NUM_RX_DESC * MAX_BUF_SIZE);
+ flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
+
/* Point the controller to the rx descriptor list */
sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
@@ -530,7 +532,6 @@
struct mii_dev *bus;
phys_addr_t iobase;
struct clk clk;
- struct gpio_desc reset_gpio;
};
static int sh_ether_send(struct udevice *dev, void *packet, int len)
@@ -555,15 +556,13 @@
*packetp = packet;
return len;
- } else {
- len = 0;
-
- /* Restart the receiver if disabled */
- if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
- sh_eth_write(port_info, EDRRR_R, EDRRR);
-
- return -EAGAIN;
}
+
+ /* Restart the receiver if disabled */
+ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
+
+ return len;
}
static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
@@ -601,14 +600,11 @@
int ret = 0;
struct sh_eth_info *port_info = ð->port_info[eth->port];
struct phy_device *phydev;
- int mask = 0xffffffff;
- phydev = phy_find_by_mask(priv->bus, mask);
+ phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev, pdata->phy_interface);
-
port_info->phydev = phydev;
phy_config(phydev);
@@ -653,7 +649,6 @@
struct eth_pdata *pdata = dev_get_plat(udev);
struct sh_ether_priv *priv = dev_get_priv(udev);
struct sh_eth_dev *eth = &priv->shdev;
- struct ofnode_phandle_args phandle_args;
struct mii_dev *mdiodev;
int ret;
@@ -664,18 +659,6 @@
if (ret < 0)
return ret;
#endif
-
- ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
- if (!ret) {
- gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
- &priv->reset_gpio, GPIOD_IS_OUT);
- }
-
- if (!dm_gpio_is_valid(&priv->reset_gpio)) {
- gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
- GPIOD_IS_OUT);
- }
-
mdiodev = mdio_alloc();
if (!mdiodev) {
ret = -ENOMEM;
@@ -738,9 +721,6 @@
mdio_unregister(priv->bus);
mdio_free(priv->bus);
- if (dm_gpio_is_valid(&priv->reset_gpio))
- dm_gpio_free(udev, &priv->reset_gpio);
-
return 0;
}
diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c
index 014b070..f5a0d80 100644
--- a/drivers/net/sni_ave.c
+++ b/drivers/net/sni_ave.c
@@ -391,14 +391,12 @@
static int ave_phy_init(struct ave_private *priv, void *dev)
{
struct phy_device *phydev;
- int mask = GENMASK(31, 0), ret;
+ int ret;
- phydev = phy_find_by_mask(priv->bus, mask);
+ phydev = phy_connect(priv->bus, -1, dev, priv->phy_mode);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev, priv->phy_mode);
-
phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index ad9e1ab..4c90d4b 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -248,10 +248,10 @@
static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
{
- int ret, mask = 0xffffffff;
+ int ret, mask = -1;
#ifdef CONFIG_PHY_ADDR
- mask = 1 << CONFIG_PHY_ADDR;
+ mask = CONFIG_PHY_ADDR;
#endif
priv->bus = mdio_alloc();
@@ -269,11 +269,10 @@
if (ret)
return ret;
- priv->phydev = phy_find_by_mask(priv->bus, mask);
+ priv->phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII);
if (!priv->phydev)
return -ENODEV;
- phy_connect_dev(priv->phydev, dev, PHY_INTERFACE_MODE_MII);
phy_config(priv->phydev);
return 0;
diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c
index 29d2fc9..034877a 100644
--- a/drivers/net/ti/davinci_emac.c
+++ b/drivers/net/ti/davinci_emac.c
@@ -833,9 +833,9 @@
#endif
}
-#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
- !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
+ !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
for (i = 0; i < num_phy; i++) {
if (phy[i].is_phy_connected(i))
phy[i].auto_negotiate(i);
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 2339717..34314d0 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -256,6 +256,7 @@
J721E_WIZ_10G,
AM64_WIZ_10G,
J784S4_WIZ_10G,
+ J721S2_WIZ_10G,
};
struct wiz_data {
@@ -307,6 +308,15 @@
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
+static struct wiz_data j721s2_10g_data = {
+ .type = J721S2_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
+ .refclk_dig_sel = &refclk_dig_sel_10g,
+ .clk_mux_sel = clk_mux_sel_10g,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
@@ -1037,8 +1047,14 @@
ofnode node;
int i, rc;
- if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G)
+ switch (type) {
+ case AM64_WIZ_10G:
+ case J784S4_WIZ_10G:
+ case J721S2_WIZ_10G:
return j721e_wiz_bind_clocks(wiz);
+ default:
+ break;
+ };
div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
if (!div_clk_drv) {
@@ -1282,6 +1298,9 @@
{
.compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
},
+ {
+ .compatible = "ti,j721s2-wiz-10g", .data = (ulong)&j721s2_10g_data,
+ },
{}
};
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h b/drivers/pinctrl/exynos/pinctrl-exynos.h
index a7788b7..cbc5174 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.h
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -6,7 +6,7 @@
*/
#ifndef __PINCTRL_EXYNOS_H_
-#define __PINCTRL_EXYNOS__H_
+#define __PINCTRL_EXYNOS_H_
#define PIN_CON 0x00 /* Offset of pin function register */
#define PIN_DAT 0x04 /* Offset of pin data register */
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 1ad8bfb..9251382 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1552,12 +1552,12 @@
setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
case PIN_CONFIG_OUTPUT:
dev_dbg(dev, "set pin %d output %d\n", pin, arg);
- clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
- setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
if (arg)
setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
else
clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
+ clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
+ setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
dev_dbg(dev, "set pin %d push pull\n", pin);
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index 0ec47e9..f18be08 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -900,12 +900,12 @@
setbits_le32(base + GPIO_OES, BIT(gpio));
case PIN_CONFIG_OUTPUT:
dev_dbg(dev, "set pin %d output %d\n", pin, arg);
- clrbits_le32(base + GPIO_IEM, BIT(gpio));
- setbits_le32(base + GPIO_OES, BIT(gpio));
if (arg)
setbits_le32(base + GPIO_DOUT, BIT(gpio));
else
clrbits_le32(base + GPIO_DOUT, BIT(gpio));
+ clrbits_le32(base + GPIO_IEM, BIT(gpio));
+ setbits_le32(base + GPIO_OES, BIT(gpio));
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
dev_dbg(dev, "set pin %d push pull\n", pin);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4f435fd..453a598 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -382,7 +382,7 @@
config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
depends on RCAR_64 || RZA1
- imply SPI_FLASH_BAR
+ imply SPI_FLASH_SFDP_SUPPORT
help
Enable the Renesas RPC SPI driver, used to access SPI NOR flash
on Renesas RCar Gen3 SoCs. This uses driver model and requires a
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index cb2b8fb..51c37d7 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -17,6 +17,7 @@
#include <linux/bug.h>
#include <linux/errno.h>
#include <spi.h>
+#include <spi-mem.h>
#include <wait_bit.h>
#define RPC_CMNCR 0x0000 /* R/W */
@@ -140,6 +141,7 @@
#define PRC_PHYCNT_EXDS BIT(21)
#define RPC_PHYCNT_OCT BIT(20)
#define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
+#define RPC_PHYCNT_STRTIM2(v) ((((v) & 0x7) << 15) | (((v) & 0x8) << 24))
#define RPC_PHYCNT_WBUF2 BIT(4)
#define RPC_PHYCNT_WBUF BIT(2)
#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
@@ -167,10 +169,6 @@
fdt_addr_t regs;
fdt_addr_t extr;
struct clk clk;
-
- u8 cmdcopy[8];
- u32 cmdlen;
- bool cmdstarted;
};
static int rpc_spi_wait_sslf(struct udevice *dev)
@@ -202,18 +200,35 @@
}
+static u32 rpc_spi_get_strobe_delay(void)
+{
+#ifndef CONFIG_RZA1
+ u32 cpu_type = rmobile_get_cpu_type();
+
+ /*
+ * NOTE: RPC_PHYCNT_STRTIM value:
+ * 0: On H3 ES1.x (not supported in mainline U-Boot)
+ * 6: On M3 ES1.x
+ * 7: On other R-Car Gen3
+ * 15: On R-Car Gen4
+ */
+ if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1)
+ return RPC_PHYCNT_STRTIM(6);
+ else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
+ cpu_type == RMOBILE_CPU_TYPE_R8A779G0)
+ return RPC_PHYCNT_STRTIM2(15);
+ else
+#endif
+ return RPC_PHYCNT_STRTIM(7);
+}
+
static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
{
struct udevice *bus = dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
- /*
- * NOTE: The 0x260 are undocumented bits, but they must be set.
- * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
- * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
- * RPC_PHYCNT_STRTIM shall be 6.
- */
- writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
+ /* NOTE: The 0x260 are undocumented bits, but they must be set. */
+ writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
priv->regs + RPC_PHYCNT);
writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
@@ -233,79 +248,91 @@
struct rpc_spi_priv *priv = dev_get_priv(bus);
/* NOTE: The 0x260 are undocumented bits, but they must be set. */
- writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
+ writel(rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT);
rpc_spi_flush_read_cache(dev);
return 0;
}
-static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int rpc_spi_mem_exec_op(struct spi_slave *spi,
+ const struct spi_mem_op *op)
{
- struct udevice *bus = dev->parent;
+ struct udevice *bus = spi->dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
- u32 wlen = dout ? (bitlen / 8) : 0;
- u32 rlen = din ? (bitlen / 8) : 0;
- u32 wloop = DIV_ROUND_UP(wlen, 4);
- u32 smenr, smcr, offset;
+ const void *dout = op->data.buf.out ? op->data.buf.out : NULL;
+ void *din = op->data.buf.in ? op->data.buf.in : NULL;
int ret = 0;
-
- if (!priv->cmdstarted) {
- if (!wlen || rlen)
- BUG();
-
- memcpy(priv->cmdcopy, dout, wlen);
- priv->cmdlen = wlen;
-
- /* Command transfer start */
- priv->cmdstarted = true;
- if (!(flags & SPI_XFER_END))
- return 0;
- }
-
- offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
- (priv->cmdcopy[3] << 0);
+ u32 offset = 0;
+ u32 smenr, smcr;
smenr = 0;
+ offset = op->addr.val;
- if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
- if (wlen && flags == SPI_XFER_END)
- smenr = RPC_SMENR_SPIDE(0xf);
+ switch (op->data.dir) {
+ case SPI_MEM_DATA_IN:
+ rpc_spi_claim_bus(spi->dev, false);
- rpc_spi_claim_bus(dev, true);
+ writel(0, priv->regs + RPC_DRCMR);
+ writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
+ smenr |= RPC_DRENR_CDE;
+
+ writel(0, priv->regs + RPC_DREAR);
+ if (op->addr.nbytes == 4) {
+ writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
+ priv->regs + RPC_DREAR);
+ smenr |= RPC_DRENR_ADE(0xF);
+ } else if (op->addr.nbytes == 3) {
+ smenr |= RPC_DRENR_ADE(0x7);
+ } else {
+ smenr |= RPC_DRENR_ADE(0);
+ }
+
+ writel(0, priv->regs + RPC_DRDMCR);
+ if (op->dummy.nbytes) {
+ writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
+ smenr |= RPC_DRENR_DME;
+ }
+
+ writel(0, priv->regs + RPC_DROPR);
+ writel(smenr, priv->regs + RPC_DRENR);
+
+ memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
+
+ rpc_spi_release_bus(spi->dev);
+ break;
+ case SPI_MEM_DATA_OUT:
+ case SPI_MEM_NO_DATA:
+ rpc_spi_claim_bus(spi->dev, true);
writel(0, priv->regs + RPC_SMCR);
+ writel(0, priv->regs + RPC_SMCMR);
+ writel(RPC_SMCMR_CMD(op->cmd.opcode), priv->regs + RPC_SMCMR);
+ smenr |= RPC_SMENR_CDE;
- if (priv->cmdlen >= 1) { /* Command(1) */
- writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
- priv->regs + RPC_SMCMR);
- smenr |= RPC_SMENR_CDE;
- } else {
- writel(0, priv->regs + RPC_SMCMR);
- }
+ writel(0, priv->regs + RPC_SMADR);
+ if (op->addr.nbytes == 4)
+ smenr |= RPC_SMENR_ADE(0xF);
+ else if (op->addr.nbytes == 3)
+ smenr |= RPC_SMENR_ADE(0x7);
+ else
+ smenr |= RPC_SMENR_ADE(0);
+ writel(offset, priv->regs + RPC_SMADR);
- if (priv->cmdlen >= 4) { /* Address(3) */
- writel(offset, priv->regs + RPC_SMADR);
- smenr |= RPC_SMENR_ADE(7);
- } else {
- writel(0, priv->regs + RPC_SMADR);
- }
-
- if (priv->cmdlen >= 5) { /* Dummy(n) */
- writel(8 * (priv->cmdlen - 4) - 1,
- priv->regs + RPC_SMDMCR);
+ writel(0, priv->regs + RPC_SMDMCR);
+ if (op->dummy.nbytes) {
+ writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_SMDMCR);
smenr |= RPC_SMENR_DME;
- } else {
- writel(0, priv->regs + RPC_SMDMCR);
}
writel(0, priv->regs + RPC_SMOPR);
-
writel(0, priv->regs + RPC_SMDRENR);
- if (wlen && flags == SPI_XFER_END) {
+ if (dout && op->data.nbytes) {
u32 *datout = (u32 *)dout;
+ u32 wloop = DIV_ROUND_UP(op->data.nbytes, 4);
+
+ smenr |= RPC_SMENR_SPIDE(0xF);
while (wloop--) {
smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
@@ -314,57 +341,28 @@
writel(smenr, priv->regs + RPC_SMENR);
writel(*datout, priv->regs + RPC_SMWDR0);
writel(smcr, priv->regs + RPC_SMCR);
- ret = rpc_spi_wait_tend(dev);
- if (ret)
- goto err;
+ ret = rpc_spi_wait_tend(spi->dev);
+ if (ret) {
+ rpc_spi_release_bus(spi->dev);
+ return ret;
+ }
datout++;
- smenr = RPC_SMENR_SPIDE(0xf);
+ smenr &= (~RPC_SMENR_CDE & ~RPC_SMENR_ADE(0xF));
}
- ret = rpc_spi_wait_sslf(dev);
-
+ ret = rpc_spi_wait_sslf(spi->dev);
} else {
writel(smenr, priv->regs + RPC_SMENR);
writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
- ret = rpc_spi_wait_tend(dev);
- }
- } else { /* Read data only, using DRx ext access */
- rpc_spi_claim_bus(dev, false);
-
- if (priv->cmdlen >= 1) { /* Command(1) */
- writel(RPC_DRCMR_CMD(priv->cmdcopy[0]),
- priv->regs + RPC_DRCMR);
- smenr |= RPC_DRENR_CDE;
- } else {
- writel(0, priv->regs + RPC_DRCMR);
+ ret = rpc_spi_wait_tend(spi->dev);
}
- if (priv->cmdlen >= 4) /* Address(3) */
- smenr |= RPC_DRENR_ADE(7);
-
- if (priv->cmdlen >= 5) { /* Dummy(n) */
- writel(8 * (priv->cmdlen - 4) - 1,
- priv->regs + RPC_DRDMCR);
- smenr |= RPC_DRENR_DME;
- } else {
- writel(0, priv->regs + RPC_DRDMCR);
- }
-
- writel(0, priv->regs + RPC_DROPR);
-
- writel(smenr, priv->regs + RPC_DRENR);
-
- if (rlen)
- memcpy_fromio(din, (void *)(priv->extr + offset), rlen);
- else
- readl(priv->extr); /* Dummy read */
+ rpc_spi_release_bus(spi->dev);
+ break;
+ default:
+ break;
}
-err:
- priv->cmdstarted = false;
-
- rpc_spi_release_bus(dev);
-
return ret;
}
@@ -380,6 +378,10 @@
return 0;
}
+static const struct spi_controller_mem_ops rpc_spi_mem_ops = {
+ .exec_op = rpc_spi_mem_exec_op
+};
+
static int rpc_spi_bind(struct udevice *parent)
{
const void *fdt = gd->fdt_blob;
@@ -443,9 +445,9 @@
}
static const struct dm_spi_ops rpc_spi_ops = {
- .xfer = rpc_spi_xfer,
.set_speed = rpc_spi_set_speed,
.set_mode = rpc_spi_set_mode,
+ .mem_ops = &rpc_spi_mem_ops
};
static const struct udevice_id rpc_spi_ids[] = {
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 94fb32d..a972d87 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -126,6 +126,28 @@
value = 1s because some usb device needs around 1.5s to be initialized
and a 2s value should solve detection issue on problematic USB keys.
+if SPL_USB_HOST
+
+comment "USB peripherals in SPL"
+
+config SPL_USB_STORAGE
+ bool "Support loading from USB"
+ help
+ Enable support for USB devices in SPL. This allows use of USB
+ devices such as hard drives and flash drivers for loading U-Boot.
+ The actual drivers are enabled separately using the normal U-Boot
+ config options. This enables loading from USB using a configured
+ device.
+
+config SYS_USB_FAT_BOOT_PARTITION
+ int "Partition on USB to use to load U-Boot from"
+ depends on SPL_USB_STORAGE
+ default 1
+ help
+ Partition on the USB storage device to load U-Boot from.
+
+endif
+
if USB_KEYBOARD
config USB_KEYBOARD_FN_KEYS
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 941f97c..1cfe602 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -36,6 +36,12 @@
peripheral/device side bus controller, and a "gadget driver" for
your peripheral protocol.
+config SPL_USB_GADGET
+ bool "USB Gadget Support in SPL"
+ help
+ Enable USB Gadget API which allows to enable USB device functions
+ in SPL.
+
if USB_GADGET
config USB_GADGET_MANUFACTURER
@@ -265,3 +271,85 @@
endif # USB_ETHER
endif # USB_GADGET
+
+if SPL_USB_GADGET
+
+config SPL_USB_ETHER
+ bool "Support USB Ethernet drivers in SPL"
+ depends on SPL_NET
+ help
+ Enable access to the USB network subsystem and associated
+ drivers in SPL. This permits SPL to load U-Boot over a
+ USB-connected Ethernet link (such as a USB Ethernet dongle) rather
+ than from an onboard peripheral. Environment support is required
+ since the network stack uses a number of environment variables.
+ See also SPL_NET and SPL_ETH.
+
+if SPL_USB_ETHER
+
+choice
+ prompt "USB Ethernet Gadget Model in SPL"
+ default SPL_USB_ETH_RNDIS
+ help
+ There is several models (protocols) to implement Ethernet over USB
+ devices. The main ones are Microsoft's RNDIS and USB's CDC-Ethernet
+ (also called CDC-ECM). RNDIS is obviously compatible with Windows,
+ while CDC-ECM is not. Most other operating systems support both, so
+ if inter-operability is a concern, RNDIS is to be preferred.
+
+config SPL_USB_ETH_RNDIS
+ bool "RNDIS Protocol"
+ help
+ The RNDIS (Remote Network Driver Interface Specification) is a
+ Microsoft proprietary protocol to create an Ethernet device over USB.
+ Windows obviously supports it, as well as all the major operating
+ systems, so it's the best option for compatibility.
+
+endchoice
+
+endif # SPL_USB_ETHER
+
+config SPL_DFU
+ bool "Support DFU (Device Firmware Upgrade) in SPL"
+ select SPL_HASH
+ select SPL_DFU_NO_RESET
+ depends on SPL_RAM_SUPPORT
+ help
+ This feature enables the DFU (Device Firmware Upgrade) in SPL with
+ RAM memory device support. The ROM code will load and execute
+ the SPL built with dfu. The user can load binaries (u-boot/kernel) to
+ selected device partition from host-pc using dfu-utils.
+ This feature is useful to flash the binaries to factory or bare-metal
+ boards using USB interface.
+
+choice
+ bool "DFU device selection in SPL"
+ depends on SPL_DFU
+
+config SPL_DFU_RAM
+ bool "RAM device"
+ depends on SPL_DFU && SPL_RAM_SUPPORT
+ help
+ select RAM/DDR memory device for loading binary images
+ (u-boot/kernel) to the selected device partition using
+ DFU and execute the u-boot/kernel from RAM.
+
+endchoice
+
+config SPL_USB_SDP_SUPPORT
+ bool "Support SDP (Serial Download Protocol) in SPL"
+ depends on SPL_SERIAL
+ help
+ Enable Serial Download Protocol (SDP) device support in SPL. This
+ allows to download images into memory and execute (jump to) them
+ using the same protocol as implemented by the i.MX family's boot ROM.
+
+config SPL_SDP_USB_DEV
+ int "SDP USB controller index in SPL"
+ default 0
+ depends on SPL_USB_SDP_SUPPORT
+ help
+ Some boards have USB controller other than 0. Define this option
+ so it can be used in compiled environment.
+
+endif # SPL_USB_GADGET
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 6cfe0f3..6abcce0 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -3,8 +3,9 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o
-obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
+obj-$(CONFIG_$(SPL_TPL_)USB_GADGET) += epautoconf.o config.o usbstring.o
+obj-$(CONFIG_$(SPL_TPL_)USB_ETHER) += epautoconf.o config.o usbstring.o ether.o
+obj-$(CONFIG_$(SPL_TPL_)USB_ETH_RNDIS) += rndis.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o
@@ -34,9 +35,6 @@
obj-$(CONFIG_CI_UDC) += ci_udc.o
-obj-$(CONFIG_USB_ETHER) += ether.o
-obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o
-
# Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
# This is really only N900 and USBTTY now.
obj-$(CONFIG_USB_DEVICE) += core.o ep0.o
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6213b3c..1a883ba 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -6,6 +6,19 @@
config USB_HOST
bool
select DM_USB
+ help
+ Enable access to USB (Universal Serial Bus) host devices so that
+ SPL can load U-Boot from a connected USB peripheral, such as a USB
+ flash stick. While USB takes a little longer to start up than most
+ buses, it is very flexible since many different types of storage
+ device can be attached.
+
+config SPL_USB_HOST
+ bool "Support USB host drivers"
+ depends on SPL
+ help
+ For detailed help see USB_HOST Kconfig symbol. This option enables
+ the drivers in drivers/usb/host as part of an SPL build.
config USB_XHCI_HCD
bool "xHCI HCD (USB 3.0) support"
diff --git a/env/Kconfig b/env/Kconfig
index 2bbe4c4..7342397 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -55,20 +55,23 @@
be generous and should work in most cases. This setting can be used
to tune behaviour; see lib/hashtable.c for details.
-config ENV_IS_NOWHERE
- bool "Environment is not stored"
- default y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
+config ENV_IS_DEFAULT
+ def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
!ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \
!ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
!ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
!ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
!ENV_IS_IN_UBI
+ select ENV_IS_NOWHERE
+
+config ENV_IS_NOWHERE
+ bool "Environment is not stored"
help
- Define this if you don't want to or can't have an environment stored
+ Define this if you don't care whether or not an environment is stored
on a storage medium. In this case the environment will still exist
- while U-Boot is running, but once U-Boot exits it will not be
- stored. U-Boot will therefore always start up with a default
- environment.
+ while U-Boot is running, but once U-Boot exits it may not be
+ stored. If no other ENV_IS_IN_ is defined, U-Boot will always start
+ up with the default environment.
config ENV_IS_IN_EEPROM
bool "Environment in EEPROM"
diff --git a/env/env.c b/env/env.c
index ad774f4..2aa52c9 100644
--- a/env/env.c
+++ b/env/env.c
@@ -217,9 +217,7 @@
printf("OK\n");
gd->env_load_prio = prio;
-#if !CONFIG_IS_ENABLED(ENV_APPEND)
return 0;
-#endif
} else if (ret == -ENOMSG) {
/* Handle "bad CRC" case */
if (best_prio == -1)
diff --git a/fs/btrfs/crypto/hash.c b/fs/btrfs/crypto/hash.c
index 891a297..0a0b35f 100644
--- a/fs/btrfs/crypto/hash.c
+++ b/fs/btrfs/crypto/hash.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
+#include <asm/unaligned.h>
#include <linux/xxhash.h>
-#include <linux/unaligned/access_ok.h>
#include <linux/types.h>
#include <u-boot/sha256.h>
#include <u-boot/blake2.h>
diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c
index 96eb334..3592338 100644
--- a/fs/semihostingfs.c
+++ b/fs/semihostingfs.c
@@ -57,8 +57,12 @@
{
long fd, size, ret;
+ /* Try to open existing file */
fd = smh_open(filename, MODE_READ | MODE_BINARY | MODE_PLUS);
if (fd < 0)
+ /* Create new file */
+ fd = smh_open(filename, MODE_WRITE | MODE_BINARY);
+ if (fd < 0)
return fd;
ret = smh_seek(fd, pos);
if (ret < 0) {
diff --git a/include/.gitignore b/include/.gitignore
deleted file mode 100644
index 8e41a95..0000000
--- a/include/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-/autoconf.mk*
-/bmp_logo.h
-/bmp_logo_data.h
-/config.h
diff --git a/include/ali512x.h b/include/ali512x.h
deleted file mode 100644
index 6bb6700..0000000
--- a/include/ali512x.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- */
-
-#ifndef __ASM_IC_ALI512X_H_
-#define __ASM_IC_ALI512X_H_
-
-# define ALI_INDEX 0x3f0
-# define ALI_DATA 0x3f1
-
-# define ALI_ENABLED 1
-# define ALI_DISABLED 0
-
-# define ALI_UART1 0
-# define ALI_UART2 1
-
-/* setup functions */
-void ali512x_init(void);
-void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
-void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
-void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
-void ali512x_set_rtc(int enabled, u16 io, u8 irq);
-void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
-void ali512x_set_cio(int enabled);
-
-
-/* common I/O functions */
-void ali512x_cio_function(int pin, int special, int inv, int input);
-void ali512x_cio_out(int pin, int value);
-int ali512x_cio_in(int pin);
-
-/* misc features */
-void ali512x_set_uart2_irda(int enabled);
-
-#endif
diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h
deleted file mode 100644
index d24b82d..0000000
--- a/include/andestech/andes_pcu.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011 Andes Technology Corp
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-/*
- * Andes Power Control Unit
- */
-#ifndef __ANDES_PCU_H
-#define __ANDES_PCU_H
-
-#ifndef __ASSEMBLY__
-
-struct pcs {
- unsigned int cr; /* PCSx Configuration (clock scaling) */
- unsigned int parm; /* PCSx Parameter*/
- unsigned int stat1; /* PCSx Status 1 */
- unsigned int stat2; /* PCSx Stusts 2 */
- unsigned int pdd; /* PCSx PDD */
-};
-
-struct andes_pcu {
- unsigned int rev; /* 0x00 - PCU Revision */
- unsigned int spinfo; /* 0x04 - Scratch Pad Info */
- unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
- unsigned int soc_id; /* 0x10 - SoC ID */
- unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
- unsigned int soc_apb; /* 0x18 - SoC APB configuration */
- unsigned int rsvd2; /* 0x1C */
- unsigned int dcsrcr0; /* 0x20 - Driving Capability
- and Slew Rate Control 0 */
- unsigned int dcsrcr1; /* 0x24 - Driving Capability
- and Slew Rate Control 1 */
- unsigned int dcsrcr2; /* 0x28 - Driving Capability
- and Slew Rate Control 2 */
- unsigned int rsvd3; /* 0x2C */
- unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
- unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
- unsigned int dmaes; /* 0x38 - DMA Engine Selection */
- unsigned int rsvd4; /* 0x3C */
- unsigned int oscc; /* 0x40 - OSC Control */
- unsigned int pwmcd; /* 0x44 - PWM Clock divider */
- unsigned int socmisc; /* 0x48 - SoC Misc. */
- unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
- unsigned int bsmcr; /* 0x80 - BSM Controrl */
- unsigned int bsmst; /* 0x84 - BSM Status */
- unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
- unsigned int west; /* 0x8C - Wakeup Event Status */
- unsigned int rsttiming; /* 0x90 - Reset Timing */
- unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
- unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
- struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
- unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
- struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
- unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
- struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
- unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
- struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
- unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
- struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
- unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
- struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
- unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
- struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
- unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
- struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
- unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
- struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
- unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
- unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
- Scratch Pad Memory 0 */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * PCU Revision Register (ro)
- */
-#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
-#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
-
-/*
- * Scratch Pad Info Register (ro)
- */
-#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
-#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
-
-/*
- * SoC ID Register (ro)
- */
-#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
-#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
-#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
-
-/*
- * SoC AHB Configuration Register (ro)
- */
-#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
-#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1)
-#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2)
-#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3)
-#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4)
-#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5)
-#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6)
-#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7)
-#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8)
-#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9)
-#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12)
-#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13)
-#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14)
-#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15)
-#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16)
-#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17)
-#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18)
-#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19)
-#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20)
-#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30)
-#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31)
-
-/*
- * SoC APB Configuration Register (ro)
- */
-#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1)
-#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2)
-#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3)
-#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5)
-#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6)
-#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8)
-#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16)
-#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17)
-#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18)
-#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19)
-#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20)
-#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22)
-#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23)
-
-/*
- * Driving Capability and Slew Rate Control Register 0 (rw)
- */
-#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
-#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
-#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
-#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
-#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
-
-/*
- * Driving Capability and Slew Rate Control Register 1 (rw)
- */
-#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
-
-/*
- * Driving Capability and Slew Rate Control Register 2 (rw)
- */
-#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
-#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
-#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
-#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
-#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
-#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
-#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
-#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
-
-/*
- * Multi-function Port Setting Register 0 (rw)
- */
-#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
-#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1)
-#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2)
-#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3)
-#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4)
-#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
-#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31)
-
-/*
- * Multi-function Port Setting Register 1 (rw)
- */
-#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
-#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1)
-#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2)
-#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3)
-#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4)
-#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5)
-#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6)
-#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7)
-#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8)
-#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9)
-#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10)
-#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27)
-#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28)
-#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29)
-#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30)
-#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31)
-
-/*
- * DMA Engine Selection Register (rw)
- */
-#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2)
-#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3)
-#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4)
-#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5)
-#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6)
-#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7)
-#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8)
-#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9)
-
-/*
- * OSC Control Register (rw)
- */
-#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
-#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1)
-#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2)
-#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
-#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
-#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
-
-/*
- * PWM Clock Divider Register (rw)
- */
-#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
-
-/*
- * SoC Misc. Register (rw)
- */
-#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
-#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1)
-#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2)
-#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3)
-#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
-#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
-#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8)
-#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9)
-#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10)
-#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11)
-#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12)
-#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13)
-#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14)
-#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15)
-#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16)
-#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17)
-#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18)
-#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19)
-#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20)
-#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21)
-#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22)
-#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23)
-#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24)
-#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25)
-#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26)
-#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27)
-#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28)
-#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29)
-#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30)
-#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31)
-
-/*
- * BSM Control Register (rw)
- */
-#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
-#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
-#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
-#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
-#define ANDES_PCU_BSMCR_IE(x) ((x) << 31)
-
-/*
- * BSM Status Register
- */
-#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
-#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
-#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
-#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
-
-/*
- * Wakeup Event Sensitivity Register (rw)
- */
-#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
-
-/*
- * Wakeup Event Status Register (ro)
- */
-#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
-
-/*
- * Reset Timing Register
- */
-#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
-#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
-#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
-#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
-
-/*
- * PCU Interrupt Status Register
- */
-#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
-#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1)
-#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2)
-#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3)
-#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4)
-#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5)
-#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6)
-#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7)
-#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8)
-#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9)
-
-/*
- * PCSx Configuration Register
- */
-#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
-#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
-#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
-#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
-
-/*
- * PCSx Parameter Register (rw)
- */
-#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
-#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
-#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
-#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31)
-
-/*
- * PCSx Status Register 1
- */
-#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
-#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
-
-/*
- * PCSx Status Register 2
- */
-#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
-#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
-
-/*
- * PCSx PDD Register
- * This is reserved for PCS(1-7)
- */
-#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
-#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
-#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
-#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
-
-#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
-#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
-#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
-#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
-#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24)
-#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27)
-#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)
-#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30)
-#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31)
-
-#endif /* __ANDES_PCU_H */
diff --git a/include/asm-generic/types.h b/include/asm-generic/types.h
deleted file mode 100644
index 7c076c5..0000000
--- a/include/asm-generic/types.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_GENERIC_TYPES_H
-#define _ASM_GENERIC_TYPES_H
-/*
- * int-ll64 is used everywhere now.
- */
-#include <asm-generic/int-ll64.h>
-
-#endif /* _ASM_GENERIC_TYPES_H */
diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h
index 3d33a5a..9e5d93e 100644
--- a/include/asm-generic/unaligned.h
+++ b/include/asm-generic/unaligned.h
@@ -1,24 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _GENERIC_UNALIGNED_H
#define _GENERIC_UNALIGNED_H
#include <asm/byteorder.h>
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
+#define __get_unaligned_t(type, ptr) ({ \
+ const struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \
+ __pptr->x; \
+})
-/*
- * Select endianness
- */
-#if defined(__LITTLE_ENDIAN)
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-#elif defined(__BIG_ENDIAN)
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-#else
-#error invalid endian
-#endif
+#define __put_unaligned_t(type, val, ptr) do { \
+ struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \
+ __pptr->x = (val); \
+} while (0)
+
+#define get_unaligned(ptr) __get_unaligned_t(typeof(*(ptr)), (ptr))
+#define put_unaligned(val, ptr) __put_unaligned_t(typeof(*(ptr)), (val), (ptr))
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+ return le16_to_cpu(__get_unaligned_t(__le16, p));
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+ return le32_to_cpu(__get_unaligned_t(__le32, p));
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+ return le64_to_cpu(__get_unaligned_t(__le64, p));
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+ __put_unaligned_t(__le16, cpu_to_le16(val), p);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+ __put_unaligned_t(__le32, cpu_to_le32(val), p);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+ __put_unaligned_t(__le64, cpu_to_le64(val), p);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+ return be16_to_cpu(__get_unaligned_t(__be16, p));
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+ return be32_to_cpu(__get_unaligned_t(__be32, p));
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+ return be64_to_cpu(__get_unaligned_t(__be64, p));
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+ __put_unaligned_t(__be16, cpu_to_be16(val), p);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+ __put_unaligned_t(__be32, cpu_to_be32(val), p);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+ __put_unaligned_t(__be64, cpu_to_be64(val), p);
+}
/* Allow unaligned memory access */
void allow_unaligned(void);
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 9d2a225..2a136b9 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -35,11 +35,15 @@
#devtypel "_boot=" \
BOOTENV_SHARED_BLKDEV_BODY(devtypel)
+#define BOOTENV_DEV_BLKDEV_NONE(devtypeu, devtypel, instance)
+
#define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"devnum=" #instance "; " \
"run " #devtypel "_boot\0"
+#define BOOTENV_DEV_NAME_BLKDEV_NONE(devtypeu, devtypel, instance)
+
#define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \
#devtypel #instance " "
@@ -59,6 +63,10 @@
#define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc)
#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV
#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_SHARED_MMC
+#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV_NONE
#else
#define BOOTENV_SHARED_MMC
#define BOOTENV_DEV_MMC \
@@ -190,6 +198,10 @@
#define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata)
#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV
#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_SHARED_SATA
+#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV_NONE
#else
#define BOOTENV_SHARED_SATA
#define BOOTENV_DEV_SATA \
@@ -293,6 +305,11 @@
BOOTENV_SHARED_BLKDEV_BODY(usb)
#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV
#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_RUN_NET_USB_START
+#define BOOTENV_SHARED_USB
+#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV_NONE
#else
#define BOOTENV_RUN_NET_USB_START
#define BOOTENV_SHARED_USB
@@ -395,6 +412,9 @@
"\0"
#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
"dhcp "
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_DEV_DHCP BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_DHCP BOOTENV_DEV_NAME_BLKDEV_NONE
#else
#define BOOTENV_DEV_DHCP \
BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
@@ -413,6 +433,9 @@
"fi\0"
#define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \
"pxe "
+#elif defined(CONFIG_SPL_BUILD)
+#define BOOTENV_DEV_PXE BOOTENV_DEV_BLKDEV_NONE
+#define BOOTENV_DEV_NAME_PXE BOOTENV_DEV_NAME_BLKDEV_NONE
#else
#define BOOTENV_DEV_PXE \
BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
diff --git a/include/configs/eagle.h b/include/configs/eagle.h
deleted file mode 100644
index c751f75..0000000
--- a/include/configs/eagle.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * include/configs/eagle.h
- * This file is Eagle board configuration.
- *
- * Copyright (C) 2015 Renesas Electronics Corporation
- */
-
-#ifndef __EAGLE_H
-#define __EAGLE_H
-
-#include "rcar-gen3-common.h"
-
-/* Environment compatibility */
-
-/* Board Clock */
-/* XTAL_CLK : 33.33MHz */
-
-#endif /* __EAGLE_H */
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index 8f44c6f..cd7359c 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -40,19 +40,29 @@
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
+#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
+#define DEFAULT_DFU_ALT_INFO
+#else
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
"mtd nor1=u-boot.bin raw 200000 100000;" \
"fip.bin raw 180000 78000;" \
"optee.bin raw 500000 100000\0"
+#endif
/* GUIDs for capsule updatable firmware images */
#define DEVELOPERBOX_UBOOT_IMAGE_GUID \
EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \
0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00)
+#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
+#define DEVELOPERBOX_FIP_IMAGE_GUID \
+ EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
+ 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08)
+#else
#define DEVELOPERBOX_FIP_IMAGE_GUID \
EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \
0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
+#endif
#define DEVELOPERBOX_OPTEE_IMAGE_GUID \
EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
deleted file mode 100644
index ac6d46f..0000000
--- a/include/configs/ti816x_evm.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * ti816x_evm.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- */
-
-#ifndef __CONFIG_TI816X_EVM_H
-#define __CONFIG_TI816X_EVM_H
-
-#include <configs/ti_armv7_omap.h>
-#include <asm/arch/omap.h>
-
-#define CFG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
-#define CFG_SYS_SDRAM_BASE 0x80000000
-
-/**
- * Platform/Board specific defs
- */
-#define CFG_SYS_TIMERBASE 0x4802E000
-
-/*
- * NS16550 Configuration
- */
-#define CFG_SYS_NS16550_CLK (48000000)
-#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
-
-/* allow overwriting serial config and ethaddr */
-
-
-/*
- * GPMC NAND block. We support 1 device and the physical address to
- * access CS0 at is 0x8000000.
- */
-#define CFG_SYS_NAND_BASE 0x8000000
-
-/* NAND: SPL related configs */
-
-/* NAND: device related configs */
-/* NAND: driver related configs */
-#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CFG_SYS_NAND_ECCSIZE 512
-#define CFG_SYS_NAND_ECCBYTES 14
-
-/* SPL */
-/* Defines for SPL */
-
-#endif
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
new file mode 100644
index 0000000..58c2e88
--- /dev/null
+++ b/include/configs/v3hsk.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/v3hsk.h
+ * This file is V3HSK board configuration.
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#ifndef __V3HSK_H
+#define __V3HSK_H
+
+#include "rcar-gen3-common.h"
+
+/* Environment compatibility */
+
+/* SH Ether */
+#define CFG_SH_ETHER_USE_PORT 0
+#define CFG_SH_ETHER_PHY_ADDR 0x0
+#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
+#define CFG_SH_ETHER_CACHE_WRITEBACK
+#define CFG_SH_ETHER_CACHE_INVALIDATE
+#define CFG_SH_ETHER_ALIGNE_SIZE 64
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+
+#endif /* __V3HSK_H */
diff --git a/include/dp83848.h b/include/dp83848.h
deleted file mode 100644
index f1bc3d8..0000000
--- a/include/dp83848.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * DP83848 ethernet Physical layer
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- */
-
-
-/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
-
-#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */
-#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */
-#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */
-#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */
-#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */
-#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */
-#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */
-#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */
-#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */
-#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */
-
-/*--Bit definitions: DP83848_CTL_REG */
-#define DP83848_RESET (1 << 15) /* 1= S/W Reset */
-#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */
-#define DP83848_SPEED_SELECT (1 << 13)
-#define DP83848_AUTONEG (1 << 12)
-#define DP83848_POWER_DOWN (1 << 11)
-#define DP83848_ISOLATE (1 << 10)
-#define DP83848_RESTART_AUTONEG (1 << 9)
-#define DP83848_DUPLEX_MODE (1 << 8)
-#define DP83848_COLLISION_TEST (1 << 7)
-
-/*--Bit definitions: DP83848_STAT_REG */
-#define DP83848_100BASE_T4 (1 << 15)
-#define DP83848_100BASE_TX_FD (1 << 14)
-#define DP83848_100BASE_TX_HD (1 << 13)
-#define DP83848_10BASE_T_FD (1 << 12)
-#define DP83848_10BASE_T_HD (1 << 11)
-#define DP83848_MF_PREAMB_SUPPR (1 << 6)
-#define DP83848_AUTONEG_COMP (1 << 5)
-#define DP83848_RMT_FAULT (1 << 4)
-#define DP83848_AUTONEG_ABILITY (1 << 3)
-#define DP83848_LINK_STATUS (1 << 2)
-#define DP83848_JABBER_DETECT (1 << 1)
-#define DP83848_EXTEND_CAPAB (1 << 0)
-
-/*--definitions: DP83848_PHYID1 */
-#define DP83848_PHYID1_OUI 0x2000
-#define DP83848_PHYID2_OUI 0x5c90
-
-/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
-#define DP83848_NP (1 << 15)
-#define DP83848_ACK (1 << 14)
-#define DP83848_RF (1 << 13)
-#define DP83848_PAUSE (1 << 10)
-#define DP83848_T4 (1 << 9)
-#define DP83848_TX_FDX (1 << 8)
-#define DP83848_TX_HDX (1 << 7)
-#define DP83848_10_FDX (1 << 6)
-#define DP83848_10_HDX (1 << 5)
-#define DP83848_AN_IEEE_802_3 0x0001
-
-/*--Bit definitions: DP83848_ANER */
-#define DP83848_PDF (1 << 4)
-#define DP83848_LP_NP_ABLE (1 << 3)
-#define DP83848_NP_ABLE (1 << 2)
-#define DP83848_PAGE_RX (1 << 1)
-#define DP83848_LP_AN_ABLE (1 << 0)
-
-/*--Bit definitions: DP83848_PHY_STAT */
-#define DP83848_RX_ERR_LATCH (1 << 13)
-#define DP83848_POLARITY_STAT (1 << 12)
-#define DP83848_FALSE_CAR_SENSE (1 << 11)
-#define DP83848_SIG_DETECT (1 << 10)
-#define DP83848_DESCRAM_LOCK (1 << 9)
-#define DP83848_PAGE_RCV (1 << 8)
-#define DP83848_PHY_RMT_FAULT (1 << 6)
-#define DP83848_JABBER (1 << 5)
-#define DP83848_AUTONEG_COMPLETE (1 << 4)
-#define DP83848_LOOPBACK_STAT (1 << 3)
-#define DP83848_DUPLEX (1 << 2)
-#define DP83848_SPEED (1 << 1)
-#define DP83848_LINK (1 << 0)
diff --git a/include/ds1722.h b/include/ds1722.h
deleted file mode 100644
index e115696..0000000
--- a/include/ds1722.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef _DS1722_H_
-#define _DS1722_H_
-
-#define DS1722_RESOLUTION_8BIT 0x0
-#define DS1722_RESOLUTION_9BIT 0x1
-#define DS1722_RESOLUTION_10BIT 0x2
-#define DS1722_RESOLUTION_11BIT 0x3
-#define DS1722_RESOLUTION_12BIT 0x4
-
-int ds1722_probe(int dev);
-
-#endif /* _DS1722_H_ */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 38d7f66..11e08a8 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -1078,15 +1078,16 @@
* platforms which enable capsule updates
*
* @dfu_string: String used to populate dfu_alt_info
+ * @num_images: The number of images array entries
* @images: Pointer to an array of updatable images
*/
struct efi_capsule_update_info {
const char *dfu_string;
+ int num_images;
struct efi_fw_image *images;
};
extern struct efi_capsule_update_info update_info;
-extern u8 num_image_type_guids;
/**
* Install the ESRT system table.
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
deleted file mode 100644
index 484bd36..0000000
--- a/include/exynos_lcd.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * exynos_lcd.h - Exynos LCD Controller structures
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#ifndef _EXYNOS_LCD_H_
-#define _EXYNOS_LCD_H_
-
-enum {
- FIMD_RGB_INTERFACE = 1,
- FIMD_CPU_INTERFACE = 2,
-};
-
-enum exynos_fb_rgb_mode_t {
- MODE_RGB_P = 0,
- MODE_BGR_P = 1,
- MODE_RGB_S = 2,
- MODE_BGR_S = 3,
-};
-
-typedef struct vidinfo {
- ushort vl_col; /* Number of columns (i.e. 640) */
- ushort vl_row; /* Number of rows (i.e. 480) */
- ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
- ushort vl_width; /* Width of display area in millimeters */
- ushort vl_height; /* Height of display area in millimeters */
-
- /* LCD configuration register */
- u_char vl_freq; /* Frequency */
- u_char vl_clkp; /* Clock polarity */
- u_char vl_oep; /* Output Enable polarity */
- u_char vl_hsp; /* Horizontal Sync polarity */
- u_char vl_vsp; /* Vertical Sync polarity */
- u_char vl_dp; /* Data polarity */
- u_char vl_bpix; /* Bits per pixel */
-
- /* Horizontal control register. Timing from data sheet */
- u_char vl_hspw; /* Horz sync pulse width */
- u_char vl_hfpd; /* Wait before of line */
- u_char vl_hbpd; /* Wait end of line */
-
- /* Vertical control register. */
- u_char vl_vspw; /* Vertical sync pulse width */
- u_char vl_vfpd; /* Wait before of frame */
- u_char vl_vbpd; /* Wait end of frame */
- u_char vl_cmd_allow_len; /* Wait end of frame */
-
- unsigned int win_id;
- unsigned int init_delay;
- unsigned int power_on_delay;
- unsigned int reset_delay;
- unsigned int interface_mode;
- unsigned int mipi_enabled;
- unsigned int dp_enabled;
- unsigned int cs_setup;
- unsigned int wr_setup;
- unsigned int wr_act;
- unsigned int wr_hold;
- unsigned int logo_on;
- unsigned int logo_width;
- unsigned int logo_height;
- int logo_x_offset;
- int logo_y_offset;
- unsigned long logo_addr;
- unsigned int rgb_mode;
- unsigned int resolution;
-
- /* parent clock name(MPLL, EPLL or VPLL) */
- unsigned int pclk_name;
- /* ratio value for source clock from parent clock. */
- unsigned int sclk_div;
-
- unsigned int dual_lcd_enabled;
- struct exynos_fb *reg;
- struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
-} vidinfo_t;
-
-#endif
diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h
deleted file mode 100644
index e628156..0000000
--- a/include/faraday/ftahbc020s.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
-#ifndef __FTAHBC020S_H
-#define __FTAHBC202S_H
-
-/* Registers Offsets */
-
-/*
- * AHB Slave BSR, offset: n * 4, n=0~31
- */
-#ifndef __ASSEMBLY__
-struct ftahbc02s {
- unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */
- unsigned int pcr; /* 0x80 - Priority Ctrl Reg */
- unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */
- unsigned int cr; /* 0x88 - Ctrl Reg */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
- */
-#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20)
-#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16)
-/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
-#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */
-
-/*
- * FTAHBC020S_PCR - Priority Control Register
- */
-#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */
-
-/*
- * FTAHBC020S_CR - Interrupt Control Register
- */
-#define FTAHBC020S_CR_INTSTS (1 << 24)
-#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20)
-#define FTAHBC020S_CR_INTSMASK (1 << 16)
-#define FTAHBC020S_CR_REMAP (1 << 0)
-
-#endif /* __FTAHBC020S_H */
diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h
deleted file mode 100644
index 8801bd1..0000000
--- a/include/faraday/ftpci100.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
- *
- * Copyright (C) 2010 Andes Technology Corporation
- * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __FTPCI100_H
-#define __FTPCI100_H
-
-/* AHB Control Registers */
-#include <linux/bitops.h>
-struct ftpci100_ahbc {
- unsigned int iosize; /* 0x00 - I/O Space Size Signal */
- unsigned int prot; /* 0x04 - AHB Protection */
- unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
- unsigned int conf; /* 0x28 - PCI Configuration */
- unsigned int data; /* 0x2c - PCI Configuration DATA */
-};
-
-/*
- * FTPCI100_IOSIZE_REG's constant definitions
- */
-#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
-
-/*
- * PCI Configuration Register
- */
-#define PCI_INT_MASK 0x4c
-#define PCI_MEM_BASE_SIZE1 0x50
-#define PCI_MEM_BASE_SIZE2 0x54
-#define PCI_MEM_BASE_SIZE3 0x58
-
-/*
- * PCI_INT_MASK's bit definitions
- */
-#define PCI_INTA_ENABLE (1 << 22)
-#define PCI_INTB_ENABLE (1 << 23)
-#define PCI_INTC_ENABLE (1 << 24)
-#define PCI_INTD_ENABLE (1 << 25)
-
-/*
- * PCI_MEM_BASE_SIZE1's constant definitions
- */
-#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
-
-#define FTPCI100_MAX_FUNCTIONS 20
-#define PCI_IRQ_LINES 4
-
-#define MAX_BUS_NUM 256
-#define MAX_DEV_NUM 32
-#define MAX_FUN_NUM 8
-
-#define PCI_MAX_BAR_PER_FUNC 6
-
-/*
- * PCI_MEM_SIZE
- */
-#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
-
-/* This definition is used by pci_ftpci_init() */
-#define FTPCI100_BRIDGE_VENDORID 0x159b
-#define FTPCI100_BRIDGE_DEVICEID 0x4321
-
-void pci_ftpci_init(void);
-
-struct pcibar {
- unsigned int size;
- unsigned int addr;
-};
-
-struct pci_config {
- unsigned int bus;
- unsigned int dev; /* device */
- unsigned int func;
- unsigned int pin;
- unsigned short v_id; /* vendor id */
- unsigned short d_id; /* device id */
- struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
-};
-
-#endif
diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h
deleted file mode 100644
index d74da16..0000000
--- a/include/faraday/ftsdmc020.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- */
-
-/*
- * SDRAM Controller
- */
-#ifndef __FTSDMC020_H
-#define __FTSDMC020_H
-
-#define FTSDMC020_OFFSET_TP0 0x00
-#define FTSDMC020_OFFSET_TP1 0x04
-#define FTSDMC020_OFFSET_CR 0x08
-#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
-#define FTSDMC020_OFFSET_BANK1_BSR 0x10
-#define FTSDMC020_OFFSET_BANK2_BSR 0x14
-#define FTSDMC020_OFFSET_BANK3_BSR 0x18
-#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
-#define FTSDMC020_OFFSET_BANK5_BSR 0x20
-#define FTSDMC020_OFFSET_BANK6_BSR 0x24
-#define FTSDMC020_OFFSET_BANK7_BSR 0x28
-#define FTSDMC020_OFFSET_ACR 0x34
-
-/*
- * Timing Parametet 0 Register
- */
-#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
-#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
-#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
-#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
-#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
-#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
-
-/*
- * Timing Parametet 1 Register
- */
-#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
-#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
-#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
-
-/*
- * Configuration Register
- */
-#define FTSDMC020_CR_SREF (1 << 0)
-#define FTSDMC020_CR_PWDN (1 << 1)
-#define FTSDMC020_CR_ISMR (1 << 2)
-#define FTSDMC020_CR_IREF (1 << 3)
-#define FTSDMC020_CR_IPREC (1 << 4)
-#define FTSDMC020_CR_REFTYPE (1 << 5)
-
-/*
- * SDRAM External Bank Base/Size Register
- */
-#define FTSDMC020_BANK_ENABLE (1 << 28)
-
-#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
-
-#define FTSDMC020_BANK_DDW_X4 (0 << 12)
-#define FTSDMC020_BANK_DDW_X8 (1 << 12)
-#define FTSDMC020_BANK_DDW_X16 (2 << 12)
-#define FTSDMC020_BANK_DDW_X32 (3 << 12)
-
-#define FTSDMC020_BANK_DSZ_16M (0 << 8)
-#define FTSDMC020_BANK_DSZ_64M (1 << 8)
-#define FTSDMC020_BANK_DSZ_128M (2 << 8)
-#define FTSDMC020_BANK_DSZ_256M (3 << 8)
-
-#define FTSDMC020_BANK_MBW_8 (0 << 4)
-#define FTSDMC020_BANK_MBW_16 (1 << 4)
-#define FTSDMC020_BANK_MBW_32 (2 << 4)
-
-#define FTSDMC020_BANK_SIZE_1M 0x0
-#define FTSDMC020_BANK_SIZE_2M 0x1
-#define FTSDMC020_BANK_SIZE_4M 0x2
-#define FTSDMC020_BANK_SIZE_8M 0x3
-#define FTSDMC020_BANK_SIZE_16M 0x4
-#define FTSDMC020_BANK_SIZE_32M 0x5
-#define FTSDMC020_BANK_SIZE_64M 0x6
-#define FTSDMC020_BANK_SIZE_128M 0x7
-#define FTSDMC020_BANK_SIZE_256M 0x8
-
-/*
- * Arbiter Control Register
- */
-#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
-#define FTSDMC020_ACR_TOE (1 << 8)
-
-#endif /* __FTSDMC020_H */
diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h
deleted file mode 100644
index e0e5eb3..0000000
--- a/include/faraday/ftsdmc021.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * (C) Copyright 2011 Andes Technology Corp
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-/*
- * FTSDMC021 - SDRAM Controller
- */
-#ifndef __FTSDMC021_H
-#define __FTSDMC021_H
-
-#ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-struct ftsdmc021 {
- unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */
- unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */
- unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */
- unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */
- unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */
- unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */
- unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */
- unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */
- unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */
- unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */
- unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */
- unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */
- unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */
- unsigned int frr; /* 0x34 - Flush Request Register */
- unsigned int ebisr; /* 0x38 - EBI Support Register */
- unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */
- unsigned int crr; /* 0x100 - Controller Revision Reg */
- unsigned int cfr; /* 0x104 - Controller Feature Reg */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * Timing Parameter 1 Register
- */
-#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */
-#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */
-#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */
-#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */
-#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */
-#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20)
-
-/*
- * Timing Parameter 2 Register
- */
-#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */
-/* b(16:19) - Initial Refresh Times */
-#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16)
-/* b(20:23) - Initial Pre-Charge Times */
-#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20)
-
-/*
- * SDRAM Configuration Register 1
- */
-#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */
-#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */
-#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */
-#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */
-/* b(16) MA2T: Double Memory Address Cycle Enable */
-#define FTSDMC021_CR1_MA2T(x) (1 << 16)
-/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
-#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1)
-
-/*
- * Configuration Register 2
- */
-#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */
-#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */
-#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */
-#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */
-#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */
-#define FTSDMC021_CR2_REFTYPE (1 << 5)
-
-/*
- * SDRAM External Bank Base/Size Register
- */
-#define FTSDMC021_BANK_ENABLE (1 << 12)
-
-/* 12-bit base address of external bank.
- * Default value is 0x800.
- * The 12-bit equals to the haddr[31:20] of AHB address bus. */
-#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff)
-
-/*
- * Read Arbitration Grant Window Register
- */
-#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0)
-#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4)
-#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8)
-#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12)
-#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16)
-#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20)
-#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24)
-#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28)
-
-/*
- * Flush Request Register
- */
-#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0)
-#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */
-
-/*
- * External Bus Interface Support Register (EBISR)
- */
-#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */
-#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */
-#define FTSDMC021_EBISR_POPREC (1 << 13)
-#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */
-
-/*
- * Controller Revision Register (CRR, Read Only)
- */
-#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff)
-#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff)
-#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff)
-
-/*
- * Controller Feature Register (CFR, Read Only)
- */
-#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf)
-#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf)
-#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1)
-#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1)
-#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1)
-#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1)
-#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1)
-#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1)
-#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1)
-#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1)
-#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1)
-
-#endif /* __FTSDMC021_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 5638bd4..eeb83e6 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -7,7 +7,8 @@
#ifndef __FDT_SUPPORT_H
#define __FDT_SUPPORT_H
-#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC)
+#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \
+ !defined(USE_HOSTCC)
#include <asm/u-boot.h>
#include <linux/libfdt.h>
diff --git a/include/fwu.h b/include/fwu.h
index 0919ced..ac5c5de 100644
--- a/include/fwu.h
+++ b/include/fwu.h
@@ -8,6 +8,8 @@
#include <blk.h>
#include <efi.h>
+#include <mtd.h>
+#include <uuid.h>
#include <linux/types.h>
@@ -18,83 +20,32 @@
struct udevice *blk_dev;
};
-/**
- * @mdata_check: check the validity of the FWU metadata partitions
- * @get_mdata() - Get a FWU metadata copy
- * @update_mdata() - Update the FWU metadata copy
- */
+struct fwu_mtd_image_info {
+ u32 start, size;
+ int bank_num, image_num;
+ char uuidbuf[UUID_STR_LEN + 1];
+};
+
struct fwu_mdata_ops {
/**
- * check_mdata() - Check if the FWU metadata is valid
- * @dev: FWU device
- *
- * Validate both copies of the FWU metadata. If one of the copies
- * has gone bad, restore it from the other copy.
+ * read_mdata() - Populate the asked FWU metadata copy
+ * @dev: FWU metadata device
+ * @mdata: Output FWU mdata read
+ * @primary: If primary or secondary copy of metadata is to be read
*
* Return: 0 if OK, -ve on error
*/
- int (*check_mdata)(struct udevice *dev);
+ int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
/**
- * get_mdata() - Get a FWU metadata copy
- * @dev: FWU device
- * @mdata: Pointer to FWU metadata
- *
- * Get a valid copy of the FWU metadata.
+ * write_mdata() - Write the given FWU metadata copy
+ * @dev: FWU metadata device
+ * @mdata: Copy of the FWU metadata to write
+ * @primary: If primary or secondary copy of metadata is to be written
*
* Return: 0 if OK, -ve on error
*/
- int (*get_mdata)(struct udevice *dev, struct fwu_mdata *mdata);
-
- /**
- * update_mdata() - Update the FWU metadata
- * @dev: FWU device
- * @mdata: Copy of the FWU metadata
- *
- * Update the FWU metadata structure by writing to the
- * FWU metadata partitions.
- *
- * Return: 0 if OK, -ve on error
- */
- int (*update_mdata)(struct udevice *dev, struct fwu_mdata *mdata);
-
- /**
- * get_mdata_part_num() - Get the FWU metadata partition numbers
- * @dev: FWU metadata device
- * @mdata_parts: array for storing the metadata partition numbers
- *
- * Get the partition numbers on the storage device on which the
- * FWU metadata is stored. Two partition numbers will be returned.
- *
- * Return: 0 if OK, -ve on error
- */
- int (*get_mdata_part_num)(struct udevice *dev, uint *mdata_parts);
-
- /**
- * read_mdata_partition() - Read the FWU metadata from a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number from which FWU metadata is to be read
- *
- * Read the FWU metadata from the specified partition number
- *
- * Return: 0 if OK, -ve on error
- */
- int (*read_mdata_partition)(struct udevice *dev,
- struct fwu_mdata *mdata, uint part_num);
-
- /**
- * write_mdata_partition() - Write the FWU metadata to a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number to which FWU metadata is to be written
- *
- * Write the FWU metadata to the specified partition number
- *
- * Return: 0 if OK, -ve on error
- */
- int (*write_mdata_partition)(struct udevice *dev,
- struct fwu_mdata *mdata, uint part_num);
+ int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
};
#define FWU_MDATA_VERSION 0x1
@@ -127,100 +78,25 @@
0xe1, 0xfc, 0xed, 0xf1, 0xc6, 0xf8)
/**
- * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies
- *
- * Read both the metadata copies from the storage media, verify their
- * checksum, and ascertain that both copies match. If one of the copies
- * has gone bad, restore it from the good copy.
- *
- * Return: 0 if OK, -ve on error
- *
+ * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata()
*/
-int fwu_check_mdata_validity(void);
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
/**
- * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers
- * @dev: FWU metadata device
- * @mdata_parts: array for storing the metadata partition numbers
- *
- * Get the partition numbers on the storage device on which the
- * FWU metadata is stored. Two partition numbers will be returned
- * through the array.
- *
- * Return: 0 if OK, -ve on error
- *
+ * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata()
*/
-int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts);
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
/**
- * fwu_read_mdata_partition() - Read the FWU metadata from a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number from which FWU metadata is to be read
+ * fwu_get_mdata() - Read, verify and return the FWU metadata
*
- * Read the FWU metadata from the specified partition number
+ * Read both the metadata copies from the storage media, verify their checksum,
+ * and ascertain that both copies match. If one of the copies has gone bad,
+ * restore it from the good copy.
*
* Return: 0 if OK, -ve on error
- *
*/
-int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
- uint part_num);
-
-/**
- * fwu_write_mdata_partition() - Write the FWU metadata to a partition
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- * @part_num: Partition number to which FWU metadata is to be written
- *
- * Write the FWU metadata to the specified partition number
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata,
- uint part_num);
-
-/**
- * fwu_get_mdata() - Get a FWU metadata copy
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Get a valid copy of the FWU metadata.
- *
- * Note: This function is to be called first when modifying any fields
- * in the metadata. The sequence of calls to modify any field in the
- * metadata would be 1) fwu_get_mdata 2) Modify metadata, followed by
- * 3) fwu_update_mdata
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata);
-
-/**
- * fwu_update_mdata() - Update the FWU metadata
- * @dev: FWU metadata device
- * @mdata: Copy of the FWU metadata
- *
- * Update the FWU metadata structure by writing to the
- * FWU metadata partitions.
- *
- * Note: This function is not to be called directly to update the
- * metadata fields. The sequence of function calls should be
- * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata()
- *
- * The sequence of updating the partitions should be, update the
- * primary metadata partition (first partition encountered), followed
- * by updating the secondary partition. With this update sequence, in
- * the rare scenario that the two metadata partitions are valid but do
- * not match, maybe due to power outage at the time of updating the
- * metadata copies, the secondary partition can be updated from the
- * primary.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata);
+int fwu_get_mdata(struct fwu_mdata *mdata);
/**
* fwu_get_active_index() - Get active_index from the FWU metadata
@@ -263,18 +139,6 @@
int fwu_get_image_index(u8 *image_index);
/**
- * fwu_mdata_check() - Check if the FWU metadata is valid
- * @dev: FWU metadata device
- *
- * Validate both copies of the FWU metadata. If one of the copies
- * has gone bad, restore it from the other copy.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_mdata_check(struct udevice *dev);
-
-/**
* fwu_revert_boot_index() - Revert the active index in the FWU metadata
*
* Revert the active_index value in the FWU metadata, by swapping the values
@@ -287,20 +151,6 @@
int fwu_revert_boot_index(void);
/**
- * fwu_verify_mdata() - Verify the FWU metadata
- * @mdata: FWU metadata structure
- * @pri_part: FWU metadata partition is primary or secondary
- *
- * Verify the FWU metadata by computing the CRC32 for the metadata
- * structure and comparing it against the CRC32 value stored as part
- * of the structure.
- *
- * Return: 0 if OK, -ve on error
- *
- */
-int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part);
-
-/**
* fwu_accept_image() - Set the Acceptance bit for the image
* @img_type_id: GUID of the image type for which the accepted bit is to be
* cleared
@@ -409,4 +259,28 @@
*/
int fwu_trial_state_ctr_start(void);
+/**
+ * fwu_gen_alt_info_from_mtd() - Parse dfu_alt_info from metadata in mtd
+ * @buf: Buffer into which the dfu_alt_info is filled
+ * @len: Maximum characters that can be written in buf
+ * @mtd: Pointer to underlying MTD device
+ *
+ * Parse dfu_alt_info from metadata in mtd. Used for setting the env.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd);
+
+/**
+ * fwu_mtd_get_alt_num() - Mapping of fwu_plat_get_alt_num for MTD device
+ * @image_guid: Image GUID for which DFU alt number needs to be retrieved
+ * @alt_num: Pointer to the alt_num
+ * @mtd_dev: Name of mtd device instance
+ *
+ * To map fwu_plat_get_alt_num onto mtd based metadata implementation.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev);
+
#endif /* _FWU_H_ */
diff --git a/include/imx_sip.h b/include/imx_sip.h
index 1b873f2..ebbb3a1 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -4,7 +4,7 @@
*/
#ifndef _IMX_SIP_H__
-#define _IMX_SIP_H_
+#define _IMX_SIP_H__
#define IMX_SIP_GPC 0xC2000000
#define IMX_SIP_GPC_PM_DOMAIN 0x03
diff --git a/include/lcd_console.h b/include/lcd_console.h
deleted file mode 100644
index 061a6a4..0000000
--- a/include/lcd_console.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
- */
-
-/* By default we scroll by a single line */
-
-struct console_t {
- short curr_col, curr_row;
- short cols, rows;
- void *fbbase;
- u32 lcdsizex, lcdsizey, lcdrot;
- void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c);
- void (*fp_console_moverow)(struct console_t *pcons,
- u32 rowdst, u32 rowsrc);
- void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr);
-};
-
-/**
- * console_calc_rowcol() - calculate available rows / columns wihtin a given
- * screen-size based on used VIDEO_FONT.
- *
- * @pcons: Pointer to struct console_t
- * @sizex: size X of the screen in pixel
- * @sizey: size Y of the screen in pixel
- */
-void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey);
-/**
- * lcd_init_console() - Initialize lcd console parameters
- *
- * Setup the address of console base, and the number of rows and columns the
- * console has.
- *
- * @address: Console base address
- * @vl_rows: Number of rows in the console
- * @vl_cols: Number of columns in the console
- * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise
- */
-void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot);
-/**
- * lcd_set_col() - Set the number of the current lcd console column
- *
- * Set the number of the console column where the cursor is.
- *
- * @col: Column number
- */
-void lcd_set_col(short col);
-
-/**
- * lcd_set_row() - Set the number of the current lcd console row
- *
- * Set the number of the console row where the cursor is.
- *
- * @row: Row number
- */
-void lcd_set_row(short row);
-
-/**
- * lcd_position_cursor() - Position the cursor on the screen
- *
- * Position the cursor at the given coordinates on the screen.
- *
- * @col: Column number
- * @row: Row number
- */
-void lcd_position_cursor(unsigned col, unsigned row);
-
-/**
- * lcd_get_screen_rows() - Get the total number of screen rows
- *
- * @return: Number of screen rows
- */
-int lcd_get_screen_rows(void);
-
-/**
- * lcd_get_screen_columns() - Get the total number of screen columns
- *
- * @return: Number of screen columns
- */
-int lcd_get_screen_columns(void);
-
-/**
- * lcd_putc() - Print to screen a single character at the location of the cursor
- *
- * @c: The character to print
- */
-void lcd_putc(const char c);
-
-/**
- * lcd_puts() - Print to screen a string at the location of the cursor
- *
- * @s: The string to print
- */
-void lcd_puts(const char *s);
-
-/**
- * lcd_printf() - Print to screen a formatted string at location of the cursor
- *
- * @fmt: The formatted string to print
- * @...: The arguments for the formatted string
- */
-void lcd_printf(const char *fmt, ...);
diff --git a/include/lcdvideo.h b/include/lcdvideo.h
deleted file mode 100644
index f0640a5..0000000
--- a/include/lcdvideo.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * MPC823 LCD and Video Controller
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- */
-#ifndef __LCDVIDEO_H__
-#define __LCDVIDEO_H__
-
-
-/* LCD Controller Configuration Register.
-*/
-#define LCCR_BNUM ((uint)0xfffe0000)
-#define LCCR_EIEN ((uint)0x00010000)
-#define LCCR_IEN ((uint)0x00008000)
-#define LCCR_IRQL ((uint)0x00007000)
-#define LCCR_CLKP ((uint)0x00000800)
-#define LCCR_OEP ((uint)0x00000400)
-#define LCCR_HSP ((uint)0x00000200)
-#define LCCR_VSP ((uint)0x00000100)
-#define LCCR_DP ((uint)0x00000080)
-#define LCCR_BPIX ((uint)0x00000060)
-#define LCCR_LBW ((uint)0x00000010)
-#define LCCR_SPLT ((uint)0x00000008)
-#define LCCR_CLOR ((uint)0x00000004)
-#define LCCR_TFT ((uint)0x00000002)
-#define LCCR_PON ((uint)0x00000001)
-
-/* Define the bit shifts to load values into the register.
-*/
-#define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT))
-
-#define LCCR_BNUM_BIT ((uint)14)
-#define LCCR_EIEN_BIT ((uint)15)
-#define LCCR_IEN_BIT ((uint)16)
-#define LCCR_IROL_BIT ((uint)19)
-#define LCCR_CLKP_BIT ((uint)20)
-#define LCCR_OEP_BIT ((uint)21)
-#define LCCR_HSP_BIT ((uint)22)
-#define LCCR_VSP_BIT ((uint)23)
-#define LCCR_DP_BIT ((uint)24)
-#define LCCR_BPIX_BIT ((uint)26)
-#define LCCR_LBW_BIT ((uint)27)
-#define LCCR_SPLT_BIT ((uint)28)
-#define LCCR_CLOR_BIT ((uint)29)
-#define LCCR_TFT_BIT ((uint)30)
-#define LCCR_PON_BIT ((uint)31)
-
-/* LCD Horizontal control register.
-*/
-#define LCHCR_BO ((uint)0x01000000)
-#define LCHCR_AT ((uint)0x00e00000)
-#define LCHCR_HPC ((uint)0x001ffc00)
-#define LCHCR_WBL ((uint)0x000003ff)
-
-#define LCHCR_AT_BIT ((uint)10)
-#define LCHCR_HPC_BIT ((uint)21)
-#define LCHCR_WBL_BIT ((uint)31)
-
-/* LCD Vertical control register.
-*/
-#define LCVCR_VPW ((uint)0xf0000000)
-#define LCVCR_LCD_AC ((uint)0x01e00000)
-#define LCVCR_VPC ((uint)0x001ff800)
-#define LCVCR_WBF ((uint)0x000003ff)
-
-#define LCVCR_VPW_BIT ((uint)3)
-#define LCVCR_LCD_AC_BIT ((uint)10)
-#define LCVCR_VPC_BIT ((uint)20)
-
-#endif /* __LCDVIDEO_H__ */
diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h
index 9c7088b..20c2dc7 100644
--- a/include/linux/build_bug.h
+++ b/include/linux/build_bug.h
@@ -4,15 +4,16 @@
#include <linux/compiler.h>
#ifdef __CHECKER__
-#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
-#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
#define BUILD_BUG_ON_ZERO(e) (0)
-#define BUILD_BUG_ON_NULL(e) ((void *)0)
-#define BUILD_BUG_ON_INVALID(e) (0)
-#define BUILD_BUG_ON_MSG(cond, msg) (0)
-#define BUILD_BUG_ON(condition) (0)
-#define BUILD_BUG() (0)
#else /* __CHECKER__ */
+/*
+ * Force a compilation error if condition is true, but also produce a
+ * result (of value 0 and type int), so the expression can be used
+ * e.g. in a structure initializer (or where-ever else comma expressions
+ * aren't permitted).
+ */
+#define BUILD_BUG_ON_ZERO(e) ((int)sizeof(struct { int:(-!!(e)); }))
+#endif /* __CHECKER__ */
/* Force a compilation error if a constant expression is not a power of 2 */
#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) \
@@ -21,15 +22,6 @@
BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
/*
- * Force a compilation error if condition is true, but also produce a
- * result (of value 0 and type size_t), so the expression can be used
- * e.g. in a structure initializer (or where-ever else comma expressions
- * aren't permitted).
- */
-#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); }))
-#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); }))
-
-/*
* BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the
* expression but avoids the generation of any code, even if that expression
* has side-effects.
@@ -52,23 +44,9 @@
* If you have some code which relies on certain constants being equal, or
* some other compile-time-evaluated condition, you should use BUILD_BUG_ON to
* detect if someone changes it.
- *
- * The implementation uses gcc's reluctance to create a negative array, but gcc
- * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to
- * inline functions). Luckily, in 4.3 they added the "error" function
- * attribute just for this type of case. Thus, we use a negative sized array
- * (should always create an error on gcc versions older than 4.4) and then call
- * an undefined function with the error attribute (should always create an
- * error on gcc 4.3 and later). If for some reason, neither creates a
- * compile-time error, we'll still have a link-time error, which is harder to
- * track down.
*/
-#ifndef __OPTIMIZE__
-#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
-#else
#define BUILD_BUG_ON(condition) \
BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
-#endif
/**
* BUILD_BUG - break compile if used.
@@ -98,6 +76,4 @@
#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr)
#define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
-#endif /* __CHECKER__ */
-
#endif /* _LINUX_BUILD_BUG_H */
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
deleted file mode 100644
index 0644d92..0000000
--- a/include/linux/mc146818rtc.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
- * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
- * derived from Data Sheet, Copyright Motorola 1984 (!).
- * It was written to be part of the Linux operating system.
- */
-/* permission is hereby granted to copy, modify and redistribute this code
- * in terms of the GNU Library General Public License, Version 2 or later,
- * at your option.
- */
-
-#ifndef _MC146818RTC_H
-#define _MC146818RTC_H
-
-#include <asm/io.h>
-#include <linux/rtc.h> /* get the user-level API */
-#include <asm/mc146818rtc.h> /* register access macros */
-
-/**********************************************************************
- * register summary
- **********************************************************************/
-#define RTC_SECONDS 0
-#define RTC_SECONDS_ALARM 1
-#define RTC_MINUTES 2
-#define RTC_MINUTES_ALARM 3
-#define RTC_HOURS 4
-#define RTC_HOURS_ALARM 5
-/* RTC_*_alarm is always true if 2 MSBs are set */
-# define RTC_ALARM_DONT_CARE 0xC0
-
-#define RTC_DAY_OF_WEEK 6
-#define RTC_DAY_OF_MONTH 7
-#define RTC_MONTH 8
-#define RTC_YEAR 9
-
-/* control registers - Moto names
- */
-#define RTC_REG_A 10
-#define RTC_REG_B 11
-#define RTC_REG_C 12
-#define RTC_REG_D 13
-
-/**********************************************************************
- * register details
- **********************************************************************/
-#define RTC_FREQ_SELECT RTC_REG_A
-
-/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
- * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
- * totalling to a max high interval of 2.228 ms.
- */
-# define RTC_UIP 0x80
-# define RTC_DIV_CTL 0x70
- /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
-# define RTC_REF_CLCK_4MHZ 0x00
-# define RTC_REF_CLCK_1MHZ 0x10
-# define RTC_REF_CLCK_32KHZ 0x20
- /* 2 values for divider stage reset, others for "testing purposes only" */
-# define RTC_DIV_RESET1 0x60
-# define RTC_DIV_RESET2 0x70
- /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
-# define RTC_RATE_SELECT 0x0F
-
-/**********************************************************************/
-#define RTC_CONTROL RTC_REG_B
-# define RTC_SET 0x80 /* disable updates for clock setting */
-# define RTC_PIE 0x40 /* periodic interrupt enable */
-# define RTC_AIE 0x20 /* alarm interrupt enable */
-# define RTC_UIE 0x10 /* update-finished interrupt enable */
-# define RTC_SQWE 0x08 /* enable square-wave output */
-# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
-# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
-# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
-
-/**********************************************************************/
-#define RTC_INTR_FLAGS RTC_REG_C
-/* caution - cleared by read */
-# define RTC_IRQF 0x80 /* any of the following 3 is active */
-# define RTC_PF 0x40
-# define RTC_AF 0x20
-# define RTC_UF 0x10
-
-/**********************************************************************/
-#define RTC_VALID RTC_REG_D
-# define RTC_VRT 0x80 /* valid RAM and time */
-/**********************************************************************/
-#endif /* _MC146818RTC_H */
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
deleted file mode 100644
index a72cb7d..0000000
--- a/include/linux/mtd/doc2000.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Linux driver for Disk-On-Chip devices
- *
- * Copyright © 1999 Machine Vision Holdings, Inc.
- * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
- * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
- * Copyright © 2002-2003 SnapGear Inc
- *
- */
-
-#ifndef __MTD_DOC2000_H__
-#define __MTD_DOC2000_H__
-
-#include <linux/mtd/mtd.h>
-#if 0
-#include <linux/mutex.h>
-#endif
-
-#define DoC_Sig1 0
-#define DoC_Sig2 1
-
-#define DoC_ChipID 0x1000
-#define DoC_DOCStatus 0x1001
-#define DoC_DOCControl 0x1002
-#define DoC_FloorSelect 0x1003
-#define DoC_CDSNControl 0x1004
-#define DoC_CDSNDeviceSelect 0x1005
-#define DoC_ECCConf 0x1006
-#define DoC_2k_ECCStatus 0x1007
-
-#define DoC_CDSNSlowIO 0x100d
-#define DoC_ECCSyndrome0 0x1010
-#define DoC_ECCSyndrome1 0x1011
-#define DoC_ECCSyndrome2 0x1012
-#define DoC_ECCSyndrome3 0x1013
-#define DoC_ECCSyndrome4 0x1014
-#define DoC_ECCSyndrome5 0x1015
-#define DoC_AliasResolution 0x101b
-#define DoC_ConfigInput 0x101c
-#define DoC_ReadPipeInit 0x101d
-#define DoC_WritePipeTerm 0x101e
-#define DoC_LastDataRead 0x101f
-#define DoC_NOP 0x1020
-
-#define DoC_Mil_CDSN_IO 0x0800
-#define DoC_2k_CDSN_IO 0x1800
-
-#define DoC_Mplus_NOP 0x1002
-#define DoC_Mplus_AliasResolution 0x1004
-#define DoC_Mplus_DOCControl 0x1006
-#define DoC_Mplus_AccessStatus 0x1008
-#define DoC_Mplus_DeviceSelect 0x1008
-#define DoC_Mplus_Configuration 0x100a
-#define DoC_Mplus_OutputControl 0x100c
-#define DoC_Mplus_FlashControl 0x1020
-#define DoC_Mplus_FlashSelect 0x1022
-#define DoC_Mplus_FlashCmd 0x1024
-#define DoC_Mplus_FlashAddress 0x1026
-#define DoC_Mplus_FlashData0 0x1028
-#define DoC_Mplus_FlashData1 0x1029
-#define DoC_Mplus_ReadPipeInit 0x102a
-#define DoC_Mplus_LastDataRead 0x102c
-#define DoC_Mplus_LastDataRead1 0x102d
-#define DoC_Mplus_WritePipeTerm 0x102e
-#define DoC_Mplus_ECCSyndrome0 0x1040
-#define DoC_Mplus_ECCSyndrome1 0x1041
-#define DoC_Mplus_ECCSyndrome2 0x1042
-#define DoC_Mplus_ECCSyndrome3 0x1043
-#define DoC_Mplus_ECCSyndrome4 0x1044
-#define DoC_Mplus_ECCSyndrome5 0x1045
-#define DoC_Mplus_ECCConf 0x1046
-#define DoC_Mplus_Toggle 0x1046
-#define DoC_Mplus_DownloadStatus 0x1074
-#define DoC_Mplus_CtrlConfirm 0x1076
-#define DoC_Mplus_Power 0x1fff
-
-/* How to access the device?
- * On ARM, it'll be mmap'd directly with 32-bit wide accesses.
- * On PPC, it's mmap'd and 16-bit wide.
- * Others use readb/writeb
- */
-#if defined(__arm__)
-#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
-#define WriteDOC_(d, adr, reg) do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
-#define DOC_IOREMAP_LEN 0x8000
-#elif defined(__ppc__)
-#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
-#define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
-#define DOC_IOREMAP_LEN 0x4000
-#else
-#define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg))
-#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg))
-#define DOC_IOREMAP_LEN 0x2000
-
-#endif
-
-#if defined(__i386__) || defined(__x86_64__)
-#define USE_MEMCPY
-#endif
-
-/* These are provided to directly use the DoC_xxx defines */
-#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg)
-#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg)
-
-#define DOC_MODE_RESET 0
-#define DOC_MODE_NORMAL 1
-#define DOC_MODE_RESERVED1 2
-#define DOC_MODE_RESERVED2 3
-
-#define DOC_MODE_CLR_ERR 0x80
-#define DOC_MODE_RST_LAT 0x10
-#define DOC_MODE_BDECT 0x08
-#define DOC_MODE_MDWREN 0x04
-
-#define DOC_ChipID_Doc2k 0x20
-#define DOC_ChipID_Doc2kTSOP 0x21 /* internal number for MTD */
-#define DOC_ChipID_DocMil 0x30
-#define DOC_ChipID_DocMilPlus32 0x40
-#define DOC_ChipID_DocMilPlus16 0x41
-
-#define CDSN_CTRL_FR_B 0x80
-#define CDSN_CTRL_FR_B0 0x40
-#define CDSN_CTRL_FR_B1 0x80
-
-#define CDSN_CTRL_ECC_IO 0x20
-#define CDSN_CTRL_FLASH_IO 0x10
-#define CDSN_CTRL_WP 0x08
-#define CDSN_CTRL_ALE 0x04
-#define CDSN_CTRL_CLE 0x02
-#define CDSN_CTRL_CE 0x01
-
-#define DOC_ECC_RESET 0
-#define DOC_ECC_ERROR 0x80
-#define DOC_ECC_RW 0x20
-#define DOC_ECC__EN 0x08
-#define DOC_TOGGLE_BIT 0x04
-#define DOC_ECC_RESV 0x02
-#define DOC_ECC_IGNORE 0x01
-
-#define DOC_FLASH_CE 0x80
-#define DOC_FLASH_WP 0x40
-#define DOC_FLASH_BANK 0x02
-
-/* We have to also set the reserved bit 1 for enable */
-#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
-#define DOC_ECC_DIS (DOC_ECC_RESV)
-
-struct Nand {
- char floor, chip;
- unsigned long curadr;
- unsigned char curmode;
- /* Also some erase/write/pipeline info when we get that far */
-};
-
-#define MAX_FLOORS 4
-#define MAX_CHIPS 4
-
-#define MAX_FLOORS_MIL 1
-#define MAX_CHIPS_MIL 1
-
-#define MAX_FLOORS_MPLUS 2
-#define MAX_CHIPS_MPLUS 1
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-struct DiskOnChip {
- unsigned long physadr;
- void __iomem *virtadr;
- unsigned long totlen;
- unsigned char ChipID; /* Type of DiskOnChip */
- int ioreg;
-
- unsigned long mfr; /* Flash IDs - only one type of flash per device */
- unsigned long id;
- int chipshift;
- char page256;
- char pageadrlen;
- char interleave; /* Internal interleaving - Millennium Plus style */
- unsigned long erasesize;
-
- int curfloor;
- int curchip;
-
- int numchips;
- struct Nand *chips;
- struct mtd_info *nextdoc;
-/* XXX U-BOOT XXX */
-#if 0
- struct mutex lock;
-#endif
-};
-
-int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
-
-/* XXX U-BOOT XXX */
-#if 1
-/*
- * NAND Flash Manufacturer ID Codes
- */
-#define NAND_MFR_TOSHIBA 0x98
-#define NAND_MFR_SAMSUNG 0xec
-#endif
-
-#endif /* __MTD_DOC2000_H__ */
diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h
deleted file mode 100644
index d0558a9..0000000
--- a/include/linux/mtd/ndfc.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * linux/include/linux/mtd/ndfc.h
- *
- * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Info:
- * Contains defines, datastructures for ndfc nand controller
- *
- */
-#ifndef __LINUX_MTD_NDFC_H
-#define __LINUX_MTD_NDFC_H
-
-/* NDFC Register definitions */
-#define NDFC_CMD 0x00
-#define NDFC_ALE 0x04
-#define NDFC_DATA 0x08
-#define NDFC_ECC 0x10
-#define NDFC_BCFG0 0x30
-#define NDFC_BCFG1 0x34
-#define NDFC_BCFG2 0x38
-#define NDFC_BCFG3 0x3c
-#define NDFC_CCR 0x40
-#define NDFC_STAT 0x44
-#define NDFC_HWCTL 0x48
-#define NDFC_REVID 0x50
-
-#define NDFC_STAT_IS_READY 0x01000000
-
-#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */
-#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
-#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */
-#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */
-#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */
-#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */
-#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */
-#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */
-#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
-#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
-#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
-#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
-#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */
-#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */
-#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */
-#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */
-
-#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */
-#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */
-#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */
-#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */
-#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
-
-#define NDFC_MAX_BANKS 4
-
-struct ndfc_controller_settings {
- uint32_t ccr_settings;
- uint64_t ndfc_erpn;
-};
-
-struct ndfc_chip_settings {
- uint32_t bank_settings;
-};
-
-#endif
diff --git a/include/linux/stddef.h b/include/linux/stddef.h
index a7f546f..c732eef 100644
--- a/include/linux/stddef.h
+++ b/include/linux/stddef.h
@@ -14,13 +14,7 @@
#include <linux/types.h>
#endif
-#ifndef __CHECKER__
#undef offsetof
-#ifdef __compiler_offsetof
-#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER)
-#else
-#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER)
-#endif
-#endif
+#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER)
#endif
diff --git a/include/linux/unaligned/access_ok.h b/include/linux/unaligned/access_ok.h
deleted file mode 100644
index 5f46eee..0000000
--- a/include/linux/unaligned/access_ok.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef _LINUX_UNALIGNED_ACCESS_OK_H
-#define _LINUX_UNALIGNED_ACCESS_OK_H
-
-#include <asm/byteorder.h>
-
-static inline u16 get_unaligned_le16(const void *p)
-{
- return le16_to_cpup((__le16 *)p);
-}
-
-static inline u32 get_unaligned_le32(const void *p)
-{
- return le32_to_cpup((__le32 *)p);
-}
-
-static inline u64 get_unaligned_le64(const void *p)
-{
- return le64_to_cpup((__le64 *)p);
-}
-
-static inline u16 get_unaligned_be16(const void *p)
-{
- return be16_to_cpup((__be16 *)p);
-}
-
-static inline u32 get_unaligned_be32(const void *p)
-{
- return be32_to_cpup((__be32 *)p);
-}
-
-static inline u64 get_unaligned_be64(const void *p)
-{
- return be64_to_cpup((__be64 *)p);
-}
-
-static inline void put_unaligned_le16(u16 val, void *p)
-{
- *((__le16 *)p) = cpu_to_le16(val);
-}
-
-static inline void put_unaligned_le32(u32 val, void *p)
-{
- *((__le32 *)p) = cpu_to_le32(val);
-}
-
-static inline void put_unaligned_le64(u64 val, void *p)
-{
- *((__le64 *)p) = cpu_to_le64(val);
-}
-
-static inline void put_unaligned_be16(u16 val, void *p)
-{
- *((__be16 *)p) = cpu_to_be16(val);
-}
-
-static inline void put_unaligned_be32(u32 val, void *p)
-{
- *((__be32 *)p) = cpu_to_be32(val);
-}
-
-static inline void put_unaligned_be64(u64 val, void *p)
-{
- *((__be64 *)p) = cpu_to_be64(val);
-}
-
-#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */
diff --git a/include/linux_logo.h b/include/linux_logo.h
deleted file mode 100644
index 9aa712e..0000000
--- a/include/linux_logo.h
+++ /dev/null
@@ -1,1445 +0,0 @@
-/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $
- * include/linux/linux_logo.h: This is a linux logo
- * to be displayed on boot.
- *
- * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
- * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- *
- * You can put anything here, but:
- * LINUX_LOGO_COLORS has to be less than 224
- * image size has to be 80x80
- * values have to start from 0x20
- * (i.e. RGB(linux_logo_red[0],
- * linux_logo_green[0],
- * linux_logo_blue[0]) is color 0x20)
- * BW image has to be 80x80 as well, with MS bit
- * on the left
- * Serial_console ascii image can be any size,
- * but should contain %s to display the version
- */
-
-#if LINUX_LOGO_COLORS == 214
-
-unsigned char linux_logo_red[] __initdata = {
- 0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9,
- 0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6,
- 0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2,
- 0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54,
- 0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74,
- 0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E,
- 0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38,
- 0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3,
- 0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA,
- 0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC,
- 0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B,
- 0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52,
- 0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2,
- 0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6,
- 0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF,
- 0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46,
- 0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6,
- 0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA,
- 0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E,
- 0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7,
- 0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4,
- 0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA,
- 0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59,
- 0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB,
- 0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6,
- 0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72,
- 0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4
-};
-
-unsigned char linux_logo_green[] __initdata = {
- 0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5,
- 0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86,
- 0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96,
- 0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54,
- 0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74,
- 0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42,
- 0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24,
- 0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C,
- 0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2,
- 0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D,
- 0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E,
- 0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A,
- 0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE,
- 0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE,
- 0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB,
- 0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E,
- 0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E,
- 0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A,
- 0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62,
- 0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6,
- 0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA,
- 0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6,
- 0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45,
- 0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92,
- 0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA,
- 0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56,
- 0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE
-};
-
-unsigned char linux_logo_blue[] __initdata = {
- 0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7,
- 0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20,
- 0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40,
- 0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56,
- 0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74,
- 0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11,
- 0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A,
- 0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11,
- 0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C,
- 0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C,
- 0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E,
- 0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C,
- 0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94,
- 0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC,
- 0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91,
- 0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C,
- 0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C,
- 0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74,
- 0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04,
- 0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2,
- 0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10,
- 0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C,
- 0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E,
- 0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C,
- 0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C,
- 0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24,
- 0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7
-};
-
-unsigned char linux_logo[] __initdata = {
- 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C,
- 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95,
- 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C,
- 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6,
- 0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55,
- 0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A,
- 0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1,
- 0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95,
- 0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6,
- 0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A,
- 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95,
- 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB,
- 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C,
- 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C,
- 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C,
- 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6,
- 0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C,
- 0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55,
- 0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6,
- 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95,
- 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70,
- 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
- 0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
- 0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95,
- 0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1,
- 0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1,
- 0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55,
- 0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
- 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
- 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
- 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
- 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
- 0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88,
- 0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C,
- 0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6,
- 0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55,
- 0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
- 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
- 0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
- 0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95,
- 0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6,
- 0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55,
- 0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1,
- 0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95,
- 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
- 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
- 0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55,
- 0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6,
- 0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47,
- 0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
- 0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55,
- 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
- 0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C,
- 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
- 0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1,
- 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95,
- 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20,
- 0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1,
- 0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95,
- 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
- 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB,
- 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
- 0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43,
- 0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
- 0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1,
- 0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
- 0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90,
- 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
- 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55,
- 0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80,
- 0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
- 0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6,
- 0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95,
- 0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
- 0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70,
- 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95,
- 0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90,
- 0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20,
- 0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
- 0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
- 0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55,
- 0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55,
- 0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70,
- 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55,
- 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1,
- 0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C,
- 0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94,
- 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55,
- 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1,
- 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55,
- 0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95,
- 0xCB, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55,
- 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
- 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
- 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x70, 0x90, 0xCB,
- 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x2C, 0xD6,
- 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x70, 0x20, 0x20,
- 0x88, 0x43, 0xD8, 0x43, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x88, 0x88, 0x43, 0x2B, 0xD8, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x3F, 0x2C, 0x95, 0x95, 0xCB,
- 0x70, 0x70, 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90,
- 0x90, 0xCB, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x95,
- 0x2C, 0xD6, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
- 0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x90, 0x55,
- 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, 0x55, 0x95,
- 0x95, 0xCB, 0x90, 0x90, 0x90, 0x95, 0x2C, 0xA1,
- 0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x70, 0x20, 0x20,
- 0x80, 0x2B, 0x34, 0x2B, 0x88, 0x20, 0x20, 0x20,
- 0x88, 0xB1, 0x28, 0x28, 0x2B, 0x7D, 0x80, 0x20,
- 0x20, 0x20, 0x20, 0x92, 0x95, 0x55, 0xCB, 0x70,
- 0x90, 0x55, 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70,
- 0x55, 0x95, 0x55, 0x55, 0x90, 0x90, 0x90, 0x55,
- 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
- 0xA1, 0x95, 0x55, 0xCB, 0x90, 0x70, 0xCB, 0x95,
- 0xA1, 0x95, 0x95, 0xCB, 0x90, 0xCB, 0x95, 0x2C,
- 0x95, 0x70, 0x70, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
- 0x2C, 0x2C, 0x55, 0xCB, 0x55, 0x90, 0x20, 0x34,
- 0x90, 0x6D, 0x70, 0xD8, 0x43, 0x20, 0x20, 0x88,
- 0x3F, 0x55, 0xA1, 0x2A, 0xD6, 0x7D, 0x43, 0x20,
- 0x20, 0x20, 0x88, 0x7D, 0x55, 0xCB, 0x90, 0x70,
- 0xCB, 0x95, 0xA1, 0x95, 0x95, 0xCB, 0x70, 0xCB,
- 0x95, 0xA1, 0x95, 0x70, 0x70, 0xCB, 0x55, 0x2C,
- 0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
- 0x2C, 0x55, 0x90, 0x70, 0x94, 0x90, 0x95, 0x2C,
- 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95, 0xA1, 0xA1,
- 0x95, 0x90, 0x90, 0x95, 0xA1, 0xD6, 0xD6, 0x6D,
- 0xA1, 0x95, 0x55, 0xCB, 0x55, 0xCB, 0x20, 0x99,
- 0xBF, 0xA3, 0xA3, 0x90, 0x20, 0x20, 0x20, 0x92,
- 0x83, 0x6B, 0x6B, 0x6B, 0xA3, 0x70, 0x88, 0x20,
- 0x20, 0x20, 0x20, 0x2B, 0x90, 0x70, 0x94, 0x90,
- 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95,
- 0xA1, 0x2C, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xD6,
- 0xD6, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
- 0x2C, 0x55, 0x70, 0x70, 0x94, 0x90, 0x95, 0x2C,
- 0x2C, 0x55, 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x2C,
- 0x55, 0x55, 0x95, 0xA1, 0x6D, 0xBF, 0x6D, 0xD6,
- 0x95, 0x55, 0x90, 0xCB, 0x55, 0x95, 0x88, 0x95,
- 0x2C, 0x3F, 0x6D, 0x6B, 0x34, 0x20, 0x20, 0x47,
- 0x65, 0xD6, 0xE1, 0x3F, 0x2A, 0x6B, 0x2B, 0x20,
- 0x20, 0x20, 0x20, 0x43, 0x70, 0x70, 0x94, 0x90,
- 0x95, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x95, 0x2C,
- 0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xBF,
- 0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
- 0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
- 0x2C, 0x55, 0xCB, 0x55, 0x2C, 0x95, 0x2C, 0x95,
- 0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6, 0x95,
- 0x70, 0x94, 0x94, 0x70, 0x55, 0x55, 0x20, 0xBF,
- 0xC9, 0xB1, 0x99, 0x42, 0xB1, 0x61, 0x7D, 0x94,
- 0x65, 0xB1, 0x88, 0x99, 0xD5, 0xE5, 0x7F, 0x20,
- 0x20, 0x20, 0x20, 0x43, 0x70, 0x94, 0x70, 0x55,
- 0x2C, 0xA1, 0x2C, 0x55, 0x90, 0x55, 0x2C, 0x95,
- 0x2C, 0x95, 0x95, 0x2C, 0xA1, 0x6D, 0xBF, 0xBF,
- 0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
- 0x55, 0xCB, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xA1,
- 0x95, 0x55, 0x55, 0x95, 0x2C, 0x95, 0x95, 0x95,
- 0x95, 0xA1, 0x6D, 0x2A, 0x2A, 0xD6, 0x55, 0x94,
- 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x95, 0x20, 0x2A,
- 0xD8, 0x43, 0xC9, 0x83, 0x98, 0x79, 0x34, 0x9F,
- 0x6B, 0x43, 0x20, 0x88, 0x2B, 0x65, 0xA0, 0x20,
- 0x20, 0x20, 0x20, 0xE1, 0x70, 0x94, 0x70, 0x95,
- 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x95, 0x2C, 0x95,
- 0x95, 0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6,
- 0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
- 0x94, 0x70, 0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C,
- 0x95, 0xCB, 0x95, 0x2C, 0x2C, 0xA1, 0x2C, 0x2C,
- 0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB, 0x47, 0x28,
- 0xE6, 0x47, 0x70, 0x55, 0x95, 0xA1, 0x20, 0x2C,
- 0x7F, 0x88, 0xF0, 0xC6, 0x25, 0x5E, 0xCF, 0x2F,
- 0xE7, 0x9A, 0x20, 0x88, 0x99, 0x65, 0x3F, 0x20,
- 0x20, 0x20, 0x20, 0x34, 0x94, 0x47, 0x70, 0x95,
- 0xA1, 0x2C, 0x55, 0xCB, 0x95, 0x2C, 0x2C, 0xA1,
- 0x2C, 0x2C, 0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB,
- 0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
- 0x47, 0x70, 0x90, 0x94, 0x70, 0x95, 0xA1, 0x2C,
- 0x55, 0x55, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C,
- 0xA1, 0x6D, 0x2A, 0xD6, 0x55, 0x47, 0x28, 0x28,
- 0x47, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0x20, 0x28,
- 0xEC, 0x86, 0xBE, 0x48, 0x3E, 0x3E, 0x3A, 0x25,
- 0x4E, 0xAE, 0x93, 0xD7, 0xEC, 0xD1, 0x34, 0x20,
- 0x20, 0x20, 0x20, 0x43, 0x55, 0x94, 0x70, 0x95,
- 0xA1, 0xA1, 0x55, 0xCB, 0x2C, 0xA1, 0xA1, 0xA1,
- 0xA1, 0x2C, 0xA1, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
- 0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
- 0x95, 0x95, 0x55, 0x90, 0xCB, 0x2C, 0xA1, 0xA1,
- 0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0xA1, 0x2C,
- 0xD6, 0x6D, 0x6D, 0xA1, 0x70, 0x28, 0xD5, 0xE6,
- 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0x20, 0xE1,
- 0x26, 0x84, 0x76, 0x73, 0x9C, 0x22, 0x4E, 0x35,
- 0x8C, 0x7A, 0x4E, 0xDC, 0x8E, 0x7E, 0x3D, 0x88,
- 0x20, 0x20, 0x20, 0x88, 0x2C, 0x90, 0x90, 0x95,
- 0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xD6,
- 0x2C, 0x2C, 0xD6, 0x2A, 0x6D, 0x2C, 0x70, 0x28,
- 0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
- 0xBF, 0xA1, 0x95, 0xCB, 0xCB, 0x2C, 0xA1, 0xA1,
- 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
- 0xD6, 0x6D, 0xD6, 0x95, 0x94, 0x28, 0xE6, 0x70,
- 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xD6, 0x20, 0x57,
- 0xE4, 0xDF, 0x50, 0x3E, 0x22, 0x4E, 0x35, 0x8C,
- 0x8C, 0x52, 0x52, 0x7A, 0x4E, 0x58, 0xD7, 0x20,
- 0x20, 0x20, 0x20, 0x88, 0x2C, 0xCB, 0x55, 0x2C,
- 0xA1, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
- 0x2C, 0x95, 0xA1, 0x6D, 0x6D, 0x95, 0x47, 0xA0,
- 0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
- 0xD2, 0x95, 0x55, 0x90, 0x55, 0x2C, 0xD6, 0xA1,
- 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, 0x95, 0x2C,
- 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0x47, 0x94, 0xCB,
- 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0x59, 0xC8,
- 0xE3, 0x76, 0x2D, 0x3E, 0x22, 0x4E, 0x8C, 0x35,
- 0x52, 0x52, 0xEE, 0x3A, 0x4D, 0xED, 0x24, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x28, 0xCB, 0x55, 0x2C,
- 0xD6, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xA1, 0x2C,
- 0x95, 0x2C, 0xD6, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
- 0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
- 0xD0, 0x94, 0x94, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
- 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x2C,
- 0xA1, 0xD6, 0x2C, 0x70, 0x94, 0x94, 0x94, 0x94,
- 0x70, 0x55, 0xA1, 0xD6, 0xA1, 0xD6, 0x88, 0x77,
- 0x38, 0xC4, 0x3E, 0x69, 0x4E, 0x35, 0x8C, 0xEE,
- 0x35, 0x89, 0x30, 0x30, 0x4A, 0x48, 0x3C, 0x20,
- 0x20, 0x88, 0x20, 0x20, 0xD8, 0x2C, 0x55, 0x2C,
- 0xD6, 0xA1, 0x95, 0x95, 0x2C, 0xD6, 0xA1, 0x2C,
- 0x95, 0x2C, 0xA1, 0xD6, 0x2C, 0x90, 0x94, 0x47,
- 0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
- 0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
- 0x95, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
- 0xA1, 0xA1, 0x55, 0x70, 0x94, 0x47, 0x94, 0x94,
- 0x70, 0x2C, 0xD6, 0xD6, 0x2C, 0xA1, 0x43, 0x98,
- 0x54, 0x48, 0x3E, 0x22, 0x35, 0xEE, 0xEE, 0x9C,
- 0x4D, 0x45, 0x75, 0x4A, 0xDF, 0x7B, 0x3D, 0x20,
- 0xD8, 0x28, 0x2B, 0x88, 0x20, 0x95, 0x95, 0x2C,
- 0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
- 0x2C, 0x95, 0xA1, 0x2C, 0x55, 0x70, 0x94, 0x94,
- 0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
- 0x70, 0x28, 0x47, 0x55, 0x95, 0x2C, 0x2C, 0x2C,
- 0x95, 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0x95, 0x55,
- 0x95, 0x95, 0x55, 0x70, 0x70, 0x70, 0x94, 0x70,
- 0x55, 0xD6, 0x6D, 0xD6, 0x95, 0x2C, 0x20, 0x43,
- 0xBB, 0xC8, 0x36, 0x30, 0x30, 0x38, 0x45, 0x6E,
- 0xE3, 0x75, 0x78, 0x37, 0xBD, 0xD9, 0x3F, 0x20,
- 0x88, 0xD5, 0x70, 0xB1, 0x88, 0xA0, 0x95, 0x2C,
- 0x2C, 0xA1, 0x95, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
- 0x2C, 0x55, 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70,
- 0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
- 0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
- 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x55,
- 0x55, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95,
- 0xA1, 0x6D, 0x4B, 0xD6, 0x55, 0xD6, 0x20, 0xD8,
- 0xD6, 0x67, 0xDA, 0x4D, 0xED, 0x62, 0x78, 0x78,
- 0x23, 0x84, 0x67, 0xF5, 0x4B, 0xBF, 0x90, 0x88,
- 0x88, 0x2B, 0x47, 0x99, 0x20, 0x43, 0xD6, 0x2C,
- 0x2C, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
- 0x95, 0x95, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
- 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x95,
- 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0x6D, 0x2A, 0x2A, 0xA1, 0x55, 0x55, 0x20, 0xD8,
- 0x6D, 0xAB, 0x96, 0x7E, 0x64, 0x53, 0x36, 0x36,
- 0xC6, 0x63, 0x6D, 0xD0, 0x6B, 0xE5, 0xA3, 0x7D,
- 0x20, 0x88, 0x80, 0x88, 0x20, 0x20, 0xC9, 0xA1,
- 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1,
- 0x95, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
- 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
- 0xA1, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
- 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
- 0x6D, 0x6D, 0xA1, 0x55, 0x2C, 0xD8, 0x20, 0xB1,
- 0xA3, 0x4B, 0x6D, 0xD9, 0xA7, 0x6C, 0xAF, 0xB2,
- 0x6D, 0x2A, 0x83, 0x42, 0xE5, 0xE5, 0x65, 0x2C,
- 0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x88, 0x95,
- 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
- 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55,
- 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x2C,
- 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95,
- 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xA1,
- 0xA1, 0x2C, 0x55, 0x55, 0x28, 0x88, 0x43, 0x2A,
- 0xE5, 0xA3, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D,
- 0xBF, 0xA3, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
- 0xB1, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xD8,
- 0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C,
- 0x95, 0x95, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1,
- 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x90, 0x90, 0x55,
- 0x90, 0xCB, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95,
- 0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x55,
- 0x55, 0xCB, 0x55, 0x2C, 0x95, 0x95, 0x95, 0x95,
- 0x55, 0x90, 0x90, 0x90, 0xE1, 0x43, 0x28, 0xE5,
- 0xE5, 0x65, 0xD0, 0x6D, 0x6D, 0x6D, 0x2A, 0xD2,
- 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xD6, 0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x88,
- 0xD5, 0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95,
- 0x95, 0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x95,
- 0x95, 0x95, 0x55, 0x90, 0x70, 0x70, 0x70, 0x90,
- 0x70, 0x70, 0xCB, 0x55, 0x55, 0x95, 0x95, 0x95,
- 0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0xCB,
- 0x70, 0x70, 0x70, 0xCB, 0x90, 0x90, 0x70, 0x94,
- 0x94, 0x94, 0x2C, 0x80, 0x20, 0xE1, 0xA3, 0xE5,
- 0xE5, 0xE5, 0x42, 0xEC, 0xD0, 0x83, 0xA3, 0x65,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0x65, 0x7D, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x88, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55,
- 0x55, 0xCB, 0x70, 0x70, 0x90, 0x90, 0x90, 0x90,
- 0x70, 0x94, 0x94, 0x94, 0x70, 0x70, 0x70, 0x70,
- 0x70, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x95,
- 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0x90, 0x70, 0x90, 0x55, 0x55, 0xCB, 0x70, 0x94,
- 0x94, 0x95, 0xD8, 0x20, 0x88, 0x70, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0x47, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0xE1, 0x6D, 0x2C, 0x95, 0x55, 0x55, 0x55,
- 0x55, 0x55, 0x90, 0x70, 0x70, 0x55, 0x55, 0xCB,
- 0x70, 0x94, 0x94, 0x94, 0x70, 0x90, 0x70, 0x94,
- 0x55, 0x2C, 0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95,
- 0x2C, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x90,
- 0x55, 0x99, 0x20, 0x20, 0xE1, 0xA3, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xD6, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x2B, 0x6D, 0x95, 0x95, 0x55, 0x55,
- 0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x2C, 0x95,
- 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x90, 0x70,
- 0x2C, 0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
- 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x55, 0x95,
- 0xE6, 0x88, 0x20, 0x20, 0x3F, 0xA3, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0x42, 0xA3, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0x2B, 0xD6, 0x95, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
- 0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55,
- 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x2C,
- 0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95,
- 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0xCB, 0x94,
- 0x20, 0x20, 0x20, 0x20, 0xE6, 0x83, 0x65, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xA3, 0xD2,
- 0xD2, 0x6B, 0xC9, 0x20, 0x20, 0x88, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x88, 0x8A, 0xA1, 0x95, 0x95,
- 0x95, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0xCB,
- 0xCB, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95,
- 0x6D, 0x6D, 0x6D, 0xD6, 0xA1, 0x2C, 0x2C, 0x95,
- 0x2C, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x55, 0x70, 0x70, 0x2C, 0x80,
- 0x88, 0x20, 0x20, 0x80, 0x94, 0xD6, 0x32, 0x6B,
- 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xA3, 0xD2, 0xD0, 0xBF, 0x2A,
- 0x2A, 0xD0, 0x6D, 0x34, 0x20, 0xE1, 0x88, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x88, 0xA1, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x70, 0x70,
- 0x70, 0x90, 0xCB, 0xCB, 0xCB, 0x95, 0x95, 0x2C,
- 0xD0, 0x6D, 0xD6, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
- 0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x95,
- 0x95, 0x2C, 0x95, 0x55, 0xCB, 0xCB, 0x95, 0x88,
- 0x20, 0x20, 0x88, 0xD8, 0x2C, 0xD1, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xEC,
- 0xBF, 0x2A, 0xEC, 0x95, 0x20, 0x34, 0x2B, 0xE1,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x99, 0x95, 0x55,
- 0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB,
- 0x55, 0x55, 0xCB, 0xCB, 0xCB, 0x55, 0x95, 0x95,
- 0x32, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
- 0xA1, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB, 0x55,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x99, 0x20,
- 0xE1, 0xE1, 0x43, 0x47, 0x6B, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0x42, 0xEC, 0xBF, 0xA3, 0x8A, 0x20, 0x88, 0xD8,
- 0x2B, 0x20, 0x20, 0x20, 0x88, 0x88, 0x2C, 0xCB,
- 0xCB, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95,
- 0x55, 0x55, 0x55, 0x55, 0x55, 0x95, 0x55, 0x95,
- 0x6D, 0x55, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x95,
- 0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x34, 0x20,
- 0xC9, 0x20, 0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xA3, 0x83, 0x6D, 0x20, 0x88, 0x88,
- 0x2B, 0x34, 0x20, 0x20, 0x20, 0x88, 0xD5, 0x55,
- 0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95, 0x95,
- 0x2C, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x55, 0x95,
- 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x2C, 0x95, 0x95, 0x55, 0x95, 0x2C, 0x20, 0xD8,
- 0xE1, 0x20, 0x70, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x65, 0xA3, 0x92, 0x43, 0x7D,
- 0xD8, 0xC9, 0x88, 0x20, 0x20, 0x20, 0x43, 0xD6,
- 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x95, 0x2C,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C,
- 0xA1, 0x55, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55,
- 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C,
- 0xA1, 0x2C, 0x2C, 0x95, 0x2C, 0x99, 0x88, 0xB1,
- 0x20, 0xD8, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x34, 0x8A,
- 0xC9, 0x34, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x90,
- 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x95, 0x2C,
- 0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0xD6, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C,
- 0x55, 0xCB, 0x55, 0x2C, 0x2C, 0xA1, 0x2C, 0xA1,
- 0xA1, 0xA1, 0x2C, 0x2C, 0x6D, 0x43, 0xD8, 0x80,
- 0x88, 0xCB, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x32, 0x80, 0xE1,
- 0x80, 0x20, 0xB1, 0x20, 0x20, 0x20, 0x20, 0xC9,
- 0xD6, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1, 0x2C, 0x2C,
- 0x2C, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
- 0xD6, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x2C,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C,
- 0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0x20, 0xC9, 0x20,
- 0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xD8, 0x20,
- 0x20, 0x20, 0x2B, 0x43, 0x20, 0x20, 0x20, 0x88,
- 0xD6, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55,
- 0x95, 0x55, 0x55, 0xCB, 0x55, 0xCB, 0xCB, 0x55,
- 0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0x95,
- 0x55, 0x95, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95,
- 0x55, 0xCB, 0x70, 0xCB, 0xC9, 0x80, 0x2B, 0x20,
- 0xA0, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x92, 0x20,
- 0x20, 0x20, 0xE1, 0xD8, 0x20, 0x20, 0x20, 0x20,
- 0x95, 0x95, 0x55, 0xCB, 0x90, 0x90, 0x70, 0x90,
- 0x90, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55, 0x95,
- 0x95, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55,
- 0x90, 0x47, 0xA0, 0x55, 0x20, 0x2B, 0x43, 0x88,
- 0x6D, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x28, 0x20,
- 0x20, 0x20, 0xE1, 0xE1, 0x20, 0x20, 0x20, 0x20,
- 0x28, 0x55, 0x90, 0x47, 0xA0, 0x47, 0x94, 0x70,
- 0x55, 0x95, 0x95, 0x55, 0xCB, 0x55, 0x55, 0x2C,
- 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55,
- 0x94, 0xE6, 0x70, 0x2B, 0x88, 0x2B, 0x88, 0xE1,
- 0x65, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x47, 0x20,
- 0x20, 0x20, 0xE1, 0x34, 0x20, 0x20, 0x20, 0x20,
- 0xB1, 0x95, 0x94, 0xE6, 0xA0, 0x47, 0x70, 0x55,
- 0x2C, 0xA1, 0x2C, 0x55, 0x90, 0xCB, 0x2C, 0xD6,
- 0x6D, 0xA1, 0x2C, 0x95, 0x95, 0xA1, 0x2C, 0xA1,
- 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55,
- 0x70, 0xE6, 0x70, 0x20, 0x20, 0x7D, 0x20, 0x8A,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x65, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x94, 0x20,
- 0x20, 0x20, 0xD8, 0x88, 0x20, 0x20, 0x20, 0x20,
- 0xD8, 0x2C, 0x94, 0x47, 0x47, 0x90, 0x95, 0x95,
- 0xA1, 0x6D, 0xA1, 0x90, 0x94, 0x55, 0x2C, 0xD6,
- 0xD0, 0xA1, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C,
- 0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C,
- 0xCB, 0x95, 0xD8, 0x20, 0x20, 0xB1, 0x88, 0x28,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE2, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20,
- 0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x88, 0xD6, 0x55, 0x47, 0x94, 0x55, 0x2C, 0xA1,
- 0xA1, 0xD6, 0x95, 0x94, 0x94, 0x55, 0xD6, 0x6D,
- 0xBF, 0x95, 0x90, 0xCB, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x55, 0x95, 0xCB, 0x90, 0x90, 0x95, 0x2C, 0x95,
- 0x90, 0x70, 0x20, 0x20, 0x34, 0x8A, 0x20, 0x94,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20,
- 0x20, 0x88, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x88, 0xD6, 0xCB, 0x47, 0x94, 0x55, 0xA1, 0xD6,
- 0xD6, 0x2C, 0xCB, 0x47, 0x70, 0xA1, 0x6D, 0x2A,
- 0x95, 0x47, 0x47, 0x70, 0x95, 0xA1, 0x2C, 0x95,
- 0x55, 0x55, 0x90, 0x90, 0x55, 0x55, 0x55, 0x90,
- 0x47, 0xD5, 0x20, 0x20, 0x80, 0xD5, 0x43, 0xCB,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20,
- 0x20, 0x80, 0x34, 0x20, 0x20, 0x20, 0x88, 0x20,
- 0x20, 0x2C, 0x47, 0xE6, 0x70, 0x2C, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xD6,
- 0x90, 0x47, 0x47, 0x90, 0x2C, 0xA1, 0x2C, 0x95,
- 0x55, 0x55, 0x90, 0x90, 0x55, 0x55, 0x55, 0x70,
- 0x94, 0x8A, 0x20, 0x88, 0x88, 0xE1, 0xD8, 0x95,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE2, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x47, 0x20,
- 0x43, 0x7D, 0x43, 0x80, 0x88, 0x20, 0x20, 0x20,
- 0x88, 0xCB, 0x94, 0x70, 0x55, 0xA1, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x2C, 0x95, 0xA1, 0xA1, 0xD6, 0xA1,
- 0x94, 0xE6, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
- 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
- 0x55, 0xA0, 0x43, 0x86, 0x86, 0x43, 0xD8, 0xCB,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x3F, 0x80,
- 0xD8, 0x80, 0x88, 0x34, 0xD8, 0x2B, 0xD8, 0x20,
- 0x99, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
- 0xA1, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
- 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0x95, 0x44, 0xBC, 0x3E, 0x5D, 0xD3, 0x79, 0x92,
- 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x65, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x9A, 0x34,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x99, 0xE1,
- 0x70, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1,
- 0x2C, 0x95, 0x55, 0x55, 0x95, 0x95, 0x95, 0x95,
- 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
- 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
- 0x32, 0x9D, 0xEB, 0x5D, 0x69, 0x49, 0x84, 0xF0,
- 0xB1, 0xEC, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xC1, 0x4E, 0x21, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0xC9, 0xD8,
- 0xBB, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
- 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C,
- 0x55, 0xCB, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
- 0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0x6D, 0xD0,
- 0xC2, 0x48, 0x6A, 0x49, 0x69, 0x82, 0x5D, 0x2F,
- 0x59, 0x7D, 0xBF, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xEA, 0xC7, 0x7E, 0x66,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0x43, 0x5A,
- 0x46, 0x27, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
- 0x95, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0x55,
- 0x94, 0x94, 0x2C, 0x2A, 0x72, 0x3B, 0x56, 0xDD,
- 0xDF, 0x29, 0x5D, 0x49, 0x89, 0x5D, 0x3E, 0x69,
- 0x93, 0x66, 0x34, 0xA1, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x65, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xEA, 0x3E, 0x5A, 0x66,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x66, 0x5B, 0x73,
- 0x89, 0x4C, 0xBF, 0x2C, 0x95, 0x2C, 0x2C, 0x95,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
- 0x2C, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0xCB,
- 0x70, 0x55, 0xE7, 0x60, 0x4A, 0x48, 0xCD, 0x4A,
- 0x29, 0x73, 0x5D, 0x82, 0x49, 0x49, 0x49, 0x49,
- 0x3A, 0x57, 0x88, 0x88, 0x70, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x42, 0x73, 0x50, 0xBE, 0x79,
- 0x20, 0x20, 0x20, 0x20, 0x66, 0xCC, 0x37, 0x9C,
- 0x3E, 0xCE, 0xBF, 0x95, 0x95, 0x95, 0x2C, 0x95,
- 0x95, 0x55, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
- 0xA1, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x94,
- 0x94, 0xE8, 0x60, 0xC4, 0x3E, 0x2D, 0x2D, 0x2D,
- 0x33, 0x5D, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x89, 0xAA, 0x59, 0x20, 0x20, 0x28, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xEC, 0x4A, 0x2D, 0x50, 0x78, 0x2E,
- 0x57, 0x51, 0xF0, 0x57, 0x31, 0x4D, 0x50, 0x2D,
- 0x5D, 0xF2, 0xA1, 0x2C, 0x95, 0x95, 0x55, 0x55,
- 0x90, 0x90, 0x70, 0x90, 0xCB, 0x55, 0x55, 0x55,
- 0x6D, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x55, 0x94,
- 0x70, 0xB9, 0x75, 0x50, 0x3E, 0x49, 0x49, 0x49,
- 0x5D, 0x82, 0x49, 0x49, 0x82, 0x49, 0x49, 0x49,
- 0x89, 0x69, 0x4F, 0x20, 0x20, 0x20, 0x8A, 0x42,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x83, 0x4A, 0x3A, 0x50, 0x62, 0x23,
- 0x81, 0xB8, 0xB8, 0xE9, 0x5F, 0x29, 0x33, 0x5D,
- 0x5D, 0x73, 0xE8, 0xCB, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x70,
- 0xCB, 0x68, 0x75, 0x50, 0x82, 0x49, 0x49, 0x49,
- 0x5D, 0x49, 0x49, 0x5D, 0x49, 0x49, 0x5D, 0x82,
- 0x69, 0x5D, 0x25, 0xF0, 0x20, 0x20, 0x20, 0xE1,
- 0x2A, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0x4B, 0xF4, 0xDF, 0x50, 0x73, 0x76, 0x48,
- 0x75, 0xDF, 0x75, 0x62, 0xC4, 0x33, 0x82, 0x49,
- 0x5D, 0x5D, 0xA8, 0xF5, 0x55, 0x55, 0x55, 0x55,
- 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
- 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
- 0x95, 0x83, 0x5F, 0xEA, 0x2D, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x5D, 0x49, 0x22, 0x5A, 0x79, 0x20, 0x20, 0x20,
- 0x80, 0xD2, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0x65, 0xD0, 0x63, 0x5F, 0x29, 0x2D, 0x2D, 0xEA,
- 0x29, 0x29, 0x76, 0x50, 0x2D, 0x82, 0x49, 0x49,
- 0x3E, 0x49, 0x5C, 0xB0, 0xBA, 0x95, 0x55, 0x55,
- 0x2C, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
- 0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x70, 0x55,
- 0x2C, 0x83, 0x60, 0x76, 0x5D, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x5D, 0x89, 0xDC, 0x8B, 0x20, 0x20, 0x20,
- 0x20, 0x95, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE2, 0x32, 0x85, 0xE3, 0x29, 0x2D, 0x33, 0x2D,
- 0x2D, 0x2D, 0x6A, 0x2D, 0x33, 0x5D, 0x49, 0x82,
- 0x49, 0x49, 0x82, 0x73, 0x5C, 0x9E, 0x2C, 0x55,
- 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
- 0x2C, 0x95, 0x55, 0xCB, 0x90, 0x90, 0xCB, 0x95,
- 0x2C, 0x6D, 0x41, 0x6F, 0x3E, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x82, 0x3E, 0x4E, 0x38, 0xCA, 0x20, 0x20,
- 0x20, 0x55, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
- 0x42, 0xA0, 0xD4, 0xE3, 0x29, 0x2D, 0x82, 0x5D,
- 0x5D, 0x82, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x3E, 0x49, 0x49, 0x49, 0x5C, 0x56, 0xD6,
- 0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
- 0xA1, 0x55, 0x90, 0x70, 0x94, 0x70, 0x95, 0x2C,
- 0x2C, 0xD6, 0xDD, 0x6F, 0x33, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x5D, 0x5D, 0x82, 0x69, 0x22, 0x62, 0x80, 0x34,
- 0x94, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0x65, 0x6B,
- 0xD5, 0x88, 0x5B, 0xE3, 0x29, 0x5D, 0x5D, 0x5D,
- 0x5D, 0x5D, 0x5D, 0x5D, 0x49, 0x49, 0x49, 0x82,
- 0x49, 0x49, 0x89, 0x49, 0x82, 0x49, 0x71, 0xBA,
- 0x6D, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
- 0x2C, 0x55, 0x70, 0x70, 0x70, 0x90, 0x95, 0xA1,
- 0x2C, 0xA1, 0x41, 0x76, 0x5D, 0x5D, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x5D, 0x82, 0x5D, 0x89, 0x5E, 0x96, 0x65,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xEC, 0xB1,
- 0x20, 0x20, 0xCA, 0x23, 0x29, 0x33, 0x49, 0x5D,
- 0x49, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, 0x82,
- 0x49, 0x82, 0x5D, 0x5D, 0x5D, 0x2D, 0x5C, 0x8F,
- 0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
- 0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
- 0x95, 0xE8, 0x5F, 0x76, 0x33, 0x5D, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x3E, 0x9C, 0x2F, 0x68,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0x65, 0xE5, 0x65, 0xE5, 0x6B, 0x90, 0x80, 0x20,
- 0x20, 0x20, 0x4F, 0x81, 0x50, 0x3E, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x69, 0x69, 0x49, 0x5D, 0x2D, 0xC4, 0x46, 0xA3,
- 0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
- 0x55, 0xCB, 0x70, 0x47, 0x70, 0x95, 0xA1, 0xA1,
- 0x95, 0xBD, 0x75, 0x2D, 0x33, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x5D, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x5D, 0x2D, 0xB5, 0xDB,
- 0xD6, 0x65, 0xE5, 0x65, 0xE5, 0xE5, 0x65, 0xE5,
- 0x65, 0x65, 0x6B, 0x95, 0x2B, 0x88, 0x20, 0x20,
- 0x20, 0x20, 0x8B, 0x81, 0x29, 0x33, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x3E, 0x3E, 0x5E, 0x41, 0x97, 0x27, 0xD6,
- 0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
- 0x94, 0x70, 0x94, 0x94, 0x70, 0x55, 0xA1, 0x2C,
- 0x6D, 0xC5, 0x39, 0x6A, 0x5D, 0x5D, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x3E, 0xEA, 0x30, 0x77,
- 0xE1, 0xC9, 0x94, 0x2C, 0xD6, 0xD6, 0xA1, 0x55,
- 0x47, 0x9F, 0x43, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x80, 0x91, 0x81, 0x6A, 0x2D, 0x49, 0x49,
- 0x49, 0x5D, 0x5D, 0x49, 0x49, 0x5D, 0x5D, 0x82,
- 0xEB, 0x4A, 0x41, 0xC2, 0x8F, 0xF5, 0xA1, 0x55,
- 0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
- 0x47, 0x70, 0x70, 0x94, 0x90, 0x95, 0xA1, 0x2C,
- 0xE8, 0xA6, 0x39, 0x76, 0x50, 0x50, 0x2D, 0x2D,
- 0x3E, 0x3E, 0x5D, 0x3E, 0x5D, 0x5D, 0x49, 0x82,
- 0x49, 0x49, 0x49, 0x82, 0x82, 0x50, 0x75, 0xE0,
- 0x57, 0x20, 0x88, 0x88, 0x20, 0x20, 0x88, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x79, 0x91, 0x81, 0x76, 0x33, 0x49, 0x49,
- 0x5D, 0x82, 0x49, 0x49, 0x3E, 0x6A, 0xEA, 0x29,
- 0xDF, 0x97, 0xBF, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
- 0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
- 0x95, 0x95, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xA1,
- 0xD6, 0x26, 0x45, 0x81, 0x5F, 0x30, 0x48, 0x6F,
- 0x6F, 0x29, 0x29, 0x6A, 0x2D, 0x2D, 0x5D, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x2D, 0x76, 0x6E, 0x77,
- 0x5B, 0x66, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x79, 0xA9, 0xB8, 0x39, 0x50, 0x5D, 0x5D,
- 0x5D, 0x5D, 0x3E, 0x2D, 0x29, 0x76, 0xCD, 0x37,
- 0xB9, 0xA1, 0xA1, 0x6D, 0x6D, 0x2C, 0x94, 0x28,
- 0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
- 0xBF, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0xA1, 0x2C,
- 0x95, 0x83, 0xDE, 0x87, 0xB6, 0xBE, 0x40, 0x6E,
- 0x81, 0x81, 0x78, 0x78, 0x39, 0x6F, 0xEA, 0x2D,
- 0x2D, 0x33, 0x33, 0x33, 0x76, 0x30, 0x64, 0x54,
- 0x5B, 0x66, 0x20, 0x20, 0x66, 0x20, 0x88, 0x20,
- 0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x88, 0x34, 0x8B, 0xF1, 0x23, 0x6F, 0x50, 0x2D,
- 0x2D, 0x6A, 0x29, 0x6F, 0x78, 0x84, 0x9B, 0xD2,
- 0x2C, 0x2C, 0xD6, 0x6D, 0x6D, 0x2C, 0x47, 0xA0,
- 0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
- 0xD2, 0x95, 0x55, 0xCB, 0x55, 0x2C, 0xD6, 0xA1,
- 0x95, 0x95, 0xA1, 0xD6, 0x6D, 0x6D, 0xBA, 0xF3,
- 0x8D, 0x36, 0x74, 0x36, 0xF1, 0xB8, 0x23, 0x78,
- 0x62, 0x4A, 0x29, 0x62, 0x23, 0xF1, 0x54, 0x31,
- 0x57, 0x2B, 0x90, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, 0xCB,
- 0xE6, 0x7D, 0xCA, 0xB7, 0xB8, 0x75, 0x6F, 0x6F,
- 0x76, 0x6F, 0x78, 0x81, 0x53, 0xBD, 0x6D, 0x2C,
- 0x95, 0x95, 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
- 0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
- 0xD0, 0x94, 0x94, 0x90, 0x95, 0x2C, 0xD6, 0xA1,
- 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x2C,
- 0xD6, 0x68, 0xAB, 0x6C, 0xA4, 0x77, 0x77, 0xAD,
- 0x40, 0x53, 0x6E, 0x40, 0xB7, 0x54, 0x31, 0xD7,
- 0xAC, 0xD6, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
- 0x95, 0x2C, 0x2C, 0xA1, 0x95, 0x95, 0x2C, 0xA1,
- 0x6D, 0xD2, 0x7C, 0x54, 0xAD, 0x40, 0x6E, 0x81,
- 0x81, 0x6E, 0x36, 0xDA, 0xE8, 0xD6, 0xD6, 0x2C,
- 0x2C, 0x2C, 0xA1, 0xD6, 0x95, 0x90, 0x94, 0x47,
- 0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
- 0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
- 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4,
- 0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A,
- 0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
- 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6,
- 0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD,
- 0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1,
- 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94,
- 0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
- 0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1,
- 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95,
- 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C,
- 0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C,
- 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95,
- 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF,
- 0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1,
- 0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70,
- 0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
- 0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
- 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55,
- 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95,
- 0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95,
- 0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95,
- 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1,
- 0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D,
- 0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
- 0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
- 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
- 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95,
- 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95,
- 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
- 0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C,
- 0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
- 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95,
- 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
- 0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55,
- 0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95,
- 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1,
- 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C,
- 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
- 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55
-};
-
-#endif
-
-#ifdef INCLUDE_LINUX_LOGOBW
-
-unsigned char linux_logo_bw[] __initdata = {
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F,
- 0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
- 0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF,
- 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7,
- 0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0,
- 0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80,
- 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4,
- 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C,
- 0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F,
- 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00,
- 0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF,
- 0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF,
- 0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19,
- 0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E,
- 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00,
- 0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC,
- 0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF,
- 0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11,
- 0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06,
- 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00,
- 0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1,
- 0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF,
- 0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10,
- 0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00,
- 0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00,
- 0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7,
- 0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
- 0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8,
- 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01,
- 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00,
- 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F,
- 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
- 0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18,
- 0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03,
- 0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00,
- 0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF,
- 0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01,
- 0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00,
- 0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00,
- 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40,
- 0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF,
- 0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23,
- 0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00,
- 0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80,
- 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00,
- 0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF,
- 0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04,
- 0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10,
- 0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80,
- 0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00,
- 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00,
- 0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0,
- 0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40,
- 0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00,
- 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF,
- 0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40,
- 0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0,
- 0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF,
- 0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F,
- 0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF,
- 0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F,
- 0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F,
- 0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07,
- 0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-};
-
-#endif
-
-#ifdef INCLUDE_LINUX_LOGO16
-
-unsigned char linux_logo16_red[] __initdata = {
- 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5,
- 0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8
-};
-
-unsigned char linux_logo16_green[] __initdata = {
- 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5,
- 0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8
-};
-
-unsigned char linux_logo16_blue[] __initdata = {
- 0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5,
- 0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8
-};
-
-unsigned char linux_logo16[] __initdata = {
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11,
- 0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77,
- 0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
- 0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77,
- 0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa,
- 0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73,
- 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3,
- 0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11,
- 0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77,
- 0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
- 0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66,
- 0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22,
- 0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
- 0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22,
- 0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33,
- 0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33,
- 0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37,
- 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33,
- 0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22,
- 0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a,
- 0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a,
- 0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00,
- 0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72,
- 0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61,
- 0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa,
- 0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00,
- 0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77,
- 0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66,
- 0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1,
- 0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00,
- 0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66,
- 0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa,
- 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11,
- 0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00,
- 0x54, 0x48, 0x54, 0x40, 0x00, 0x00, 0x01, 0xaa,
- 0x32, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x31,
- 0x66, 0x66, 0x11, 0x37, 0x22, 0x27, 0x73, 0x3a,
- 0xaa, 0xaa, 0xa3, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
- 0xa3, 0x77, 0xaa, 0x10, 0x50, 0x08, 0x46, 0x05,
- 0x54, 0x80, 0x50, 0x42, 0x00, 0x00, 0x08, 0x66,
- 0x66, 0x1a, 0x32, 0x22, 0x22, 0x22, 0x22, 0x27,
- 0x31, 0x66, 0x66, 0x13, 0x72, 0x22, 0x77, 0x33,
- 0xaa, 0xaa, 0xaa, 0x33, 0xaa, 0xa1, 0xaa, 0xa3,
- 0x37, 0xa1, 0x1a, 0x30, 0x50, 0x06, 0x26, 0x00,
- 0x54, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0xe2,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, 0x22,
- 0x27, 0xa6, 0x66, 0x61, 0xa7, 0x72, 0x27, 0x73,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
- 0x31, 0x11, 0x37, 0x70, 0x02, 0x00, 0xab, 0xbb,
- 0xb6, 0x00, 0x00, 0xf4, 0x00, 0x00, 0xee, 0xee,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
- 0x22, 0x23, 0x16, 0x66, 0x1a, 0x37, 0x22, 0x77,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a,
- 0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd,
- 0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
- 0x22, 0x22, 0x71, 0x66, 0x66, 0x13, 0x72, 0x27,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x11,
- 0xa3, 0x73, 0xa1, 0x60, 0x08, 0xbd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdb, 0x90, 0x00, 0x02, 0xec, 0xee,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xce, 0x22,
- 0x22, 0x22, 0x27, 0xa6, 0x66, 0x61, 0x37, 0x27,
- 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x1a,
- 0x33, 0xa1, 0x16, 0x60, 0x0b, 0xbd, 0xdd, 0xdd,
- 0xcd, 0xdd, 0xdd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xce, 0xa2,
- 0x22, 0x22, 0x22, 0x7a, 0x66, 0x66, 0x13, 0x77,
- 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0x3a, 0x11, 0x33,
- 0xaa, 0x11, 0x66, 0x60, 0x9b, 0xdd, 0xdd, 0xdd,
- 0xcd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0xec, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x61,
- 0x72, 0x22, 0x22, 0x22, 0xa1, 0x66, 0x61, 0x37,
- 0x1a, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x13, 0x3a,
- 0x11, 0x11, 0x11, 0x10, 0x5b, 0xdd, 0xdd, 0xdc,
- 0xdd, 0xdd, 0xbd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x86,
- 0x17, 0x22, 0x22, 0x22, 0x23, 0x16, 0x66, 0xaa,
- 0xaa, 0xa3, 0x3a, 0xaa, 0xaa, 0x1a, 0x3a, 0xa1,
- 0x11, 0x11, 0x1a, 0x70, 0x05, 0xbd, 0xdd, 0xdd,
- 0xdb, 0x5b, 0xdd, 0xb0, 0x00, 0x60, 0x2e, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe6, 0x88,
- 0x66, 0x32, 0x22, 0x22, 0x22, 0x36, 0x66, 0x11,
- 0x33, 0x33, 0x3a, 0xaa, 0x11, 0xaa, 0xaa, 0xa1,
- 0x11, 0x1a, 0x3a, 0x60, 0x02, 0x99, 0xbb, 0xb9,
- 0x9b, 0xbb, 0xbc, 0x22, 0x00, 0x86, 0x5e, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe1, 0x68,
- 0x86, 0x63, 0x22, 0x22, 0x22, 0x2a, 0x66, 0x66,
- 0x33, 0x33, 0xaa, 0xaa, 0x1a, 0xaa, 0xaa, 0x11,
- 0x1a, 0xa7, 0x68, 0x80, 0x02, 0x2b, 0xbd, 0xbb,
- 0xbb, 0xb9, 0x22, 0x22, 0x00, 0x06, 0x6e, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc7, 0xa6,
- 0x88, 0x86, 0x32, 0x22, 0x22, 0x27, 0xa6, 0x66,
- 0x33, 0x3a, 0xaa, 0xa1, 0xaa, 0xaa, 0xa1, 0x11,
- 0xa3, 0xa6, 0x88, 0x80, 0x02, 0x22, 0x9b, 0xbb,
- 0xbb, 0x22, 0x24, 0xf4, 0x60, 0x00, 0x0c, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc2, 0x21,
- 0x68, 0x88, 0x63, 0x22, 0x22, 0x22, 0x71, 0x66,
- 0x33, 0x3a, 0x11, 0x11, 0xaa, 0xaa, 0x11, 0xaa,
- 0x71, 0x88, 0x88, 0x00, 0x02, 0xe2, 0x26, 0x99,
- 0x22, 0x22, 0x4f, 0xf4, 0x40, 0x00, 0x0c, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x22, 0x22,
- 0x16, 0x88, 0x86, 0xa2, 0x22, 0x22, 0x27, 0x11,
- 0x33, 0xa1, 0x11, 0x11, 0xaa, 0x31, 0x1a, 0xa3,
- 0x68, 0x88, 0x81, 0x00, 0x54, 0x42, 0x22, 0x22,
- 0x22, 0x44, 0xff, 0xff, 0x48, 0x00, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x22,
- 0x21, 0x88, 0x88, 0x6a, 0x22, 0x22, 0x22, 0x31,
- 0x3a, 0xa1, 0x11, 0x1a, 0xa3, 0x11, 0x33, 0x36,
- 0x88, 0x86, 0x30, 0x00, 0x4f, 0x44, 0x22, 0x22,
- 0x24, 0xff, 0xff, 0xff, 0x44, 0x00, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x95, 0x22, 0x72,
- 0x22, 0x18, 0x88, 0x86, 0x32, 0x22, 0x22, 0x27,
- 0xaa, 0x11, 0x11, 0x1a, 0x31, 0x13, 0x33, 0x68,
- 0x88, 0x6a, 0x00, 0x02, 0x4f, 0x4f, 0x42, 0x24,
- 0x4f, 0xff, 0xff, 0xff, 0xf4, 0x50, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x73,
- 0x72, 0x26, 0x88, 0x88, 0x63, 0x22, 0x22, 0x22,
- 0x11, 0x11, 0x11, 0xa3, 0xa1, 0x73, 0xa6, 0x88,
- 0x81, 0xa5, 0x00, 0x04, 0x4f, 0x4f, 0x44, 0x4f,
- 0xff, 0xff, 0xff, 0xff, 0xf4, 0x40, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x12, 0x27,
- 0xaa, 0x22, 0x68, 0x55, 0x86, 0x72, 0x22, 0x22,
- 0x11, 0x11, 0x1a, 0x33, 0x13, 0x3a, 0x18, 0x88,
- 0x1a, 0x10, 0x00, 0x44, 0x4f, 0x4f, 0xff, 0x4f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x61, 0x22,
- 0x3a, 0xa2, 0x26, 0x85, 0x58, 0x67, 0x22, 0x22,
- 0x61, 0x61, 0x1a, 0x7a, 0x37, 0x31, 0x88, 0x81,
- 0x11, 0x00, 0x05, 0xe4, 0x44, 0xff, 0xff, 0xff,
- 0x4f, 0xf4, 0x44, 0xff, 0xff, 0xf5, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x12,
- 0x2a, 0xaa, 0x72, 0x68, 0x55, 0x81, 0x22, 0x22,
- 0x66, 0x61, 0xa3, 0x33, 0x73, 0x16, 0x88, 0x11,
- 0x10, 0x00, 0x08, 0x74, 0x44, 0x4f, 0x44, 0x44,
- 0xf4, 0xf4, 0x44, 0x44, 0xe2, 0x44, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x81,
- 0x22, 0xaa, 0xa7, 0x26, 0x85, 0x88, 0x12, 0x22,
- 0x66, 0x61, 0x37, 0xa7, 0x3a, 0x66, 0x66, 0x11,
- 0x80, 0x00, 0x0a, 0x72, 0x44, 0x4f, 0x44, 0x4f,
- 0xff, 0x44, 0x44, 0x22, 0x22, 0x24, 0x00, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x85, 0x88,
- 0x12, 0x2a, 0xaa, 0x22, 0x68, 0x58, 0x63, 0x22,
- 0x66, 0x1a, 0x73, 0x77, 0x31, 0x66, 0x61, 0x11,
- 0x00, 0x00, 0x07, 0x44, 0xff, 0x4f, 0xf4, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0x42, 0x22, 0x40, 0x9b,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x85, 0x55,
- 0x81, 0x27, 0xaa, 0xa2, 0x78, 0x88, 0x86, 0x72,
- 0x66, 0x13, 0x77, 0x73, 0x11, 0x66, 0x61, 0x76,
- 0x00, 0x50, 0x84, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x42, 0x40, 0x9b,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x68, 0x55,
- 0x58, 0x12, 0x3a, 0xaa, 0x23, 0x88, 0x88, 0xa7,
- 0x66, 0xa7, 0x77, 0x7a, 0x16, 0x66, 0x1a, 0x15,
- 0x05, 0x00, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0x24, 0x9b,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x26, 0x55,
- 0x55, 0x81, 0x23, 0xaa, 0x32, 0x18, 0x88, 0x6a,
- 0x61, 0x37, 0x77, 0x31, 0x66, 0x66, 0x17, 0x60,
- 0x05, 0x08, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4e, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0xa2, 0x65,
- 0x55, 0x58, 0xa2, 0x7a, 0xa2, 0x26, 0x88, 0x61,
- 0x61, 0x32, 0x27, 0xa1, 0x66, 0x61, 0x31, 0x60,
- 0x00, 0x04, 0x4f, 0xf4, 0xff, 0x44, 0x44, 0xff,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99,
- 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x9b, 0xaa, 0x26,
- 0x55, 0x55, 0x87, 0x27, 0x33, 0x27, 0x68, 0x61,
- 0x1a, 0x72, 0x27, 0xa6, 0x66, 0x6a, 0x71, 0x00,
- 0x80, 0x84, 0xff, 0xf4, 0xff, 0x44, 0x44, 0xff,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99,
- 0x9b, 0x9b, 0x99, 0xb9, 0xb9, 0x99, 0xaa, 0xa2,
- 0x85, 0x55, 0x56, 0x22, 0x27, 0x22, 0x36, 0x66,
- 0x13, 0x22, 0x23, 0x16, 0x86, 0x63, 0x73, 0x00,
- 0x00, 0x44, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4f, 0x99,
- 0x9b, 0x99, 0x99, 0x99, 0xb9, 0x99, 0xaa, 0xaa,
- 0x28, 0x55, 0x58, 0x12, 0x22, 0x22, 0x21, 0x11,
- 0xa3, 0x27, 0x7a, 0x66, 0x86, 0x17, 0x75, 0x05,
- 0x05, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff,
- 0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x44, 0x4f, 0x99,
- 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x3a, 0xaa,
- 0xa2, 0x85, 0x58, 0x67, 0x72, 0x22, 0x27, 0xa1,
- 0x37, 0x27, 0x7a, 0x68, 0x86, 0xa2, 0x70, 0x00,
- 0x02, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xf4, 0x99,
- 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x23, 0xaa,
- 0xa7, 0x78, 0x88, 0x81, 0x77, 0x22, 0x27, 0x3a,
- 0x72, 0x73, 0x71, 0x68, 0x66, 0x32, 0x50, 0x00,
- 0x04, 0x4f, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x95,
- 0x99, 0x99, 0x99, 0x99, 0x99, 0x55, 0x12, 0x3a,
- 0xaa, 0x21, 0x88, 0x81, 0x77, 0x27, 0x73, 0x73,
- 0x72, 0x33, 0x36, 0x86, 0x61, 0x72, 0x00, 0x00,
- 0x04, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0x55,
- 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x8a, 0x27,
- 0xaa, 0x77, 0x68, 0x61, 0x23, 0x71, 0x11, 0x3a,
- 0x27, 0xa3, 0x36, 0x86, 0x61, 0x20, 0x00, 0x00,
- 0x04, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x59,
- 0x99, 0x99, 0x99, 0x99, 0x99, 0x95, 0x58, 0x77,
- 0x27, 0x32, 0x36, 0x63, 0x23, 0x71, 0x66, 0x11,
- 0x27, 0x13, 0xa6, 0x86, 0x6a, 0x20, 0x00, 0x50,
- 0x04, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x99,
- 0x9b, 0xbb, 0xbb, 0xbb, 0xb9, 0x99, 0x68, 0x13,
- 0x32, 0x22, 0x73, 0xa7, 0x2a, 0x31, 0x88, 0x66,
- 0x7a, 0x13, 0x18, 0x66, 0x63, 0x20, 0x00, 0x06,
- 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x49, 0x95,
- 0xa9, 0xa9, 0x99, 0x97, 0x92, 0x99, 0x65, 0x6a,
- 0x17, 0x22, 0x23, 0x72, 0x27, 0xaa, 0x88, 0x88,
- 0xa1, 0x17, 0x68, 0x66, 0x67, 0x70, 0x00, 0x05,
- 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x49, 0x9c,
- 0x2e, 0xee, 0xee, 0xee, 0xee, 0xa9, 0x65, 0x8a,
- 0x1a, 0xaa, 0x37, 0x72, 0x27, 0x37, 0x88, 0x88,
- 0x11, 0x17, 0x68, 0x66, 0x67, 0x10, 0x9d, 0xd0,
- 0x84, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0xf4, 0x4f,
- 0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x4f, 0x69,
- 0xcc, 0xee, 0xee, 0xee, 0xec, 0x99, 0x88, 0x63,
- 0x61, 0x68, 0x61, 0x72, 0x22, 0x7a, 0x68, 0x88,
- 0x11, 0x17, 0x88, 0x66, 0x12, 0x1b, 0xdd, 0xdd,
- 0x02, 0x44, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xff, 0xff, 0x4f, 0x4c, 0xc5,
- 0x0c, 0xc1, 0x11, 0x1c, 0xc0, 0x26, 0x66, 0x17,
- 0x66, 0x88, 0x88, 0x12, 0x22, 0x23, 0xa8, 0x88,
- 0x11, 0x13, 0x88, 0x66, 0x17, 0xbb, 0xdd, 0xdd,
- 0xd0, 0x8f, 0xff, 0xf4, 0xf4, 0x44, 0xf4, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0x4f, 0x44, 0xdd, 0xdd,
- 0x00, 0x00, 0x00, 0x05, 0x9d, 0x21, 0x66, 0x27,
- 0xa6, 0x65, 0x58, 0x67, 0x22, 0x27, 0x28, 0x88,
- 0x11, 0xaa, 0x86, 0x68, 0x1a, 0xbb, 0xdd, 0xdd,
- 0xdb, 0x05, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xdd, 0xdb,
- 0x00, 0x00, 0x00, 0x00, 0xdd, 0xda, 0x66, 0x22,
- 0x71, 0x15, 0x55, 0x81, 0x22, 0x22, 0x76, 0x88,
- 0x11, 0x31, 0x88, 0x88, 0xab, 0xbd, 0xdd, 0xdd,
- 0xdd, 0x00, 0x04, 0x44, 0xff, 0xff, 0x4f, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0x44, 0xdd, 0xdb,
- 0x00, 0x00, 0x00, 0x0b, 0xdd, 0xda, 0x11, 0x22,
- 0x23, 0x68, 0x55, 0x86, 0x22, 0x22, 0x7a, 0x88,
- 0x1a, 0x71, 0x88, 0x89, 0xbb, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xd0, 0x00, 0x4f, 0x44, 0xff, 0x4f, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0xff, 0xe2, 0xdd, 0xdb,
- 0x90, 0x00, 0x05, 0xbd, 0xdd, 0xb8, 0x63, 0x22,
- 0x27, 0xa6, 0x55, 0x88, 0x77, 0x22, 0x22, 0x88,
- 0x1a, 0x28, 0xbd, 0xdb, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdb, 0x00, 0x07, 0x44, 0x4f, 0x4f, 0x4f,
- 0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x22, 0xdd, 0xdb,
- 0xbb, 0x9b, 0xbb, 0xbd, 0xdd, 0xd5, 0x86, 0x22,
- 0x22, 0x77, 0x85, 0x88, 0x17, 0x22, 0x22, 0x88,
- 0xaa, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0x00, 0x00, 0x54, 0x4f, 0x4f, 0x4f,
- 0xff, 0x4f, 0x44, 0xf4, 0x44, 0x22, 0xbd, 0xdd,
- 0xbb, 0xbb, 0xbb, 0xdd, 0xdd, 0xdd, 0x88, 0x72,
- 0x27, 0x22, 0x88, 0x88, 0x67, 0x72, 0x22, 0x18,
- 0x33, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xd0, 0x00, 0x05, 0x4f, 0x4f, 0x4f,
- 0xff, 0x4f, 0x44, 0x44, 0x4f, 0x22, 0xbd, 0xdd,
- 0xdb, 0xbb, 0xdd, 0xdd, 0xdd, 0xdd, 0x88, 0x17,
- 0x27, 0x72, 0x68, 0x88, 0x87, 0x32, 0x22, 0x36,
- 0x37, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xd5, 0x00, 0x00, 0x4f, 0x4f, 0x4f,
- 0xff, 0xf4, 0xf4, 0xf4, 0xf4, 0x22, 0xbb, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x67,
- 0x72, 0x77, 0x38, 0x88, 0x83, 0x37, 0x22, 0x26,
- 0x72, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0x00, 0x00, 0x4f, 0x4f, 0x4f,
- 0xff, 0xf4, 0xf4, 0xf4, 0x44, 0x25, 0xbb, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd3,
- 0x32, 0x73, 0x76, 0x88, 0x81, 0x33, 0x22, 0x2a,
- 0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xb0, 0x54, 0x4f, 0x4f, 0x4f,
- 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x00, 0xbb, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xa7, 0x73, 0x26, 0x88, 0x86, 0x7a, 0x72, 0x27,
- 0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0xff, 0x4f, 0x4f,
- 0xff, 0xf4, 0xf4, 0x44, 0x40, 0x05, 0xbb, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0x13, 0x23, 0x21, 0x68, 0x86, 0x17, 0x72, 0x22,
- 0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0x4f, 0x4f, 0x4f,
- 0xff, 0xff, 0x44, 0x42, 0x00, 0x05, 0xbd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0x87, 0x27, 0x27, 0x16, 0x66, 0x67, 0x22, 0x22,
- 0x72, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0x94, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x00, 0x00, 0x05, 0xbb, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb8,
- 0x86, 0x22, 0x22, 0x7a, 0x68, 0x81, 0x22, 0x22,
- 0x37, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x44, 0x44, 0x44,
- 0x44, 0x47, 0x00, 0x00, 0x00, 0x05, 0xbd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x68,
- 0x58, 0x72, 0x22, 0x27, 0x18, 0x86, 0x72, 0x22,
- 0x1a, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x18, 0x85,
- 0x58, 0x12, 0x22, 0x36, 0x18, 0x88, 0x32, 0x22,
- 0x61, 0x3b, 0xbb, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
- 0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x7a, 0x68, 0x85,
- 0x88, 0x62, 0x27, 0x16, 0x18, 0x88, 0x12, 0x27,
- 0x86, 0x18, 0x9b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbd,
- 0xdd, 0xdd, 0xdd, 0xbb, 0xb5, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xbb, 0xbd,
- 0xdd, 0xdd, 0xdb, 0xbb, 0x87, 0x31, 0x68, 0x65,
- 0x88, 0x82, 0x23, 0x16, 0x18, 0x88, 0x12, 0x23,
- 0x88, 0x67, 0x27, 0xa8, 0x9b, 0xbb, 0xbb, 0xbb,
- 0xbd, 0xdd, 0xbb, 0xbb, 0x95, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x9b, 0xbb,
- 0xbb, 0xbb, 0xbb, 0x96, 0x87, 0x16, 0x68, 0x18,
- 0x88, 0x62, 0x31, 0x66, 0x18, 0x88, 0x62, 0x73,
- 0x88, 0x63, 0x27, 0x33, 0x65, 0x55, 0x99, 0x9b,
- 0xbb, 0xbb, 0xbb, 0x99, 0x55, 0x0a, 0xa1, 0x86,
- 0x81, 0x68, 0x88, 0x55, 0x58, 0x85, 0x9b, 0xbb,
- 0xbb, 0xbb, 0x95, 0x88, 0x83, 0x66, 0x66, 0x18,
- 0x66, 0x82, 0xa1, 0x66, 0x18, 0x88, 0x62, 0x33,
- 0x88, 0x81, 0x27, 0x7a, 0x18, 0x58, 0x86, 0x85,
- 0x99, 0x99, 0x99, 0x95, 0x53, 0x2a, 0xaa, 0x88,
- 0x67, 0x31, 0x68, 0x55, 0x58, 0x85, 0x59, 0xbb,
- 0xbb, 0xb9, 0x58, 0x68, 0x83, 0x66, 0x61, 0x16,
- 0x66, 0x62, 0x16, 0x66, 0x68, 0x88, 0x62, 0xaa,
- 0x88, 0x86, 0x27, 0x77, 0x78, 0x55, 0x88, 0x22,
- 0x25, 0x55, 0x95, 0x55, 0x6a, 0xa2, 0x2a, 0x88,
- 0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59,
- 0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68,
- 0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11,
- 0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17,
- 0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66,
- 0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55,
- 0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88,
- 0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11,
- 0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62,
- 0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88,
- 0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61,
- 0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88,
- 0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61,
- 0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83,
- 0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55,
- 0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66,
- 0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88,
- 0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61,
- 0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86,
- 0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55,
- 0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68,
- 0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86,
- 0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61,
- 0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58,
- 0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55,
- 0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68,
- 0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68,
- 0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66,
- 0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88,
- 0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55,
- 0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66,
- 0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68,
- 0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66,
- 0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88,
- 0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85,
- 0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68,
- 0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88,
- 0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a
-};
-
-#endif
diff --git a/include/lxt971a.h b/include/lxt971a.h
deleted file mode 100644
index a5dd82b..0000000
--- a/include/lxt971a.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
- * @Author: Markus Pietrek
- * @References: [1] NS9750 Hardware Reference, December 2003
- * [2] Intel LXT971 Datasheet #249414 Rev. 02
- * [3] NS7520 Linux Ethernet Driver
- */
-
-#ifndef __LXT971A_H__
-#define __LXT971A_H__
-
-/* PHY definitions (LXT971A) [2] */
-#define PHY_LXT971_PORT_CFG (0x10)
-#define PHY_LXT971_STAT2 (0x11)
-#define PHY_LXT971_INT_ENABLE (0x12)
-#define PHY_LXT971_INT_STATUS (0x13)
-#define PHY_LXT971_LED_CFG (0x14)
-#define PHY_LXT971_DIG_CFG (0x1A)
-#define PHY_LXT971_TX_CTRL (0x1E)
-
-/* PORT_CFG Port Configuration Register Bit Fields */
-#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
-#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
-#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
-#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
-#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
-#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
-#define PHY_LXT971_PORT_CFG_SQE (0x0200)
-#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
-#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
-#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
-#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
-#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
-#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
-#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
-
-/* STAT2 Status Register #2 Bit Fields */
-#define PHY_LXT971_STAT2_RES1 (0x8000)
-#define PHY_LXT971_STAT2_100BTX (0x4000)
-#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
-#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
-#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
-#define PHY_LXT971_STAT2_LINK (0x0400)
-#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
-#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
-#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
-#define PHY_LXT971_STAT2_RES2 (0x0040)
-#define PHY_LXT971_STAT2_POLARITY (0x0020)
-#define PHY_LXT971_STAT2_PAUSE (0x0010)
-#define PHY_LXT971_STAT2_ERROR (0x0008)
-#define PHY_LXT971_STAT2_RES3 (0x0007)
-
-/* INT_ENABLE Interrupt Enable Register Bit Fields */
-#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
-#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
-#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
-#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
-#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
-#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
-#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
-#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
-
-/* INT_STATUS Interrupt Status Register Bit Fields */
-#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
-#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
-#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
-#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
-#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
-#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
-#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
-#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
-
-/* LED_CFG Interrupt LED Configuration Register Bit Fields */
-#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
-#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
-#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
-#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
-#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
-#define PHY_LXT971_LED_CFG_RES1 (0x0001)
-
-/* only one of these values must be shifted for each SHIFT_LED? */
-#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
-#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
-#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
-#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
-#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
-#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
-#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
-#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
-#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
-#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
-#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
-#define PHY_LXT971_LED_CFG_LINK (0x0004)
-#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
-#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
-#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
-#define PHY_LXT971_LED_CFG_SPEED (0x0000)
-
-/* DIG_CFG Digitial Configuration Register Bit Fields */
-#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
-#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
-#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
-#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
-#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
-
-#define PHY_LXT971_MDIO_MAX_CLK (8000000)
-#define PHY_MDIO_MAX_CLK (2500000)
-
-/* TX_CTRL Transmit Control Register Bit Fields
- documentation is buggy for this register, therefore setting not included */
-
-typedef enum
-{
- PHY_NONE = 0x0000, /* no PHY detected yet */
- PHY_LXT971A = 0x0013
-} PhyType;
-
-#endif /* __LXT971A_H__ */
diff --git a/include/mc13783.h b/include/mc13783.h
deleted file mode 100644
index c7ee03b..0000000
--- a/include/mc13783.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
- */
-
-
-#ifndef __MC13783_H__
-#define __MC13783_H__
-
-/* REG_MODE_0 */
-#define VAUDIOEN (1 << 0)
-#define VAUDIOSTBY (1 << 1)
-#define VAUDIOMODE (1 << 2)
-#define VIOHIEN (1 << 3)
-#define VIOHISTBY (1 << 4)
-#define VIOHIMODE (1 << 5)
-#define VIOLOEN (1 << 6)
-#define VIOLOSTBY (1 << 7)
-#define VIOLOMODE (1 << 8)
-#define VDIGEN (1 << 9)
-#define VDIGSTBY (1 << 10)
-#define VDIGMODE (1 << 11)
-#define VGENEN (1 << 12)
-#define VGENSTBY (1 << 13)
-#define VGENMODE (1 << 14)
-#define VRFDIGEN (1 << 15)
-#define VRFDIGSTBY (1 << 16)
-#define VRFDIGMODE (1 << 17)
-#define VRFREFEN (1 << 18)
-#define VRFREFSTBY (1 << 19)
-#define VRFREFMODE (1 << 20)
-#define VRFCPEN (1 << 21)
-#define VRFCPSTBY (1 << 22)
-#define VRFCPMODE (1 << 23)
-
-/* REG_MODE_1 */
-#define VSIMEN (1 << 0)
-#define VSIMSTBY (1 << 1)
-#define VSIMMODE (1 << 2)
-#define VESIMEN (1 << 3)
-#define VESIMSTBY (1 << 4)
-#define VESIMMODE (1 << 5)
-#define VCAMEN (1 << 6)
-#define VCAMSTBY (1 << 7)
-#define VCAMMODE (1 << 8)
-#define VRFBGEN (1 << 9)
-#define VRFBGSTBY (1 << 10)
-#define VVIBEN (1 << 11)
-#define VRF1EN (1 << 12)
-#define VRF1STBY (1 << 13)
-#define VRF1MODE (1 << 14)
-#define VRF2EN (1 << 15)
-#define VRF2STBY (1 << 16)
-#define VRF2MODE (1 << 17)
-#define VMMC1EN (1 << 18)
-#define VMMC1STBY (1 << 19)
-#define VMMC1MODE (1 << 20)
-#define VMMC2EN (1 << 21)
-#define VMMC2STBY (1 << 22)
-#define VMMC2MODE (1 << 23)
-
-#endif
diff --git a/include/mc34704.h b/include/mc34704.h
deleted file mode 100644
index b837dda..0000000
--- a/include/mc34704.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __MC34704_H__
-#define __MC34704_H__
-
-enum {
- MC34704_RESERVED0_REG = 0, /* 0x00 */
- MC34704_GENERAL1_REG, /* 0x01 */
- MC34704_GENERAL2_REG, /* 0x02 */
- MC34704_GENERAL3_REG, /* 0x03 */
- MC34704_RESERVED4_REG, /* 0x04 */
- MC34704_VGSET2_REG, /* 0x05 */
- MC34704_REG2SET1_REG, /* 0x06 */
- MC34704_REG2SET2_REG, /* 0x07 */
- MC34704_REG3SET1_REG, /* 0x08 */
- MC34704_REG3SET2_REG, /* 0x09 */
- MC34704_REG4SET1_REG, /* 0x0a */
- MC34704_REG4SET2_REG, /* 0x0b */
- MC34704_REG5SET1_REG, /* 0x0c */
- MC34704_REG5SET2_REG, /* 0x0d */
- MC34704_REG5SET3_REG, /* 0x0e */
- MC34704_RESERVEDF_REG, /* 0x0f */
- MC34704_RESERVED10_REG, /* 0x10 */
- MC34704_RESERVED11_REG, /* 0x11 */
- MC34704_RESERVED12_REG, /* 0x12 */
- MC34704_FSW2SET_REG, /* 0x13 */
- MC34704_RESERVED14_REG, /* 0x14 */
- MC34704_REG8SET1_REG, /* 0x15 */
- MC34704_REG8SET2_REG, /* 0x16 */
- MC34704_REG8SET3_REG, /* 0x17 */
- MC34704_FAULTS_REG, /* 0x18 */
- MC34704_I2CSET1, /* 0x19 */
- MC34704_NUM_OF_REGS,
-};
-
-/* GENERAL2 register fields */
-#define ONOFFE (1 << 0)
-#define ONOFFD (1 << 1)
-#define ONOFFA (1 << 3)
-#define ALLOFF (1 << 4)
-
-#endif /* __MC34704_H__ */
diff --git a/include/mc9sdz60.h b/include/mc9sdz60.h
deleted file mode 100644
index ffe376b..0000000
--- a/include/mc9sdz60.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
- *
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#ifndef __ASM_ARCH_MC9SDZ60_H
-#define __ASM_ARCH_MC9SDZ60_H
-
-/**
- * Register addresses for the MC9SDZ60
- *
- * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
- * but not include/linux/mfd/mc9s08dz60/pmic.h
- *
- */
-enum mc9sdz60_reg {
- MC9SDZ60_REG_VERSION = 0x00,
- /* reserved 0x01 */
- MC9SDZ60_REG_SECS = 0x02,
- MC9SDZ60_REG_MINS = 0x03,
- MC9SDZ60_REG_HRS = 0x04,
- MC9SDZ60_REG_DAY = 0x05,
- MC9SDZ60_REG_DATE = 0x06,
- MC9SDZ60_REG_MONTH = 0x07,
- MC9SDZ60_REG_YEAR = 0x08,
- MC9SDZ60_REG_ALARM_SECS = 0x09,
- MC9SDZ60_REG_ALARM_MINS = 0x0a,
- MC9SDZ60_REG_ALARM_HRS = 0x0b,
- /* reserved 0x0c */
- /* reserved 0x0d */
- MC9SDZ60_REG_TS_CONTROL = 0x0e,
- MC9SDZ60_REG_X_LOW = 0x0f,
- MC9SDZ60_REG_Y_LOW = 0x10,
- MC9SDZ60_REG_XY_HIGH = 0x11,
- MC9SDZ60_REG_X_LEFT_LOW = 0x12,
- MC9SDZ60_REG_X_LEFT_HIGH = 0x13,
- MC9SDZ60_REG_X_RIGHT = 0x14,
- MC9SDZ60_REG_Y_TOP_LOW = 0x15,
- MC9SDZ60_REG_Y_TOP_HIGH = 0x16,
- MC9SDZ60_REG_Y_BOTTOM = 0x17,
- /* reserved 0x18 */
- /* reserved 0x19 */
- MC9SDZ60_REG_RESET_1 = 0x1a,
- MC9SDZ60_REG_RESET_2 = 0x1b,
- MC9SDZ60_REG_POWER_CTL = 0x1c,
- MC9SDZ60_REG_DELAY_CONFIG = 0x1d,
- /* reserved 0x1e */
- /* reserved 0x1f */
- MC9SDZ60_REG_GPIO_1 = 0x20,
- MC9SDZ60_REG_GPIO_2 = 0x21,
- MC9SDZ60_REG_KPD_1 = 0x22,
- MC9SDZ60_REG_KPD_2 = 0x23,
- MC9SDZ60_REG_KPD_CONTROL = 0x24,
- MC9SDZ60_REG_INT_ENABLE_1 = 0x25,
- MC9SDZ60_REG_INT_ENABLE_2 = 0x26,
- MC9SDZ60_REG_INT_FLAG_1 = 0x27,
- MC9SDZ60_REG_INT_FLAG_2 = 0x28,
- MC9SDZ60_REG_DES_FLAG = 0x29,
-};
-
-extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
-extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
-
-#endif /* __ASM_ARCH_MC9SDZ60_H */
diff --git a/include/mii_phy.h b/include/mii_phy.h
deleted file mode 100644
index f0d3e62..0000000
--- a/include/mii_phy.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _MII_PHY_H_
-#define _MII_PHY_H_
-
-void mii_discover_phy(void);
-unsigned short mii_phy_read(unsigned short reg);
-void mii_phy_write(unsigned short reg, unsigned short val);
-
-#endif
diff --git a/include/mk48t59.h b/include/mk48t59.h
deleted file mode 100644
index f95d349..0000000
--- a/include/mk48t59.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- */
-
-/*
- * Date & Time support for the MK48T59 RTC
- */
-
-
-#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
-
-#define RTC_PORT_ADDR0 0x70
-#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1
-#define RTC_PORT_DATA 0x76
-
-/* RTC Offsets */
-#define RTC_SECONDS 0x1FF9
-#define RTC_MINUTES 0x1FFA
-#define RTC_HOURS 0x1FFB
-#define RTC_DAY_OF_WEEK 0x1FFC
-#define RTC_DAY_OF_MONTH 0x1FFD
-#define RTC_MONTH 0x1FFE
-#define RTC_YEAR 0x1FFF
-
-#define RTC_CONTROLA 0x1FF8
-#define RTC_CA_WRITE 0x80
-#define RTC_CA_READ 0x40
-#define RTC_CA_CALIB_SIGN 0x20
-#define RTC_CA_CALIB_MASK 0x1f
-
-#define RTC_CONTROLB 0x1FF9
-#define RTC_CB_STOP 0x80
-
-#define RTC_WATCHDOG 0x1FF7
-#define RTC_WDS 0x80
-#define RTC_WD_RB_16TH 0x0
-#define RTC_WD_RB_4TH 0x1
-#define RTC_WD_RB_1 0x2
-#define RTC_WD_RB_4 0x3
-
-void rtc_set_watchdog(short multi, short res);
-void *nvram_read(void *dest, const short src, size_t count);
-void nvram_write(short dest, const void *src, size_t count);
-
-#endif
diff --git a/include/mpc106.h b/include/mpc106.h
deleted file mode 100644
index 2157b32..0000000
--- a/include/mpc106.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- */
-
-#ifndef _MPC106_PCI_H
-#define _MPC106_PCI_H
-
-/*
- * Defines for the MPC106 PCI Config address and data registers followed by
- * defines for the standard PCI device configuration header.
- */
-#define PCIDEVID_MPC106 0x0
-
-/*
- * MPC106 Registers
- */
-#define MPC106_REG 0x80000000
-
-#ifdef CONFIG_SYS_ADDRESS_MAP_A
-#define MPC106_REG_ADDR 0x80000cf8
-#define MPC106_REG_DATA 0x80000cfc
-#define MPC106_ISA_IO_PHYS 0x80000000
-#define MPC106_ISA_IO_BUS 0x00000000
-#define MPC106_ISA_IO_SIZE 0x00800000
-#define MPC106_PCI_IO_PHYS 0x81000000
-#define MPC106_PCI_IO_BUS 0x01000000
-#define MPC106_PCI_IO_SIZE 0x3e800000
-#define MPC106_PCI_MEM_PHYS 0xc0000000
-#define MPC106_PCI_MEM_BUS 0x00000000
-#define MPC106_PCI_MEM_SIZE 0x3f000000
-#define MPC106_PCI_MEMORY_PHYS 0x00000000
-#define MPC106_PCI_MEMORY_BUS 0x80000000
-#define MPC106_PCI_MEMORY_SIZE 0x80000000
-#else
-#define MPC106_REG_ADDR 0xfec00cf8
-#define MPC106_REG_DATA 0xfee00cfc
-#define MPC106_ISA_MEM_PHYS 0xfd000000
-#define MPC106_ISA_MEM_BUS 0x00000000
-#define MPC106_ISA_MEM_SIZE 0x01000000
-#define MPC106_ISA_IO_PHYS 0xfe000000
-#define MPC106_ISA_IO_BUS 0x00000000
-#define MPC106_ISA_IO_SIZE 0x00800000
-#define MPC106_PCI_IO_PHYS 0xfe800000
-#define MPC106_PCI_IO_BUS 0x00800000
-#define MPC106_PCI_IO_SIZE 0x00400000
-#define MPC106_PCI_MEM_PHYS 0x80000000
-#define MPC106_PCI_MEM_BUS 0x80000000
-#define MPC106_PCI_MEM_SIZE 0x7d000000
-#define MPC106_PCI_MEMORY_PHYS 0x00000000
-#define MPC106_PCI_MEMORY_BUS 0x00000000
-#define MPC106_PCI_MEMORY_SIZE 0x40000000
-#endif
-
-#define CMD_SERR 0x0100
-#define PCI_CMD_MASTER 0x0004
-#define PCI_CMD_MEMEN 0x0002
-#define PCI_CMD_IOEN 0x0001
-
-#define PCI_STAT_NO_RSV_BITS 0xffff
-
-#define PCI_BUSNUM 0x40
-#define PCI_SUBBUSNUM 0x41
-#define PCI_DISCOUNT 0x42
-
-#define PCI_PICR1 0xA8
-#define PICR1_CF_CBA(value) ((value & 0xff) << 24)
-#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22)
-#define PICR1_PROC_TYPE_603 0x40000
-#define PICR1_PROC_TYPE_604 0x60000
-#define PICR1_MCP_EN 0x800
-#define PICR1_CF_DPARK 0x200
-#define PICR1_CF_LOOP_SNOOP 0x10
-#define PICR1_CF_L2_COPY_BACK 0x2
-#define PICR1_CF_L2_CACHE_MASK 0x3
-#define PICR1_CF_APARK 0x8
-#define PICR1_ADDRESS_MAP 0x10000
-#define PICR1_XIO_MODE 0x80000
-#define PICR1_CF_CACHE_1G 0x200000
-
-#define PCI_PICR2 0xAC
-#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18)
-#define PICR2_CF_FLUSH_L2 0x10000000
-#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9)
-#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2)
-#define PICR2_CF_INV_MODE 0x00001000
-#define PICR2_CF_MOD_HIGH 0x00020000
-#define PICR2_CF_HIT_HIGH 0x00010000
-#define PICR2_L2_SIZE_256K 0x00000000
-#define PICR2_L2_SIZE_512K 0x00000010
-#define PICR2_L2_SIZE_1MB 0x00000020
-#define PICR2_L2_EN 0x40000000
-#define PICR2_L2_UPDATE_EN 0x80000000
-#define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000
-#define PICR2_CF_FAST_CASTOUT 0x00000080
-#define PICR2_CF_WDATA 0x00000001
-#define PICR2_CF_DATA_RAM_PBURST 0x00400000
-
-/*
- * Memory controller
- */
-#define MPC106_MCCR1 0xF0
-#define MCCR1_TYPE_EDO 0x00020000
-#define MCCR1_BK0_9BITS 0x0
-#define MCCR1_BK0_10BITS 0x1
-#define MCCR1_BK0_11BITS 0x2
-#define MCCR1_BK0_12BITS 0x3
-#define MCCR1_BK1_9BITS 0x0
-#define MCCR1_BK1_10BITS 0x4
-#define MCCR1_BK1_11BITS 0x8
-#define MCCR1_BK1_12BITS 0xC
-#define MCCR1_BK2_9BITS 0x00
-#define MCCR1_BK2_10BITS 0x10
-#define MCCR1_BK2_11BITS 0x20
-#define MCCR1_BK2_12BITS 0x30
-#define MCCR1_BK3_9BITS 0x00
-#define MCCR1_BK3_10BITS 0x40
-#define MCCR1_BK3_11BITS 0x80
-#define MCCR1_BK3_12BITS 0xC0
-#define MCCR1_MEMGO 0x00080000
-
-#define MPC106_MCCR2 0xF4
-#define MPC106_MCCR3 0xF8
-#define MPC106_MCCR4 0xFC
-
-#define MPC106_MSAR1 0x80
-#define MPC106_EMSAR1 0x88
-#define MPC106_EMSAR2 0x8C
-#define MPC106_MEAR1 0x90
-#define MPC106_EMEAR1 0x98
-#define MPC106_EMEAR2 0x9C
-
-#define MPC106_MBER 0xA0
-#define MBER_BANK0 0x1
-#define MBER_BANK1 0x2
-#define MBER_BANK2 0x4
-#define MBER_BANK3 0x8
-
-#endif
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
deleted file mode 100644
index ea8d17d..0000000
--- a/include/mpc86xx.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2006 Freescale Semiconductor.
- * Jeffrey Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- */
-
-#ifndef __MPC86xx_H__
-#define __MPC86xx_H__
-
-#include <asm/fsl_lbc.h>
-
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
-#define _START_OFFSET EXC_OFF_SYS_RESET
-
-/*
- * platform register addresses
- */
-
-#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4)
-#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000)
-#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008)
-
-/*
- * l2cr values. Look in config_<BOARD>.h for the actual setup
- */
-#define l2cr 1017
-
-#define L2CR_L2E 0x80000000 /* bit 0 - enable */
-#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
-#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
-#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
-#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
-#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
-#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
-#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-
-#define HID0_XBSEN 0x00000100
-#define HID0_HIGH_BAT_EN 0x00800000
-#define HID0_XAEN 0x00020000
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
- unsigned long freq_processor;
- unsigned long freq_systembus;
- unsigned long freq_localbus;
-} MPC86xx_SYS_INFO;
-
-#define l1icache_enable icache_enable
-
-void l2cache_enable(void);
-void l1dcache_enable(void);
-
-static __inline__ unsigned long get_hid0 (void)
-{
- unsigned long hid0;
- asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
- return hid0;
-}
-
-static __inline__ unsigned long get_hid1 (void)
-{
- unsigned long hid1;
- asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
- return hid1;
-}
-
-static __inline__ void set_hid0 (unsigned long hid0)
-{
- asm volatile("mtspr 1008, %0" : : "r" (hid0));
-}
-
-static __inline__ void set_hid1 (unsigned long hid1)
-{
- asm volatile("mtspr 1009, %0" : : "r" (hid1));
-}
-
-
-static __inline__ unsigned long get_l2cr (void)
-{
- unsigned long l2cr_val;
- asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
- return l2cr_val;
-}
-
-void setup_ddr_bat(phys_addr_t dram_size);
-extern void setup_bats(void);
-
-#endif /* _ASMLANGUAGE */
-#endif /* __MPC86xx_H__ */
diff --git a/include/mvmfp.h b/include/mvmfp.h
deleted file mode 100644
index de86ffd..0000000
--- a/include/mvmfp.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __MVMFP_H
-#define __MVMFP_H
-
-/*
- * Header file for MultiFunctionPin (MFP) Configururation framework
- *
- * Processors Supported:
- * 1. Marvell ARMADA100 Processors
- *
- * processor to be supported should be added here
- */
-
-/*
- * MFP configuration is represented by a 32-bit unsigned integer
- */
-#ifdef CONFIG_MVMFP_V2
-#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
- /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
- /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
- /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \
- /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \
- /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \
- /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
- /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \
- /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7))
-#else
-#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
- /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
- /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
- /* bit 12 - Unused */ \
- /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \
- /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \
- /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
- /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \
- /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7))
-#endif
-
-/*
- * to facilitate the definition, the following macros are provided
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0)
-#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0)
-#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16)
-
-#define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0)
-#define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1)
-#define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2)
-#define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3)
-#define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4)
-#define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5)
-#define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6)
-#define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7)
-#define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7)
-
-#define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0)
-#define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0)
-#define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0)
-#define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0)
-#define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0)
-
-#define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0)
-#define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0)
-#define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0)
-#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0)
-#define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0)
-
-#define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0)
-
-#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0)
-#define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0)
-#define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0)
-#define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0)
-#define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0)
-
-#define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0)
-#define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0)
-#define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0)
-#define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0)
-#define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0)
-#define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0)
-
-#define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \
- | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \
- | MFP_AF_MASK)
-#define MFP_EOC 0xffffffff /* indicates end-of-conf */
-
-/* Functions */
-void mfp_config(u32 *mfp_cfgs);
-
-#endif /* __MVMFP_H */
diff --git a/include/pca9564.h b/include/pca9564.h
deleted file mode 100644
index 99e8bcd..0000000
--- a/include/pca9564.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * File: include/pca9564.h
- * Author:
- *
- * Created: 2009-06-23
- * Description: PCA9564 i2c bridge driver
- *
- * Modified:
- * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- *
- * Bugs:
- */
-
-#ifndef _PCA9564_H
-#define _PCA9564_H
-
-/* Clock speeds for the bus */
-#define PCA_CON_330kHz 0x00
-#define PCA_CON_288kHz 0x01
-#define PCA_CON_217kHz 0x02
-#define PCA_CON_146kHz 0x03
-#define PCA_CON_88kHz 0x04
-#define PCA_CON_59kHz 0x05
-#define PCA_CON_44kHz 0x06
-#define PCA_CON_36kHz 0x07
-
-#define PCA_CON_AA 0x80 /* Assert Acknowledge */
-#define PCA_CON_ENSIO 0x40 /* Enable */
-#define PCA_CON_STA 0x20 /* Start */
-#define PCA_CON_STO 0x10 /* Stop */
-#define PCA_CON_SI 0x08 /* Serial Interrupt */
-#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */
-
-#endif
diff --git a/include/phy.h b/include/phy.h
index 247223d..f023a3c 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -224,15 +224,6 @@
#endif
/**
- * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
- * @phydev: PHY device
- * @dev: Ethernet device
- * @interface: type of MAC-PHY interface
- */
-void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
- phy_interface_t interface);
-
-/**
* phy_connect() - Creates a PHY device for the Ethernet interface
* Creates a PHY device for the PHY at the given address, if one doesn't exist
* already, and associates it with the Ethernet device.
diff --git a/include/power/pmic.h b/include/power/pmic.h
index 70f2709..6362216 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -86,7 +86,7 @@
#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */
/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */
-#ifdef CONFIG_DM_PMIC
+#if defined(CONFIG_DM_PMIC) || !CONFIG_IS_ENABLED(POWER_LEGACY)
/**
* U-Boot PMIC Framework
* =====================
diff --git a/include/sja1000.h b/include/sja1000.h
deleted file mode 100644
index 6ceb6f4..0000000
--- a/include/sja1000.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
- *
- * SJA1000 register layout for basic CAN mode
- */
-
-#ifndef _SJA1000_H_
-#define _SJA1000_H_
-
-/*
- * SJA1000 register layout in basic can mode
- */
-struct sja1000_basic_s {
- u8 cr;
- u8 cmr;
- u8 sr;
- u8 ir;
- u8 ac;
- u8 am;
- u8 btr0;
- u8 btr1;
- u8 oc;
- u8 txb[10];
- u8 rxb[10];
- u8 unused;
- u8 cdr;
-};
-
-/* control register */
-#define CR_RR 0x01
-
-/* output control register */
-#define OC_MODE0 0x01
-#define OC_MODE1 0x02
-#define OC_POL0 0x04
-#define OC_TN0 0x08
-#define OC_TP0 0x10
-#define OC_POL1 0x20
-#define OC_TN1 0x40
-#define OC_TP1 0x80
-
-#endif
diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h
deleted file mode 100644
index 7628c33..0000000
--- a/include/sym53c8xx.h
+++ /dev/null
@@ -1,552 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * Most of these definitions are derived from
- * linux/drivers/scsi/sym53c8xx_defs.h
- */
-
-#ifndef _SYM53C8XX_DEFS_H
-#define _SYM53C8XX_DEFS_H
-
-
-#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
-
-#define SCNTL1 0x01 /* no reset */
- #define ISCON 0x10 /* connected to scsi */
- #define CRST 0x08 /* force reset */
- #define IARB 0x02 /* immediate arbitration */
-
-#define SCNTL2 0x02 /* no disconnect expected */
- #define SDU 0x80 /* cmd: disconnect will raise error */
- #define CHM 0x40 /* sta: chained mode */
- #define WSS 0x08 /* sta: wide scsi send [W]*/
- #define WSR 0x01 /* sta: wide scsi received [W]*/
-
-#define SCNTL3 0x03 /* cnf system clock dependent */
- #define EWS 0x08 /* cmd: enable wide scsi [W]*/
- #define ULTRA 0x80 /* cmd: ULTRA enable */
- /* bits 0-2, 7 rsvd for C1010 */
-
-#define SCID 0x04 /* cnf host adapter scsi address */
- #define RRE 0x40 /* r/w:e enable response to resel. */
- #define SRE 0x20 /* r/w:e enable response to select */
-
-#define SXFER 0x05 /* ### Sync speed and count */
- /* bits 6-7 rsvd for C1010 */
-
-#define SDID 0x06 /* ### Destination-ID */
-
-#define GPREG 0x07 /* ??? IO-Pins */
-
-#define SFBR 0x08 /* ### First byte in phase */
-
-#define SOCL 0x09
- #define CREQ 0x80 /* r/w: SCSI-REQ */
- #define CACK 0x40 /* r/w: SCSI-ACK */
- #define CBSY 0x20 /* r/w: SCSI-BSY */
- #define CSEL 0x10 /* r/w: SCSI-SEL */
- #define CATN 0x08 /* r/w: SCSI-ATN */
- #define CMSG 0x04 /* r/w: SCSI-MSG */
- #define CC_D 0x02 /* r/w: SCSI-C_D */
- #define CI_O 0x01 /* r/w: SCSI-I_O */
-
-#define SSID 0x0a
-
-#define SBCL 0x0b
-
-#define DSTAT 0x0c
- #define DFE 0x80 /* sta: dma fifo empty */
- #define MDPE 0x40 /* int: master data parity error */
- #define BF 0x20 /* int: script: bus fault */
- #define ABRT 0x10 /* int: script: command aborted */
- #define SSI 0x08 /* int: script: single step */
- #define SIR 0x04 /* int: script: interrupt instruct. */
- #define IID 0x01 /* int: script: illegal instruct. */
-
-#define SSTAT0 0x0d
- #define ILF 0x80 /* sta: data in SIDL register lsb */
- #define ORF 0x40 /* sta: data in SODR register lsb */
- #define OLF 0x20 /* sta: data in SODL register lsb */
- #define AIP 0x10 /* sta: arbitration in progress */
- #define LOA 0x08 /* sta: arbitration lost */
- #define WOA 0x04 /* sta: arbitration won */
- #define IRST 0x02 /* sta: scsi reset signal */
- #define SDP 0x01 /* sta: scsi parity signal */
-
-#define SSTAT1 0x0e
- #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
-
-#define SSTAT2 0x0f
- #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
- #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
- #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
- #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
- #define LDSC 0x02 /* sta: disconnect & reconnect */
-
-#define DSA 0x10 /* --> Base page */
-#define DSA1 0x11
-#define DSA2 0x12
-#define DSA3 0x13
-
-#define ISTAT 0x14 /* --> Main Command and status */
- #define CABRT 0x80 /* cmd: abort current operation */
- #define SRST 0x40 /* mod: reset chip */
- #define SIGP 0x20 /* r/w: message from host to ncr */
- #define SEM 0x10 /* r/w: message between host + ncr */
- #define CON 0x08 /* sta: connected to scsi */
- #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
- #define SIP 0x02 /* sta: scsi-interrupt */
- #define DIP 0x01 /* sta: host/script interrupt */
-
-
-#define CTEST0 0x18
-#define CTEST1 0x19
-#define CTEST2 0x1a
- #define CSIGP 0x40
- /* bits 0-2,7 rsvd for C1010 */
-
-#define CTEST3 0x1b
- #define FLF 0x08 /* cmd: flush dma fifo */
- #define CLF 0x04 /* cmd: clear dma fifo */
- #define FM 0x02 /* mod: fetch pin mode */
- #define WRIE 0x01 /* mod: write and invalidate enable */
- /* bits 4-7 rsvd for C1010 */
-
-#define DFIFO 0x20
-#define CTEST4 0x21
- #define BDIS 0x80 /* mod: burst disable */
- #define MPEE 0x08 /* mod: master parity error enable */
-
-#define CTEST5 0x22
- #define DFS 0x20 /* mod: dma fifo size */
- /* bits 0-1, 3-7 rsvd for C1010 */
-#define CTEST6 0x23
-
-#define DBC 0x24 /* ### Byte count and command */
-#define DNAD 0x28 /* ### Next command register */
-#define DSP 0x2c /* --> Script Pointer */
-#define DSPS 0x30 /* --> Script pointer save/opcode#2 */
-
-#define SCRATCHA 0x34 /* Temporary register a */
-#define SCRATCHA1 0x35
-#define SCRATCHA2 0x36
-#define SCRATCHA3 0x37
-
-#define DMODE 0x38
- #define BL_2 0x80 /* mod: burst length shift value +2 */
- #define BL_1 0x40 /* mod: burst length shift value +1 */
- #define ERL 0x08 /* mod: enable read line */
- #define ERMP 0x04 /* mod: enable read multiple */
- #define BOF 0x02 /* mod: burst op code fetch */
- #define MAN 0x01 /* mod: manual start */
-
-#define DIEN 0x39
-#define SBR 0x3a
-
-#define DCNTL 0x3b /* --> Script execution control */
- #define CLSE 0x80 /* mod: cache line size enable */
- #define PFF 0x40 /* cmd: pre-fetch flush */
- #define PFEN 0x20 /* mod: pre-fetch enable */
- #define SSM 0x10 /* mod: single step mode */
- #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
- #define STD 0x04 /* cmd: start dma mode */
- #define IRQD 0x02 /* mod: irq disable */
- #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
- /* bits 0-1 rsvd for C1010 */
-
-#define ADDER 0x3c
-
-#define SIEN 0x40 /* -->: interrupt enable */
-#define SIST 0x42 /* <--: interrupt status */
- #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
- #define STO 0x0400/* sta: timeout (select) */
- #define GEN 0x0200/* sta: timeout (general) */
- #define HTH 0x0100/* sta: timeout (handshake) */
- #define MA 0x80 /* sta: phase mismatch */
- #define CMP 0x40 /* sta: arbitration complete */
- #define SEL 0x20 /* sta: selected by another device */
- #define RSL 0x10 /* sta: reselected by another device*/
- #define SGE 0x08 /* sta: gross error (over/underflow)*/
- #define UDC 0x04 /* sta: unexpected disconnect */
- #define RST 0x02 /* sta: scsi bus reset detected */
- #define PAR 0x01 /* sta: scsi parity error */
-
-#define SLPAR 0x44
-#define SWIDE 0x45
-#define MACNTL 0x46
-#define GPCNTL 0x47
-#define STIME0 0x48 /* cmd: timeout for select&handshake*/
-#define STIME1 0x49 /* cmd: timeout user defined */
-#define RESPID 0x4a /* sta: Reselect-IDs */
-
-#define STEST0 0x4c
-
-#define STEST1 0x4d
- #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
- #define DBLEN 0x08 /* clock doubler running */
- #define DBLSEL 0x04 /* clock doubler selected */
-
-
-#define STEST2 0x4e
- #define ROF 0x40 /* reset scsi offset (after gross error!) */
- #define EXT 0x02 /* extended filtering */
-
-#define STEST3 0x4f
- #define TE 0x80 /* c: tolerAnt enable */
- #define HSC 0x20 /* c: Halt SCSI Clock */
- #define CSF 0x02 /* c: clear scsi fifo */
-
-#define SIDL 0x50 /* Lowlevel: latched from scsi data */
-#define STEST4 0x52
- #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
- #define SMODE_HVD 0x40 /* High Voltage Differential */
- #define SMODE_SE 0x80 /* Single Ended */
- #define SMODE_LVD 0xc0 /* Low Voltage Differential */
- #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
- /* bits 0-5 rsvd for C1010 */
-
-#define SODL 0x54 /* Lowlevel: data out to scsi data */
-
-#define SBDL 0x58 /* Lowlevel: data from scsi data */
-
-
-/*-----------------------------------------------------------
-**
-** Utility macros for the script.
-**
-**-----------------------------------------------------------
-*/
-
-#define REG(r) (r)
-
-/*-----------------------------------------------------------
-**
-** SCSI phases
-**
-** DT phases illegal for ncr driver.
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_DATA_OUT 0x00000000
-#define SCR_DATA_IN 0x01000000
-#define SCR_COMMAND 0x02000000
-#define SCR_STATUS 0x03000000
-#define SCR_DT_DATA_OUT 0x04000000
-#define SCR_DT_DATA_IN 0x05000000
-#define SCR_MSG_OUT 0x06000000
-#define SCR_MSG_IN 0x07000000
-
-#define SCR_ILG_OUT 0x04000000
-#define SCR_ILG_IN 0x05000000
-
-/*-----------------------------------------------------------
-**
-** Data transfer via SCSI.
-**
-**-----------------------------------------------------------
-**
-** MOVE_ABS (LEN)
-** <<start address>>
-**
-** MOVE_IND (LEN)
-** <<dnad_offset>>
-**
-** MOVE_TBL
-** <<dnad_offset>>
-**
-**-----------------------------------------------------------
-*/
-
-#define OPC_MOVE 0x08000000
-
-#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
-#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
-#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
-
-#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
-#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
-#define SCR_CHMOV_TBL (0x10000000)
-
-
-/*-----------------------------------------------------------
-**
-** Selection
-**
-**-----------------------------------------------------------
-**
-** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
-** <<alternate_address>>
-**
-** SEL_TBL | << dnad_offset>> [ | REL_JMP]
-** <<alternate_address>>
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_SEL_ABS 0x40000000
-#define SCR_SEL_ABS_ATN 0x41000000
-#define SCR_SEL_TBL 0x42000000
-#define SCR_SEL_TBL_ATN 0x43000000
-
-
-#define SCR_JMP_REL 0x04000000
-#define SCR_ID(id) (((unsigned long)(id)) << 16)
-
-/*-----------------------------------------------------------
-**
-** Waiting for Disconnect or Reselect
-**
-**-----------------------------------------------------------
-**
-** WAIT_DISC
-** dummy: <<alternate_address>>
-**
-** WAIT_RESEL
-** <<alternate_address>>
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_WAIT_DISC 0x48000000
-#define SCR_WAIT_RESEL 0x50000000
-
-/*-----------------------------------------------------------
-**
-** Bit Set / Reset
-**
-**-----------------------------------------------------------
-**
-** SET (flags {|.. })
-**
-** CLR (flags {|.. })
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_SET(f) (0x58000000 | (f))
-#define SCR_CLR(f) (0x60000000 | (f))
-
-#define SCR_CARRY 0x00000400
-#define SCR_TRG 0x00000200
-#define SCR_ACK 0x00000040
-#define SCR_ATN 0x00000008
-
-
-/*-----------------------------------------------------------
-**
-** Memory to memory move
-**
-**-----------------------------------------------------------
-**
-** COPY (bytecount)
-** << source_address >>
-** << destination_address >>
-**
-** SCR_COPY sets the NO FLUSH option by default.
-** SCR_COPY_F does not set this option.
-**
-** For chips which do not support this option,
-** ncr_copy_and_bind() will remove this bit.
-**-----------------------------------------------------------
-*/
-
-#define SCR_NO_FLUSH 0x01000000
-
-#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
-#define SCR_COPY_F(n) (0xc0000000 | (n))
-
-/*-----------------------------------------------------------
-**
-** Register move and binary operations
-**
-**-----------------------------------------------------------
-**
-** SFBR_REG (reg, op, data) reg = SFBR op data
-** << 0 >>
-**
-** REG_SFBR (reg, op, data) SFBR = reg op data
-** << 0 >>
-**
-** REG_REG (reg, op, data) reg = reg op data
-** << 0 >>
-**
-**-----------------------------------------------------------
-** On 810A, 860, 825A, 875, 895 and 896 chips the content
-** of SFBR register can be used as data (SCR_SFBR_DATA).
-** The 896 has additionnal IO registers starting at
-** offset 0x80. Bit 7 of register offset is stored in
-** bit 7 of the SCRIPTS instruction first DWORD.
-**-----------------------------------------------------------
-*/
-
-#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
-
-#define SCR_SFBR_REG(reg,op,data) \
- (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
-
-#define SCR_REG_SFBR(reg,op,data) \
- (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
-
-#define SCR_REG_REG(reg,op,data) \
- (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
-
-
-#define SCR_LOAD 0x00000000
-#define SCR_SHL 0x01000000
-#define SCR_OR 0x02000000
-#define SCR_XOR 0x03000000
-#define SCR_AND 0x04000000
-#define SCR_SHR 0x05000000
-#define SCR_ADD 0x06000000
-#define SCR_ADDC 0x07000000
-
-#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
-
-/*-----------------------------------------------------------
-**
-** FROM_REG (reg) SFBR = reg
-** << 0 >>
-**
-** TO_REG (reg) reg = SFBR
-** << 0 >>
-**
-** LOAD_REG (reg, data) reg = <data>
-** << 0 >>
-**
-** LOAD_SFBR(data) SFBR = <data>
-** << 0 >>
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_FROM_REG(reg) \
- SCR_REG_SFBR(reg,SCR_OR,0)
-
-#define SCR_TO_REG(reg) \
- SCR_SFBR_REG(reg,SCR_OR,0)
-
-#define SCR_LOAD_REG(reg,data) \
- SCR_REG_REG(reg,SCR_LOAD,data)
-
-#define SCR_LOAD_SFBR(data) \
- (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
-
-/*-----------------------------------------------------------
-**
-** LOAD from memory to register.
-** STORE from register to memory.
-**
-** Only supported by 810A, 860, 825A, 875, 895 and 896.
-**
-**-----------------------------------------------------------
-**
-** LOAD_ABS (LEN)
-** <<start address>>
-**
-** LOAD_REL (LEN) (DSA relative)
-** <<dsa_offset>>
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
-#define SCR_NO_FLUSH2 0x02000000
-#define SCR_DSA_REL2 0x10000000
-
-#define SCR_LOAD_R(reg, how, n) \
- (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
-
-#define SCR_STORE_R(reg, how, n) \
- (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
-
-#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
-#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
-#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
-#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
-
-#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
-#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
-#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
-#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
-
-
-/*-----------------------------------------------------------
-**
-** Waiting for Disconnect or Reselect
-**
-**-----------------------------------------------------------
-**
-** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
-** <<address>>
-**
-** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
-** <<distance>>
-**
-** CALL [ | IFTRUE/IFFALSE ( ... ) ]
-** <<address>>
-**
-** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
-** <<distance>>
-**
-** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
-** <<dummy>>
-**
-** INT [ | IFTRUE/IFFALSE ( ... ) ]
-** <<ident>>
-**
-** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
-** <<ident>>
-**
-** Conditions:
-** WHEN (phase)
-** IF (phase)
-** CARRYSET
-** DATA (data, mask)
-**
-**-----------------------------------------------------------
-*/
-
-#define SCR_NO_OP 0x80000000
-#define SCR_JUMP 0x80080000
-#define SCR_JUMP64 0x80480000
-#define SCR_JUMPR 0x80880000
-#define SCR_CALL 0x88080000
-#define SCR_CALLR 0x88880000
-#define SCR_RETURN 0x90080000
-#define SCR_INT 0x98080000
-#define SCR_INT_FLY 0x98180000
-
-#define IFFALSE(arg) (0x00080000 | (arg))
-#define IFTRUE(arg) (0x00000000 | (arg))
-
-#define WHEN(phase) (0x00030000 | (phase))
-#define IF(phase) (0x00020000 | (phase))
-
-#define DATA(D) (0x00040000 | ((D) & 0xff))
-#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
-
-#define CARRYSET (0x00200000)
-
-
-#define SIR_COMPLETE 0x10000000
-/* script errors */
-#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
-#define SIR_CMD_OUT_ILL_PH 0x00000002
-#define SIR_STATUS_ILL_PH 0x00000003
-#define SIR_MSG_RECEIVED 0x00000004
-#define SIR_DATA_IN_ERR 0x00000005
-#define SIR_DATA_OUT_ERR 0x00000006
-#define SIR_SCRIPT_ERROR 0x00000007
-#define SIR_MSG_OUT_NO_CMD 0x00000008
-#define SIR_MSG_OVER7 0x00000009
-/* Fly interrupt */
-#define INT_ON_FY 0x00000080
-
-/* Hardware errors are defined in scsi.h */
-
-#define SCSI_IDENTIFY 0xC0
-
-#endif
diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h
deleted file mode 100644
index 6bb5cff..0000000
--- a/include/synopsys/dwcddr21mctl.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011 Andes Technology Corp
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-/*
- * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
- */
-#ifndef __DWCDDR21MCTL_H
-#define __DWCDDR21MCTL_H
-
-#ifndef __ASSEMBLY__
-struct dwcddr21mctl {
- unsigned int ccr; /* Controller Configuration */
- unsigned int dcr; /* DRAM Configuration */
- unsigned int iocr; /* I/O Configuration */
- unsigned int csr; /* Controller Status */
- unsigned int drr; /* DRAM refresh */
- unsigned int tpr0; /* SDRAM Timing Parameters 0 */
- unsigned int tpr1; /* SDRAM Timing Parameters 1 */
- unsigned int tpr2; /* SDRAM Timing Parameters 2 */
- unsigned int gdllcr; /* Global DLL Control */
- unsigned int dllcr[10]; /* DLL Control */
- unsigned int rslr[4]; /* Rank System Lantency */
- unsigned int rdgr[4]; /* Rank DQS Gating */
- unsigned int dqtr[9]; /* DQ Timing */
- unsigned int dqstr; /* DQS Timing */
- unsigned int dqsbtr; /* DQS_b Timing */
- unsigned int odtcr; /* ODT Configuration */
- unsigned int dtr[2]; /* Data Training */
- unsigned int dtar; /* Data Training Address */
- unsigned int rsved[82]; /* Reserved */
- unsigned int mr; /* Mode Register */
- unsigned int emr; /* Extended Mode Register */
- unsigned int emr2; /* Extended Mode Register 2 */
- unsigned int emr3; /* Extended Mode Register 3 */
- unsigned int hpcr[32]; /* Host Port Configurarion */
- unsigned int pqcr[8]; /* Priority Queue Configuration */
- unsigned int mmgcr; /* Memory Manager General Config */
-};
-#endif /* __ASSEMBLY__ */
-
-/*
- * Control Configuration Register
- */
-#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
-#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
-#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
-#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
-#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
-#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
-#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
-#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
-#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
-#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
-#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
-#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
-#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
-#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
-
-/*
- * DRAM Configuration Register
- */
-#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
-#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
-#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
-#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
-#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
-#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
-#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
-#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
-#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
-
-/*
- * I/O Configuration Register
- */
-#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
-#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
-#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
-#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
-#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
-#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
-#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
-
-/*
- * Controller Status Register
- */
-#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
-#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
-#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
-#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
-#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
-#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
-
-/*
- * DRAM Refresh Register
- */
-#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
-#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
-#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
-#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
-
-/*
- * SDRAM Timing Parameters Register 0
- */
-#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
-#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
-#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
-#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
-#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
-#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
-#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
-#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
-#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
-
-/*
- * SDRAM Timing Parameters Register 1
- */
-#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
-#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
-#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
-#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
-#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
-#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
-#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
-#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
-
-/*
- * SDRAM Timing Parameters Register 2
- */
-#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
-#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
-#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
-
-/*
- * Global DLL Control Register
- */
-#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
-#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
-#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
-#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
-#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
-#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
-#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
-#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
-#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
-
-/*
- * DLL Control Register 0-9
- */
-#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
-#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
-#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
-#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
-#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
-#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
-#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
-
-/*
- * Rank System Lantency Register
- */
-#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
-#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
-#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
-#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
-#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
-#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
-#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
-#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
-#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
-
-/*
- * Rank DQS Gating Register
- */
-#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
-#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
-#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
-#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
-#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
-#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
-#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
-#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
-#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
-
-/*
- * DQ Timing Register
- */
-#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
-#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
-#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
-#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
-#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
-#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
-#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
-#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
-
-/*
- * DQS Timing Register
- */
-#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
-#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
-#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
-#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
-#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
-#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
-#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
-
-/*
- * DQS_b (DQSBTR) Timing Register
- */
-#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
-#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
-
-/*
- * ODT Configuration Register
- */
-#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
-#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
-#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
-#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
-#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
-#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
-#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
-#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
-
-/*
- * Data Training Register
- */
-#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
-#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
-#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
-#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
-
-#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
-#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
-#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
-#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
-
-/*
- * Data Training Address Register
- */
-#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
-#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
-#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
-
-/*
- * Mode Register
- */
-#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
-#define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
-#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
-#define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
-#define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
-#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
-#define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
-
-/*
- * Extended Mode register
- */
-#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
-#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
-#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
-#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
-#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
-#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
-#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
-#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
-#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
-
-#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
-#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
-
-#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0))
-#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1))
-#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0))
-#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1))
-
-/*
- * Extended Mode register 2
- */
-#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
-#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
-#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
-
-/*
- * Extended Mode register 3: [15:0] reserved for JEDEC.
- */
-
-/*
- * Host port Configuration register 0-31
- */
-#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
-
-/*
- * Priority Queue Configuration register 0-7
- */
-#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
-#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
-#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
-#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
-#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
-#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
-#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
-
-/*
- * Memory Manager General Configuration register
- */
-#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
-
-#endif /* __DWCDDR21MCTL_H */
diff --git a/include/version_string.h b/include/version_string.h
index a89a6e4..a7d07e4 100644
--- a/include/version_string.h
+++ b/include/version_string.h
@@ -4,5 +4,7 @@
#define __VERSION_STRING_H__
extern const char version_string[];
+extern const unsigned short version_num;
+extern const unsigned char version_num_patch;
#endif /* __VERSION_STRING_H__ */
diff --git a/include/video_easylogo.h b/include/video_easylogo.h
deleted file mode 100644
index ce93868..0000000
--- a/include/video_easylogo.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
-** video easylogo
-** ==============
-** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
-** AIRVENT SAM s.p.a - RIMINI(ITALY)
-**
-** This utility is still under construction!
-*/
-
-#ifndef _EASYLOGO_H_
-#define _EASYLOGO_H_
-
-#if 0
-#define ENABLE_ASCII_BANNERS
-#endif
-
-typedef struct {
- unsigned char *data;
- int width;
- int height;
- int bpp;
- int pixel_size;
- int size;
-} fastimage_t ;
-
-#endif /* _EASYLOGO_H_ */
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index 7c4189e..a8d4b47 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -11,8 +11,7 @@
#include <log.h>
#include <mapmem.h>
#include <tables_csum.h>
-#include <timestamp.h>
-#include <version.h>
+#include <version_string.h>
#include <acpi/acpi_table.h>
#include <asm/global_data.h>
#include <dm/acpi.h>
@@ -25,12 +24,12 @@
* to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to
* value 0x20210401.
*/
-#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \
- (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \
- (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \
- ((U_BOOT_VERSION_NUM % 10) << 16) | \
- (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \
- ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \
+#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \
+ (((version_num / 100) % 10) << 24) | \
+ (((version_num / 10) % 10) << 20) | \
+ ((version_num % 10) << 16) | \
+ (((version_num_patch / 10) % 10) << 12) | \
+ ((version_num_patch % 10) << 8) | \
0x01)
int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags)
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 13a35ea..1a8c8d7 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -23,6 +23,7 @@
ifdef CONFIG_RISCV
always += boothart.efi
+targets += boothart.o
endif
ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
@@ -32,10 +33,12 @@
ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
always += dtbdump.efi
+targets += dtbdump.o
endif
ifdef CONFIG_EFI_LOAD_FILE2_INITRD
always += initrddump.efi
+targets += initrddump.o
endif
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 93e2b01..b557738 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -10,6 +10,7 @@
#include <charset.h>
#include <dfu.h>
#include <efi_loader.h>
+#include <efi_variable.h>
#include <fwu.h>
#include <image.h>
#include <signatures.h>
@@ -36,11 +37,52 @@
u32 lowest_supported_version;
};
+/**
+ * struct fmp_state - fmp firmware update state
+ *
+ * This structure describes the state of the firmware update
+ * through FMP protocol.
+ *
+ * @fw_version: Firmware versions used
+ * @lowest_supported_version: Lowest supported version
+ * @last_attempt_version: Last attempt version
+ * @last_attempt_status: Last attempt status
+ */
+struct fmp_state {
+ u32 fw_version;
+ u32 lowest_supported_version; /* not used */
+ u32 last_attempt_version; /* not used */
+ u32 last_attempt_status; /* not used */
+};
+
__weak void set_dfu_alt_info(char *interface, char *devstr)
{
env_set("dfu_alt_info", update_info.dfu_string);
}
+/**
+ * efi_firmware_get_image_type_id - get image_type_id
+ * @image_index: image index
+ *
+ * Return the image_type_id identified by the image index.
+ *
+ * Return: pointer to the image_type_id, NULL if image_index is invalid
+ */
+static
+efi_guid_t *efi_firmware_get_image_type_id(u8 image_index)
+{
+ int i;
+ struct efi_fw_image *fw_array;
+
+ fw_array = update_info.images;
+ for (i = 0; i < update_info.num_images; i++) {
+ if (fw_array[i].image_index == image_index)
+ return &fw_array[i].image_type_id;
+ }
+
+ return NULL;
+}
+
/* Place holder; not supported */
static
efi_status_t EFIAPI efi_firmware_get_image_unsupported(
@@ -103,6 +145,87 @@
}
/**
+ * efi_firmware_get_lsv_from_dtb - get lowest supported version from dtb
+ * @image_index: Image index
+ * @image_type_id: Image type id
+ * @lsv: Pointer to store the lowest supported version
+ *
+ * Read the firmware version information from dtb.
+ */
+static void efi_firmware_get_lsv_from_dtb(u8 image_index,
+ efi_guid_t *image_type_id, u32 *lsv)
+{
+ const void *fdt = gd->fdt_blob;
+ const fdt32_t *val;
+ const char *guid_str;
+ int len, offset, index;
+ int parent;
+
+ *lsv = 0;
+
+ parent = fdt_subnode_offset(fdt, 0, "firmware-version");
+ if (parent < 0)
+ return;
+
+ fdt_for_each_subnode(offset, fdt, parent) {
+ efi_guid_t guid;
+
+ guid_str = fdt_getprop(fdt, offset, "image-type-id", &len);
+ if (!guid_str)
+ continue;
+ uuid_str_to_bin(guid_str, guid.b, UUID_STR_FORMAT_GUID);
+
+ val = fdt_getprop(fdt, offset, "image-index", &len);
+ if (!val)
+ continue;
+ index = fdt32_to_cpu(*val);
+
+ if (!guidcmp(&guid, image_type_id) && index == image_index) {
+ val = fdt_getprop(fdt, offset,
+ "lowest-supported-version", &len);
+ if (val)
+ *lsv = fdt32_to_cpu(*val);
+ }
+ }
+}
+
+/**
+ * efi_firmware_fill_version_info - fill the version information
+ * @image_info: Image information
+ * @fw_array: Pointer to size of new image
+ *
+ * Fill the version information into image_info strucrure.
+ *
+ */
+static
+void efi_firmware_fill_version_info(struct efi_firmware_image_descriptor *image_info,
+ struct efi_fw_image *fw_array)
+{
+ u16 varname[13]; /* u"FmpStateXXXX" */
+ efi_status_t ret;
+ efi_uintn_t size;
+ struct fmp_state var_state = { 0 };
+
+ efi_create_indexed_name(varname, sizeof(varname), "FmpState",
+ fw_array->image_index);
+ size = sizeof(var_state);
+ ret = efi_get_variable_int(varname, &fw_array->image_type_id,
+ NULL, &size, &var_state, NULL);
+ if (ret == EFI_SUCCESS)
+ image_info->version = var_state.fw_version;
+ else
+ image_info->version = 0;
+
+ efi_firmware_get_lsv_from_dtb(fw_array->image_index,
+ &fw_array->image_type_id,
+ &image_info->lowest_supported_image_version);
+
+ image_info->version_name = NULL; /* not supported */
+ image_info->last_attempt_version = 0;
+ image_info->last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
+}
+
+/**
* efi_fill_image_desc_array - populate image descriptor array
* @image_info_size: Size of @image_info
* @image_info: Image information
@@ -131,7 +254,7 @@
struct efi_fw_image *fw_array;
int i;
- total_size = sizeof(*image_info) * num_image_type_guids;
+ total_size = sizeof(*image_info) * update_info.num_images;
if (*image_info_size < total_size) {
*image_info_size = total_size;
@@ -141,21 +264,20 @@
*image_info_size = total_size;
fw_array = update_info.images;
- *descriptor_count = num_image_type_guids;
+ *descriptor_count = update_info.num_images;
*descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION;
*descriptor_size = sizeof(*image_info);
*package_version = 0xffffffff; /* not supported */
*package_version_name = NULL; /* not supported */
- for (i = 0; i < num_image_type_guids; i++) {
+ for (i = 0; i < update_info.num_images; i++) {
image_info[i].image_index = fw_array[i].image_index;
image_info[i].image_type_id = fw_array[i].image_type_id;
image_info[i].image_id = fw_array[i].image_index;
-
image_info[i].image_id_name = fw_array[i].fw_name;
- image_info[i].version = 0; /* not supported */
- image_info[i].version_name = NULL; /* not supported */
+ efi_firmware_fill_version_info(&image_info[i], &fw_array[i]);
+
image_info[i].size = 0;
image_info[i].attributes_supported =
IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
@@ -168,9 +290,6 @@
image_info[0].attributes_setting |=
IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED;
- image_info[i].lowest_supported_image_version = 0;
- image_info[i].last_attempt_version = 0;
- image_info[i].last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
image_info[i].hardware_instance = 1;
image_info[i].dependencies = NULL;
}
@@ -194,8 +313,6 @@
{
const void *image = *p_image;
efi_uintn_t image_size = *p_image_size;
- u32 fmp_hdr_signature;
- struct fmp_payload_header *header;
void *capsule_payload;
efi_status_t status;
efi_uintn_t capsule_payload_size;
@@ -222,27 +339,122 @@
debug("Updating capsule without authenticating.\n");
}
- fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE;
- header = (void *)image;
-
- if (!memcmp(&header->signature, &fmp_hdr_signature,
- sizeof(fmp_hdr_signature))) {
- /*
- * When building the capsule with the scripts in
- * edk2, a FMP header is inserted above the capsule
- * payload. Compensate for this header to get the
- * actual payload that is to be updated.
- */
- image += header->header_size;
- image_size -= header->header_size;
- }
-
*p_image = image;
*p_image_size = image_size;
return EFI_SUCCESS;
}
/**
+ * efi_firmware_set_fmp_state_var - set FmpStateXXXX variable
+ * @state: Pointer to fmp state
+ * @image_index: image index
+ *
+ * Update the FmpStateXXXX variable with the firmware update state.
+ *
+ * Return: status code
+ */
+static
+efi_status_t efi_firmware_set_fmp_state_var(struct fmp_state *state, u8 image_index)
+{
+ u16 varname[13]; /* u"FmpStateXXXX" */
+ efi_status_t ret;
+ efi_guid_t *image_type_id;
+ struct fmp_state var_state = { 0 };
+
+ image_type_id = efi_firmware_get_image_type_id(image_index);
+ if (!image_type_id)
+ return EFI_INVALID_PARAMETER;
+
+ efi_create_indexed_name(varname, sizeof(varname), "FmpState",
+ image_index);
+
+ /*
+ * Only the fw_version is set here.
+ * lowest_supported_version in FmpState variable is ignored since
+ * it can be tampered if the file based EFI variable storage is used.
+ */
+ var_state.fw_version = state->fw_version;
+
+ ret = efi_set_variable_int(varname, image_type_id,
+ EFI_VARIABLE_READ_ONLY |
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof(var_state), &var_state, false);
+
+ return ret;
+}
+
+/**
+ * efi_firmware_get_fw_version - get fw_version from FMP payload header
+ * @p_image: Pointer to new image
+ * @p_image_size: Pointer to size of new image
+ * @state: Pointer to fmp state
+ *
+ * Parse the FMP payload header and fill the fmp_state structure.
+ * If no FMP payload header is found, fmp_state structure is not updated.
+ *
+ */
+static void efi_firmware_get_fw_version(const void **p_image,
+ efi_uintn_t *p_image_size,
+ struct fmp_state *state)
+{
+ const struct fmp_payload_header *header;
+ u32 fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE;
+
+ header = *p_image;
+ if (header->signature == fmp_hdr_signature) {
+ /* FMP header is inserted above the capsule payload */
+ state->fw_version = header->fw_version;
+
+ *p_image += header->header_size;
+ *p_image_size -= header->header_size;
+ }
+}
+
+/**
+ * efi_firmware_verify_image - verify image
+ * @p_image: Pointer to new image
+ * @p_image_size: Pointer to size of new image
+ * @image_index: Image index
+ * @state: Pointer to fmp state
+ *
+ * Verify the capsule authentication and check if the fw_version
+ * is equal or greater than the lowest supported version.
+ *
+ * Return: status code
+ */
+static
+efi_status_t efi_firmware_verify_image(const void **p_image,
+ efi_uintn_t *p_image_size,
+ u8 image_index,
+ struct fmp_state *state)
+{
+ u32 lsv;
+ efi_status_t ret;
+ efi_guid_t *image_type_id;
+
+ ret = efi_firmware_capsule_authenticate(p_image, p_image_size);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ efi_firmware_get_fw_version(p_image, p_image_size, state);
+
+ image_type_id = efi_firmware_get_image_type_id(image_index);
+ if (!image_type_id)
+ return EFI_INVALID_PARAMETER;
+
+ efi_firmware_get_lsv_from_dtb(image_index, image_type_id, &lsv);
+ if (state->fw_version < lsv) {
+ log_err("Firmware version %u too low. Expecting >= %u. Aborting update\n",
+ state->fw_version, lsv);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return ret;
+}
+
+/**
* efi_firmware_get_image_info - return information about the current
* firmware image
* @this: Protocol instance
@@ -331,6 +543,7 @@
u16 **abort_reason)
{
efi_status_t status;
+ struct fmp_state state = { 0 };
EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
@@ -338,13 +551,16 @@
if (!image || image_index != 1)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- status = efi_firmware_capsule_authenticate(&image, &image_size);
+ status = efi_firmware_verify_image(&image, &image_size, image_index,
+ &state);
if (status != EFI_SUCCESS)
return EFI_EXIT(status);
if (fit_update(image))
return EFI_EXIT(EFI_DEVICE_ERROR);
+ efi_firmware_set_fmp_state_var(&state, image_index);
+
return EFI_EXIT(EFI_SUCCESS);
}
@@ -392,6 +608,7 @@
{
int ret;
efi_status_t status;
+ struct fmp_state state = { 0 };
EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
@@ -399,7 +616,8 @@
if (!image)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- status = efi_firmware_capsule_authenticate(&image, &image_size);
+ status = efi_firmware_verify_image(&image, &image_size, image_index,
+ &state);
if (status != EFI_SUCCESS)
return EFI_EXIT(status);
@@ -419,6 +637,8 @@
NULL, NULL))
return EFI_EXIT(EFI_DEVICE_ERROR);
+ efi_firmware_set_fmp_state_var(&state, image_index);
+
return EFI_EXIT(EFI_SUCCESS);
}
diff --git a/lib/fwu_updates/Makefile b/lib/fwu_updates/Makefile
index 1993088..c9e3c06 100644
--- a/lib/fwu_updates/Makefile
+++ b/lib/fwu_updates/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu.o
obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_gpt.o
+obj-$(CONFIG_FWU_MDATA_MTD) += fwu_mtd.o
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index 5313d07..cd5c3b6 100644
--- a/lib/fwu_updates/fwu.c
+++ b/lib/fwu_updates/fwu.c
@@ -15,13 +15,13 @@
#include <linux/errno.h>
#include <linux/types.h>
+#include <u-boot/crc.h>
+
+static struct fwu_mdata g_mdata; /* = {0} makes uninit crc32 always invalid */
+static struct udevice *g_dev;
static u8 in_trial;
static u8 boottime_check;
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <u-boot/crc.h>
-
enum {
IMAGE_ACCEPT_SET = 1,
IMAGE_ACCEPT_CLEAR,
@@ -33,26 +33,6 @@
BOTH_PARTS,
};
-static int fwu_get_dev_mdata(struct udevice **dev, struct fwu_mdata *mdata)
-{
- int ret;
-
- ret = uclass_first_device_err(UCLASS_FWU_MDATA, dev);
- if (ret) {
- log_debug("Cannot find fwu device\n");
- return ret;
- }
-
- if (!mdata)
- return 0;
-
- ret = fwu_get_mdata(*dev, mdata);
- if (ret < 0)
- log_debug("Unable to get valid FWU metadata\n");
-
- return ret;
-}
-
static int trial_counter_update(u16 *trial_state_ctr)
{
bool delete;
@@ -151,7 +131,7 @@
index = *image_index;
image = update_info.images;
- for (i = 0; i < num_image_type_guids; i++) {
+ for (i = 0; i < update_info.num_images; i++) {
if (index == image[i].image_index) {
guidcpy(image_type_id, &image[i].image_type_id);
return 0;
@@ -162,133 +142,124 @@
}
/**
- * fwu_verify_mdata() - Verify the FWU metadata
+ * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided
* @mdata: FWU metadata structure
- * @pri_part: FWU metadata partition is primary or secondary
- *
- * Verify the FWU metadata by computing the CRC32 for the metadata
- * structure and comparing it against the CRC32 value stored as part
- * of the structure.
+ * @part: Bitmask of FWU metadata partitions to be written to
*
* Return: 0 if OK, -ve on error
- *
*/
-int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part)
+static int fwu_sync_mdata(struct fwu_mdata *mdata, int part)
{
- u32 calc_crc32;
- void *buf;
+ void *buf = &mdata->version;
+ int err;
- buf = &mdata->version;
- calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
-
- if (calc_crc32 != mdata->crc32) {
- log_debug("crc32 check failed for %s FWU metadata partition\n",
- pri_part ? "primary" : "secondary");
- return -EINVAL;
+ if (part == BOTH_PARTS) {
+ err = fwu_sync_mdata(mdata, SECONDARY_PART);
+ if (err)
+ return err;
+ part = PRIMARY_PART;
}
+ /*
+ * Calculate the crc32 for the updated FWU metadata
+ * and put the updated value in the FWU metadata crc32
+ * field
+ */
+ mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+
+ err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART);
+ if (err) {
+ log_err("Unable to write %s mdata\n",
+ part == PRIMARY_PART ? "primary" : "secondary");
+ return err;
+ }
+
+ /* update the cached copy of meta-data */
+ memcpy(&g_mdata, mdata, sizeof(struct fwu_mdata));
+
return 0;
}
+static inline int mdata_crc_check(struct fwu_mdata *mdata)
+{
+ void *buf = &mdata->version;
+ u32 calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+
+ return calc_crc32 == mdata->crc32 ? 0 : -EINVAL;
+}
+
/**
- * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies
+ * fwu_get_mdata() - Read, verify and return the FWU metadata
+ * @mdata: Output FWU metadata read or NULL
*
* Read both the metadata copies from the storage media, verify their checksum,
* and ascertain that both copies match. If one of the copies has gone bad,
* restore it from the good copy.
*
* Return: 0 if OK, -ve on error
- *
*/
-int fwu_check_mdata_validity(void)
+int fwu_get_mdata(struct fwu_mdata *mdata)
{
- int ret;
- struct udevice *dev;
- struct fwu_mdata pri_mdata;
- struct fwu_mdata secondary_mdata;
- uint mdata_parts[2];
- uint valid_partitions, invalid_partitions;
+ int err;
+ bool parts_ok[2] = { false };
+ struct fwu_mdata s, *parts_mdata[2];
- ret = fwu_get_dev_mdata(&dev, NULL);
- if (ret)
- return ret;
+ parts_mdata[0] = &g_mdata;
+ parts_mdata[1] = &s;
- /*
- * Check if the platform has defined its own
- * function to check the metadata partitions'
- * validity. If so, that takes precedence.
- */
- ret = fwu_mdata_check(dev);
- if (!ret || ret != -ENOSYS)
- return ret;
+ /* if mdata already read and ready */
+ err = mdata_crc_check(parts_mdata[0]);
+ if (!err)
+ goto ret_mdata;
+ /* else read, verify and, if needed, fix mdata */
- /*
- * Two FWU metadata partitions are expected.
- * If we don't have two, user needs to create
- * them first
- */
- valid_partitions = 0;
- ret = fwu_get_mdata_part_num(dev, mdata_parts);
- if (ret < 0) {
- log_debug("Error getting the FWU metadata partitions\n");
- return -ENOENT;
+ for (int i = 0; i < 2; i++) {
+ parts_ok[i] = false;
+ err = fwu_read_mdata(g_dev, parts_mdata[i], !i);
+ if (!err) {
+ err = mdata_crc_check(parts_mdata[i]);
+ if (!err)
+ parts_ok[i] = true;
+ else
+ log_debug("mdata : %s crc32 failed\n", i ? "secondary" : "primary");
+ }
}
- ret = fwu_read_mdata_partition(dev, &pri_mdata, mdata_parts[0]);
- if (!ret) {
- ret = fwu_verify_mdata(&pri_mdata, 1);
- if (!ret)
- valid_partitions |= PRIMARY_PART;
- }
-
- ret = fwu_read_mdata_partition(dev, &secondary_mdata, mdata_parts[1]);
- if (!ret) {
- ret = fwu_verify_mdata(&secondary_mdata, 0);
- if (!ret)
- valid_partitions |= SECONDARY_PART;
- }
-
- if (valid_partitions == (PRIMARY_PART | SECONDARY_PART)) {
+ if (parts_ok[0] && parts_ok[1]) {
/*
* Before returning, check that both the
- * FWU metadata copies are the same. If not,
- * populate the secondary partition from the
+ * FWU metadata copies are the same.
+ */
+ err = memcmp(parts_mdata[0], parts_mdata[1], sizeof(struct fwu_mdata));
+ if (!err)
+ goto ret_mdata;
+
+ /*
+ * If not, populate the secondary partition from the
* primary partition copy.
*/
- if (!memcmp(&pri_mdata, &secondary_mdata,
- sizeof(struct fwu_mdata))) {
- ret = 0;
- } else {
- log_info("Both FWU metadata copies are valid but do not match.");
- log_info(" Restoring the secondary partition from the primary\n");
- ret = fwu_write_mdata_partition(dev, &pri_mdata,
- mdata_parts[1]);
- if (ret)
- log_debug("Restoring secondary FWU metadata partition failed\n");
+ log_info("Both FWU metadata copies are valid but do not match.");
+ log_info(" Restoring the secondary partition from the primary\n");
+ parts_ok[1] = false;
+ }
+
+ for (int i = 0; i < 2; i++) {
+ if (parts_ok[i])
+ continue;
+
+ memcpy(parts_mdata[i], parts_mdata[1 - i], sizeof(struct fwu_mdata));
+ err = fwu_sync_mdata(parts_mdata[i], i ? SECONDARY_PART : PRIMARY_PART);
+ if (err) {
+ log_debug("mdata : %s write failed\n", i ? "secondary" : "primary");
+ return err;
}
- goto out;
}
- if (!(valid_partitions & BOTH_PARTS)) {
- log_info("Both FWU metadata partitions invalid\n");
- ret = -EBADMSG;
- goto out;
- }
+ret_mdata:
+ if (!err && mdata)
+ memcpy(mdata, parts_mdata[0], sizeof(struct fwu_mdata));
- invalid_partitions = valid_partitions ^ BOTH_PARTS;
- ret = fwu_write_mdata_partition(dev,
- (invalid_partitions == PRIMARY_PART) ?
- &secondary_mdata : &pri_mdata,
- (invalid_partitions == PRIMARY_PART) ?
- mdata_parts[0] : mdata_parts[1]);
-
- if (ret)
- log_debug("Restoring %s FWU metadata partition failed\n",
- (invalid_partitions == PRIMARY_PART) ?
- "primary" : "secondary");
-
-out:
- return ret;
+ return err;
}
/**
@@ -303,19 +274,14 @@
*/
int fwu_get_active_index(uint *active_idx)
{
- int ret;
- struct udevice *dev;
- struct fwu_mdata mdata = { 0 };
-
- ret = fwu_get_dev_mdata(&dev, &mdata);
- if (ret)
- return ret;
+ int ret = 0;
+ struct fwu_mdata *mdata = &g_mdata;
/*
* Found the FWU metadata partition, now read the active_index
* value
*/
- *active_idx = mdata.active_index;
+ *active_idx = mdata->active_index;
if (*active_idx >= CONFIG_FWU_NUM_BANKS) {
log_debug("Active index value read is incorrect\n");
ret = -EINVAL;
@@ -336,30 +302,25 @@
int fwu_set_active_index(uint active_idx)
{
int ret;
- struct udevice *dev;
- struct fwu_mdata mdata = { 0 };
+ struct fwu_mdata *mdata = &g_mdata;
if (active_idx >= CONFIG_FWU_NUM_BANKS) {
log_debug("Invalid active index value\n");
return -EINVAL;
}
- ret = fwu_get_dev_mdata(&dev, &mdata);
- if (ret)
- return ret;
-
/*
* Update the active index and previous_active_index fields
* in the FWU metadata
*/
- mdata.previous_active_index = mdata.active_index;
- mdata.active_index = active_idx;
+ mdata->previous_active_index = mdata->active_index;
+ mdata->active_index = active_idx;
/*
* Now write this updated FWU metadata to both the
* FWU metadata partitions
*/
- ret = fwu_update_mdata(dev, &mdata);
+ ret = fwu_sync_mdata(mdata, BOTH_PARTS);
if (ret) {
log_debug("Failed to update FWU metadata partitions\n");
ret = -EIO;
@@ -389,15 +350,10 @@
u8 alt_num;
uint update_bank;
efi_guid_t *image_guid, image_type_id;
- struct udevice *dev;
- struct fwu_mdata mdata = { 0 };
+ struct fwu_mdata *mdata = &g_mdata;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_bank_info;
- ret = fwu_get_dev_mdata(&dev, &mdata);
- if (ret)
- return ret;
-
ret = fwu_plat_get_update_index(&update_bank);
if (ret) {
log_debug("Failed to get the FWU update bank\n");
@@ -418,11 +374,11 @@
*/
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
if (!guidcmp(&image_type_id,
- &mdata.img_entry[i].image_type_uuid)) {
- img_entry = &mdata.img_entry[i];
+ &mdata->img_entry[i].image_type_uuid)) {
+ img_entry = &mdata->img_entry[i];
img_bank_info = &img_entry->img_bank_info[update_bank];
image_guid = &img_bank_info->image_uuid;
- ret = fwu_plat_get_alt_num(dev, image_guid, &alt_num);
+ ret = fwu_plat_get_alt_num(g_dev, image_guid, &alt_num);
if (ret) {
log_debug("alt_num not found for partition with GUID %pUs\n",
image_guid);
@@ -436,8 +392,8 @@
}
}
- log_debug("Partition with the image type %pUs not found\n",
- &image_type_id);
+ log_err("Partition with the image type %pUs not found\n",
+ &image_type_id);
out:
return ret;
@@ -457,26 +413,21 @@
{
int ret;
u32 cur_active_index;
- struct udevice *dev;
- struct fwu_mdata mdata = { 0 };
-
- ret = fwu_get_dev_mdata(&dev, &mdata);
- if (ret)
- return ret;
+ struct fwu_mdata *mdata = &g_mdata;
/*
* Swap the active index and previous_active_index fields
* in the FWU metadata
*/
- cur_active_index = mdata.active_index;
- mdata.active_index = mdata.previous_active_index;
- mdata.previous_active_index = cur_active_index;
+ cur_active_index = mdata->active_index;
+ mdata->active_index = mdata->previous_active_index;
+ mdata->previous_active_index = cur_active_index;
/*
* Now write this updated FWU metadata to both the
* FWU metadata partitions
*/
- ret = fwu_update_mdata(dev, &mdata);
+ ret = fwu_sync_mdata(mdata, BOTH_PARTS);
if (ret) {
log_debug("Failed to update FWU metadata partitions\n");
ret = -EIO;
@@ -503,16 +454,11 @@
static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action)
{
int ret, i;
- struct udevice *dev;
- struct fwu_mdata mdata = { 0 };
+ struct fwu_mdata *mdata = &g_mdata;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_bank_info;
- ret = fwu_get_dev_mdata(&dev, &mdata);
- if (ret)
- return ret;
-
- img_entry = &mdata.img_entry[0];
+ img_entry = &mdata->img_entry[0];
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
if (!guidcmp(&img_entry[i].image_type_uuid, img_type_id)) {
img_bank_info = &img_entry[i].img_bank_info[bank];
@@ -521,7 +467,7 @@
else
img_bank_info->accepted = 0;
- ret = fwu_update_mdata(dev, &mdata);
+ ret = fwu_sync_mdata(mdata, BOTH_PARTS);
goto out;
}
}
@@ -600,6 +546,24 @@
}
/**
+ * fwu_plat_get_bootidx() - Get the value of the boot index
+ * @boot_idx: Boot index value
+ *
+ * Get the value of the bank(partition) from which the platform
+ * has booted. This value is passed to U-Boot from the earlier
+ * stage bootloader which loads and boots all the relevant
+ * firmware images
+ */
+__weak void fwu_plat_get_bootidx(uint *boot_idx)
+{
+ int ret;
+
+ ret = fwu_get_active_index(boot_idx);
+ if (ret < 0)
+ *boot_idx = 0; /* Dummy value */
+}
+
+/**
* fwu_update_checks_pass() - Check if FWU update can be done
*
* Check if the FWU update can be executed. The updates are
@@ -656,8 +620,6 @@
{
int ret;
u32 boot_idx, active_idx;
- struct udevice *dev;
- struct fwu_mdata mdata = { 0 };
/* Don't have boot time checks on sandbox */
if (IS_ENABLED(CONFIG_SANDBOX)) {
@@ -665,9 +627,17 @@
return 0;
}
- ret = fwu_check_mdata_validity();
- if (ret)
- return 0;
+ ret = uclass_first_device_err(UCLASS_FWU_MDATA, &g_dev);
+ if (ret) {
+ log_debug("Cannot find fwu device\n");
+ return ret;
+ }
+
+ ret = fwu_get_mdata(NULL);
+ if (ret) {
+ log_debug("Unable to read meta-data\n");
+ return ret;
+ }
/*
* Get the Boot Index, i.e. the bank from
@@ -703,11 +673,7 @@
if (efi_init_obj_list() != EFI_SUCCESS)
return 0;
- ret = fwu_get_dev_mdata(&dev, &mdata);
- if (ret)
- return ret;
-
- in_trial = in_trial_state(&mdata);
+ in_trial = in_trial_state(&g_mdata);
if (!in_trial || (ret = fwu_trial_count_update()) > 0)
ret = trial_counter_update(NULL);
diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c
new file mode 100644
index 0000000..b73111a
--- /dev/null
+++ b/lib/fwu_updates/fwu_mtd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <dm.h>
+#include <dfu.h>
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <log.h>
+#include <malloc.h>
+#include <mtd.h>
+#include <uuid.h>
+#include <vsprintf.h>
+
+#include <dm/ofnode.h>
+
+struct fwu_mtd_image_info
+fwu_mtd_images[CONFIG_FWU_NUM_BANKS * CONFIG_FWU_NUM_IMAGES_PER_BANK];
+
+static struct fwu_mtd_image_info *mtd_img_by_uuid(const char *uuidbuf)
+{
+ int num_images = ARRAY_SIZE(fwu_mtd_images);
+
+ for (int i = 0; i < num_images; i++)
+ if (!strcmp(uuidbuf, fwu_mtd_images[i].uuidbuf))
+ return &fwu_mtd_images[i];
+
+ return NULL;
+}
+
+int fwu_mtd_get_alt_num(efi_guid_t *image_id, u8 *alt_num,
+ const char *mtd_dev)
+{
+ struct fwu_mtd_image_info *mtd_img_info;
+ char uuidbuf[UUID_STR_LEN + 1];
+ fdt_addr_t offset, size = 0;
+ struct dfu_entity *dfu;
+ int i, nalt, ret;
+
+ mtd_probe_devices();
+
+ uuid_bin_to_str(image_id->b, uuidbuf, UUID_STR_FORMAT_STD);
+
+ mtd_img_info = mtd_img_by_uuid(uuidbuf);
+ if (!mtd_img_info) {
+ log_err("%s: Not found partition for image %s\n", __func__, uuidbuf);
+ return -ENOENT;
+ }
+
+ offset = mtd_img_info->start;
+ size = mtd_img_info->size;
+
+ ret = dfu_init_env_entities(NULL, NULL);
+ if (ret)
+ return -ENOENT;
+
+ nalt = 0;
+ list_for_each_entry(dfu, &dfu_list, list)
+ nalt++;
+
+ if (!nalt) {
+ log_warning("No entities in dfu_alt_info\n");
+ dfu_free_entities();
+ return -ENOENT;
+ }
+
+ ret = -ENOENT;
+ for (i = 0; i < nalt; i++) {
+ dfu = dfu_get_entity(i);
+
+ /* Only MTD RAW access */
+ if (!dfu || dfu->dev_type != DFU_DEV_MTD ||
+ dfu->layout != DFU_RAW_ADDR ||
+ dfu->data.mtd.start != offset ||
+ dfu->data.mtd.size != size)
+ continue;
+
+ *alt_num = dfu->alt;
+ ret = 0;
+ break;
+ }
+
+ dfu_free_entities();
+
+ log_debug("%s: %s -> %d\n", __func__, uuidbuf, *alt_num);
+ return ret;
+}
+
+/**
+ * fwu_plat_get_alt_num() - Get the DFU Alt Num for the image from the platform
+ * @dev: FWU device
+ * @image_id: Image GUID for which DFU alt number needs to be retrieved
+ * @alt_num: Pointer to the alt_num
+ *
+ * Get the DFU alt number from the platform for the image specified by the
+ * image GUID.
+ *
+ * Note: This is a weak function and platforms can override this with
+ * their own implementation for obtaining the alt number value.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+__weak int fwu_plat_get_alt_num(struct udevice *dev, efi_guid_t *image_id,
+ u8 *alt_num)
+{
+ return fwu_mtd_get_alt_num(image_id, alt_num, "nor1");
+}
+
+static int gen_image_alt_info(char *buf, size_t len, int sidx,
+ struct fwu_image_entry *img, struct mtd_info *mtd)
+{
+ char *p = buf, *end = buf + len;
+ int i;
+
+ p += snprintf(p, end - p, "mtd %s", mtd->name);
+ if (end < p) {
+ log_err("%s:%d Run out of buffer\n", __func__, __LINE__);
+ return -E2BIG;
+ }
+
+ /*
+ * List the image banks in the FWU mdata and search the corresponding
+ * partition based on partition's uuid.
+ */
+ for (i = 0; i < CONFIG_FWU_NUM_BANKS; i++) {
+ struct fwu_mtd_image_info *mtd_img_info;
+ struct fwu_image_bank_info *bank;
+ char uuidbuf[UUID_STR_LEN + 1];
+ u32 offset, size;
+
+ /* Query a partition by image UUID */
+ bank = &img->img_bank_info[i];
+ uuid_bin_to_str(bank->image_uuid.b, uuidbuf, UUID_STR_FORMAT_STD);
+
+ mtd_img_info = mtd_img_by_uuid(uuidbuf);
+ if (!mtd_img_info) {
+ log_err("%s: Not found partition for image %s\n", __func__, uuidbuf);
+ break;
+ }
+
+ offset = mtd_img_info->start;
+ size = mtd_img_info->size;
+
+ p += snprintf(p, end - p, "%sbank%d raw %x %x",
+ i == 0 ? "=" : ";", i, offset, size);
+ if (end < p) {
+ log_err("%s:%d Run out of buffer\n", __func__, __LINE__);
+ return -E2BIG;
+ }
+ }
+
+ if (i == CONFIG_FWU_NUM_BANKS)
+ return 0;
+
+ return -ENOENT;
+}
+
+int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd)
+{
+ struct fwu_mdata mdata;
+ int i, l, ret;
+
+ ret = fwu_get_mdata(&mdata);
+ if (ret < 0) {
+ log_err("Failed to get the FWU mdata.\n");
+ return ret;
+ }
+
+ for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
+ ret = gen_image_alt_info(buf, len, i * CONFIG_FWU_NUM_BANKS,
+ &mdata.img_entry[i], mtd);
+ if (ret)
+ break;
+
+ l = strlen(buf);
+ /* Replace the last ';' with '&' if there is another image. */
+ if (i != CONFIG_FWU_NUM_IMAGES_PER_BANK - 1 && l)
+ buf[l - 1] = '&';
+ len -= l;
+ buf += l;
+ }
+
+ return ret;
+}
diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts
index 2561025..5e2429c 100644
--- a/scripts/Makefile.dts
+++ b/scripts/Makefile.dts
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_$(SPL_)OF_LIST)))
+dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST)))
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 7b27224..f5ab7af 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -186,7 +186,7 @@
# Modified for U-Boot
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
$(UBOOTINCLUDE) \
- -I$(srctree)/arch/$(ARCH)/dts \
+ -I$(dir $<) \
-I$(srctree)/arch/$(ARCH)/dts/include \
-I$(srctree)/include \
-D__ASSEMBLY__ \
@@ -331,7 +331,7 @@
; \
sed "s:$(pre-tmp):$(<):" $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
-$(obj)/%.dtb: $(src)/%.dts FORCE
+$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE
$(call if_changed_dep,dtc)
pre-tmp = $(subst $(comma),_,$(dot-target).pre.tmp)
@@ -351,7 +351,10 @@
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
-$(obj)/%.dtbo: $(src)/%.dts FORCE
+$(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
+ $(call if_changed_dep,dtco)
+
+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
$(call if_changed_dep,dtco)
# Fonts
diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh
index bfb514e..53ff868 100755
--- a/scripts/dtc-version.sh
+++ b/scripts/dtc-version.sh
@@ -20,7 +20,7 @@
exit 1
fi
-MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1)
+MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1 | tr -d v)
MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2)
PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1)
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 9634fc2..818f715 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -11,10 +11,8 @@
#include <dm.h>
#include <malloc.h>
#include <mapmem.h>
-#include <timestamp.h>
-#include <version.h>
#include <tables_csum.h>
-#include <version.h>
+#include <version_string.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_device.h>
#include <acpi/acpi_table.h>
@@ -26,12 +24,12 @@
#define BUF_SIZE 4096
-#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \
- (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \
- (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \
- ((U_BOOT_VERSION_NUM % 10) << 16) | \
- (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \
- ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \
+#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \
+ (((version_num / 100) % 10) << 24) | \
+ (((version_num / 10) % 10) << 20) | \
+ ((version_num % 10) << 16) | \
+ (((version_num_patch / 10) % 10) << 12) | \
+ ((version_num_patch % 10) << 8) | \
0x01)
/**
diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c
index b179a65..8b5c83e 100644
--- a/test/dm/fwu_mdata.c
+++ b/test/dm/fwu_mdata.c
@@ -98,7 +98,7 @@
ut_assertok(populate_mmc_disk_image(uts));
ut_assertok(write_mmc_blk_device(uts));
- ut_assertok(fwu_get_mdata(dev, &mdata));
+ ut_assertok(fwu_get_mdata(&mdata));
ut_asserteq(mdata.version, 0x1);
@@ -118,30 +118,14 @@
ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
- ut_assertok(fwu_get_mdata(dev, &mdata));
+ ut_assertok(fwu_get_mdata(&mdata));
active_idx = (mdata.active_index + 1) % CONFIG_FWU_NUM_BANKS;
ut_assertok(fwu_set_active_index(active_idx));
- ut_assertok(fwu_get_mdata(dev, &mdata));
+ ut_assertok(fwu_get_mdata(&mdata));
ut_asserteq(mdata.active_index, active_idx);
return 0;
}
DM_TEST(dm_test_fwu_mdata_write, UT_TESTF_SCAN_FDT);
-
-static int dm_test_fwu_mdata_check(struct unit_test_state *uts)
-{
- struct udevice *dev;
-
- ut_assertok(setup_blk_device(uts));
- ut_assertok(populate_mmc_disk_image(uts));
- ut_assertok(write_mmc_blk_device(uts));
-
- ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
-
- ut_assertok(fwu_check_mdata_validity());
-
- return 0;
-}
-DM_TEST(dm_test_fwu_mdata_check, UT_TESTF_SCAN_FDT);
diff --git a/test/py/tests/test_efi_capsule/capsule_common.py b/test/py/tests/test_efi_capsule/capsule_common.py
new file mode 100644
index 0000000..9eef676
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/capsule_common.py
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023, Linaro Limited
+
+
+"""Common function for UEFI capsule test."""
+
+from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+
+def setup(u_boot_console, disk_img, osindications):
+ """setup the test
+
+ Args:
+ u_boot_console -- A console connection to U-Boot.
+ disk_img -- A path to disk image to be used for testing.
+ osindications -- String of osindications value.
+ """
+ u_boot_console.run_command_list([
+ f'host bind 0 {disk_img}',
+ 'printenv -e PlatformLangCodes', # workaround for terminal size determination
+ 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
+ 'efidebug boot order 1',
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+ 'u-boot-env raw 0x150000 0x200000"'])
+
+ if osindications is None:
+ u_boot_console.run_command('env set -e OsIndications')
+ else:
+ u_boot_console.run_command(f'env set -e -nv -bs -rt OsIndications ={osindications}')
+
+ u_boot_console.run_command('env save')
+
+def init_content(u_boot_console, target, filename, expected):
+ """initialize test content
+
+ Args:
+ u_boot_console -- A console connection to U-Boot.
+ target -- Target address to place the content.
+ filename -- File name of the content.
+ expected -- Expected string of the content.
+ """
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{filename}',
+ f'sf write 4000000 {target} 10',
+ 'sf read 5000000 100000 10',
+ 'md.b 5000000 10'])
+ assert expected in ''.join(output)
+
+def place_capsule_file(u_boot_console, filenames):
+ """place the capsule file
+
+ Args:
+ u_boot_console -- A console connection to U-Boot.
+ filenames -- File name array of the target capsule files.
+ """
+ for name in filenames:
+ u_boot_console.run_command_list([
+ f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{name}',
+ f'fatwrite host 0:1 4000000 {CAPSULE_INSTALL_DIR}/{name} $filesize'])
+
+ output = u_boot_console.run_command(f'fatls host 0:1 {CAPSULE_INSTALL_DIR}')
+ for name in filenames:
+ assert name in ''.join(output)
+
+def exec_manual_update(u_boot_console, disk_img, filenames, need_reboot = True):
+ """execute capsule update manually
+
+ Args:
+ u_boot_console -- A console connection to U-Boot.
+ disk_img -- A path to disk image to be used for testing.
+ filenames -- File name array of the target capsule files.
+ need_reboot -- Flag indicates whether system reboot is required.
+ """
+ # make sure that dfu_alt_info exists even persistent variables
+ # are not available.
+ output = u_boot_console.run_command_list([
+ 'env set dfu_alt_info '
+ '"sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+ 'u-boot-env raw 0x150000 0x200000"',
+ f'host bind 0 {disk_img}',
+ f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
+ for name in filenames:
+ assert name in ''.join(output)
+
+ # need to run uefi command to initiate capsule handling
+ u_boot_console.run_command(
+ 'env print -e Capsule0000', wait_for_reboot = need_reboot)
+
+def check_file_removed(u_boot_console, disk_img, filenames):
+ """check files are removed
+
+ Args:
+ u_boot_console -- A console connection to U-Boot.
+ disk_img -- A path to disk image to be used for testing.
+ filenames -- File name array of the target capsule files.
+ """
+ output = u_boot_console.run_command_list([
+ f'host bind 0 {disk_img}',
+ f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
+ for name in filenames:
+ assert name not in ''.join(output)
+
+def check_file_exist(u_boot_console, disk_img, filenames):
+ """check files exist
+
+ Args:
+ u_boot_console -- A console connection to U-Boot.
+ disk_img -- A path to disk image to be used for testing.
+ filenames -- File name array of the target capsule files.
+ """
+ output = u_boot_console.run_command_list([
+ f'host bind 0 {disk_img}',
+ f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
+ for name in filenames:
+ assert name in ''.join(output)
+
+def verify_content(u_boot_console, target, expected):
+ """verify the content
+
+ Args:
+ u_boot_console -- A console connection to U-Boot.
+ target -- Target address to verify.
+ expected -- Expected string of the content.
+ """
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ f'sf read 4000000 {target} 10',
+ 'md.b 4000000 10'])
+ assert expected in ''.join(output)
+
+def do_reboot_dtb_specified(u_boot_config, u_boot_console, dtb_filename):
+ """do reboot with specified DTB
+
+ Args:
+ u_boot_config -- U-boot configuration.
+ u_boot_console -- A console connection to U-Boot.
+ dtb_filename -- DTB file name.
+ """
+ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
+ u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+ + f'/{dtb_filename}'
+ u_boot_console.restart_uboot()
diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py
index 3e585b6..054be1e 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -62,6 +62,23 @@
'-out SIGNER2.crt -nodes -days 365'
% data_dir, shell=True)
+ # Update dtb to add the version information
+ check_call('cd %s; '
+ 'cp %s/test/py/tests/test_efi_capsule/version.dts .'
+ % (data_dir, u_boot_config.source_dir), shell=True)
+ if capsule_auth_enabled:
+ check_call('cd %s; '
+ 'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
+ 'fdtoverlay -i test_sig.dtb '
+ '-o test_ver.dtb version.dtbo'
+ % (data_dir), shell=True)
+ else:
+ check_call('cd %s; '
+ 'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
+ 'fdtoverlay -i %s/arch/sandbox/dts/test.dtb '
+ '-o test_ver.dtb version.dtbo'
+ % (data_dir, u_boot_config.build_dir), shell=True)
+
# Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir,
@@ -87,6 +104,26 @@
check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 uboot_bin_env.itb Test05' %
(data_dir, u_boot_config.build_dir),
shell=True)
+ check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
+ '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test101' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+ check_call('cd %s; %s/tools/mkeficapsule --index 2 --fw-version 10 '
+ '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test102' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+ check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
+ '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test103' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+ check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
+ '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test104' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+ check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
+ '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test105' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
if capsule_auth_enabled:
# raw firmware signed with proper key
@@ -123,6 +160,51 @@
'uboot_bin_env.itb Test14'
% (data_dir, u_boot_config.build_dir),
shell=True)
+ # raw firmware signed with proper key with version information
+ check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+ '--fw-version 5 '
+ '--private-key SIGNER.key --certificate SIGNER.crt '
+ '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
+ 'u-boot.bin.new Test111'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
+ # raw firmware signed with proper key with version information
+ check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 2 --monotonic-count 1 '
+ '--fw-version 10 '
+ '--private-key SIGNER.key --certificate SIGNER.crt '
+ '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 '
+ 'u-boot.env.new Test112'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
+ # raw firmware signed with proper key with lower version information
+ check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+ '--fw-version 2 '
+ '--private-key SIGNER.key --certificate SIGNER.crt '
+ '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
+ 'u-boot.bin.new Test113'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
+ # FIT firmware signed with proper key with version information
+ check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+ '--fw-version 5 '
+ '--private-key SIGNER.key --certificate SIGNER.crt '
+ '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
+ 'uboot_bin_env.itb Test114'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
+ # FIT firmware signed with proper key with lower version information
+ check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+ '--fw-version 2 '
+ '--private-key SIGNER.key --certificate SIGNER.crt '
+ '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
+ 'uboot_bin_env.itb Test115'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
# Create a disk image with EFI system partition
check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s' %
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
index 9ee1528..a3094c3 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
@@ -7,8 +7,15 @@
"""
import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
-
+from capsule_common import (
+ setup,
+ init_content,
+ place_capsule_file,
+ exec_manual_update,
+ check_file_removed,
+ verify_content,
+ do_reboot_dtb_specified
+)
@pytest.mark.boardspec('sandbox_flattree')
@pytest.mark.buildconfigspec('efi_capsule_firmware_fit')
@@ -40,37 +47,12 @@
u_boot_console.restart_uboot()
disk_img = efi_capsule_data
+ capsule_files = ['Test05']
with u_boot_console.log.section('Test Case 1-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
-
- # initialize contents
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 150000 10',
- 'sf read 5000000 150000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test05' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test05 $filesize' % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test05' in ''.join(output)
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
@@ -80,28 +62,13 @@
with u_boot_console.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test05' in ''.join(output)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ # deleted anyway
+ check_file_removed(u_boot_console, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:Old' in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'sf read 4000000 150000 10',
- 'md.b 4000000 10'])
- assert 'u-boot-env:Old' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(u_boot_console, '150000', 'u-boot-env:Old')
def test_efi_capsule_fw2(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -112,38 +79,12 @@
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test04']
with u_boot_console.log.section('Test Case 2-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
-
- # initialize contents
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 150000 10',
- 'sf read 5000000 150000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test04' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test04 $filesize' % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test04' in ''.join(output)
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
@@ -155,36 +96,88 @@
with u_boot_console.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test04' in ''.join(output)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+ expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
+ verify_content(u_boot_console, '100000', expected)
+
+ expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
+ verify_content(u_boot_console, '150000', expected)
+
+ def test_efi_capsule_fw3(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """ Test Case 3
+ Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+ 0x100000-0x150000: U-Boot binary (but dummy)
+ 0x150000-0x200000: U-Boot environment (but dummy)
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test104']
+ with u_boot_console.log.section('Test Case 3-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ # reboot
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ capsule_auth = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_authenticate')
+ with u_boot_console.log.section('Test Case 3-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ # deleted anyway
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
+ # make sure the dfu_alt_info exists because it is required for making ESRT.
output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test04' not in ''.join(output)
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+ 'u-boot-env raw 0x150000 0x200000"',
+ 'efidebug capsule esrt'])
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
if capsule_auth:
- assert 'u-boot:Old' in ''.join(output)
+ # capsule authentication failed
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(u_boot_console, '150000', 'u-boot-env:Old')
else:
- assert 'u-boot:New' in ''.join(output)
+ # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+ assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output)
+ assert 'ESRT: fw_version=5' in ''.join(output)
+ assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
- output = u_boot_console.run_command_list([
- 'sf read 4000000 150000 10',
- 'md.b 4000000 10'])
- if capsule_auth:
- assert 'u-boot-env:Old' in ''.join(output)
- else:
- assert 'u-boot-env:New' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:New')
+ verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+ def test_efi_capsule_fw4(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """ Test Case 4
+ Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+ but fw_version is lower than lowest_supported_version
+ No update should happen
+ 0x100000-0x150000: U-Boot binary (but dummy)
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test105']
+ with u_boot_console.log.section('Test Case 4-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ # reboot
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
index 92bfb14..80d791e 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
@@ -7,7 +7,16 @@
"""
import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+from capsule_common import (
+ setup,
+ init_content,
+ place_capsule_file,
+ exec_manual_update,
+ check_file_removed,
+ check_file_exist,
+ verify_content,
+ do_reboot_dtb_specified
+)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('efi_capsule_firmware_raw')
@@ -40,37 +49,12 @@
u_boot_console.restart_uboot()
disk_img = efi_capsule_data
+ capsule_files = ['Test03']
with u_boot_console.log.section('Test Case 1-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
-
- # initialize contents
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 150000 10',
- 'sf read 5000000 150000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test03' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test03 $filesize' % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test03' in ''.join(output)
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
# reboot
u_boot_console.restart_uboot()
@@ -80,28 +64,13 @@
with u_boot_console.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test03' in ''.join(output)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ # deleted anyway
+ check_file_removed(u_boot_console, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:Old' in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'sf read 4000000 150000 10',
- 'md.b 4000000 10'])
- assert 'u-boot-env:Old' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(u_boot_console, '150000', 'u-boot-env:Old')
def test_efi_capsule_fw2(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -112,44 +81,12 @@
0x150000-0x200000: U-Boot environment (but dummy)
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test01', 'Test02']
with u_boot_console.log.section('Test Case 2-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
- 'efidebug boot order 1',
- 'env set -e OsIndications',
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
-
- # initialize contents
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 150000 10',
- 'sf read 5000000 150000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place the capsule files
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test01' in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' in ''.join(output)
+ setup(u_boot_console, disk_img, None)
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
# reboot
u_boot_console.restart_uboot()
@@ -158,35 +95,12 @@
'config_efi_capsule_on_disk_early')
with u_boot_console.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test01' in ''.join(output)
- assert 'Test02' in ''.join(output)
+ exec_manual_update(u_boot_console, disk_img, capsule_files, False)
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000')
+ check_file_exist(u_boot_console, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test01' in ''.join(output)
- assert 'Test02' in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:Old' in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'sf read 4000000 150000 10',
- 'md.b 4000000 10'])
- assert 'u-boot-env:Old' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(u_boot_console, '150000', 'u-boot-env:Old')
def test_efi_capsule_fw3(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -195,45 +109,12 @@
0x100000-0x150000: U-Boot binary (but dummy)
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test01', 'Test02']
with u_boot_console.log.section('Test Case 3-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
-
- # initialize contents
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR,
- 'sf write 4000000 150000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place the capsule files
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test01' in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' in ''.join(output)
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
@@ -245,18 +126,7 @@
with u_boot_console.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test01' in ''.join(output)
- assert 'Test02' in ''.join(output)
-
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
# make sure the dfu_alt_info exists because it is required for making ESRT.
output = u_boot_console.run_command_list([
@@ -269,26 +139,91 @@
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test01' not in ''.join(output)
- assert 'Test02' not in ''.join(output)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- if capsule_auth:
- assert 'u-boot:Old' in ''.join(output)
- else:
- assert 'u-boot:New' in ''.join(output)
+ expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
+ verify_content(u_boot_console, '100000', expected)
+ expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
+ verify_content(u_boot_console, '150000', expected)
+
+ def test_efi_capsule_fw4(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """ Test Case 4
+ Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+ 0x100000-0x150000: U-Boot binary (but dummy)
+ 0x150000-0x200000: U-Boot environment (but dummy)
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test101', 'Test102']
+ with u_boot_console.log.section('Test Case 4-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ # reboot
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ capsule_auth = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_authenticate')
+ with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ # deleted anyway
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
+ # make sure the dfu_alt_info exists because it is required for making ESRT.
output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 150000 10',
- 'md.b 4000000 10'])
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000'
+ 'u-boot-env raw 0x150000 0x200000"',
+ 'efidebug capsule esrt'])
+
if capsule_auth:
- assert 'u-boot-env:Old' in ''.join(output)
+ # capsule authentication failed
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(u_boot_console, '150000', 'u-boot-env:Old')
else:
- assert 'u-boot-env:New' in ''.join(output)
+ # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+ assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
+ assert 'ESRT: fw_version=5' in ''.join(output)
+ assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
+
+ # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT.
+ assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output)
+ assert 'ESRT: fw_version=10' in ''.join(output)
+ assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
+
+ verify_content(u_boot_console, '100000', 'u-boot:New')
+ verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+ def test_efi_capsule_fw5(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """ Test Case 5
+ Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
+ but fw_version is lower than lowest_supported_version
+ No update should happen
+ 0x100000-0x150000: U-Boot binary (but dummy)
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test103']
+ with u_boot_console.log.section('Test Case 5-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ # reboot
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 5-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
index ba8429e..94d6c3e 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
@@ -10,7 +10,15 @@
"""
import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+from capsule_common import (
+ setup,
+ init_content,
+ place_capsule_file,
+ exec_manual_update,
+ check_file_removed,
+ verify_content,
+ do_reboot_dtb_specified
+)
@pytest.mark.boardspec('sandbox_flattree')
@pytest.mark.buildconfigspec('efi_capsule_firmware_fit')
@@ -37,70 +45,23 @@
should pass and the firmware be updated.
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test13']
with u_boot_console.log.section('Test Case 1-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
- # initialize content
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old'
- % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test13' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test13 $filesize'
- % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test13' in ''.join(output)
-
- # reboot
- mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
- u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
- + '/test_sig.dtb'
- u_boot_console.restart_uboot()
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
with u_boot_console.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test13' in ''.join(output)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test13' not in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:New' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:New')
def test_efi_capsule_auth2(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -113,73 +74,26 @@
not be updated.
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test14']
with u_boot_console.log.section('Test Case 2-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
- # initialize content
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old'
- % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test14' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test14 $filesize'
- % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test14' in ''.join(output)
-
- # reboot
- mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
- u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
- + '/test_sig.dtb'
- u_boot_console.restart_uboot()
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
with u_boot_console.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test14' in ''.join(output)
-
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
# deleted any way
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test14' not in ''.join(output)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:Old' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
def test_efi_capsule_auth3(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -191,70 +105,89 @@
should fail and the firmware not be updated.
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test02']
with u_boot_console.log.section('Test Case 3-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
- # initialize content
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old'
- % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test02 $filesize'
- % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' in ''.join(output)
-
- # reboot
- mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
- u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
- + '/test_sig.dtb'
- u_boot_console.restart_uboot()
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
with u_boot_console.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' in ''.join(output)
-
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
# deleted any way
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' not in ''.join(output)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
+
+ def test_efi_capsule_auth4(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
+ 0x100000-0x150000: U-Boot binary (but dummy)
+
+ If the capsule is properly signed, the authentication
+ should pass and the firmware be updated.
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test114']
+ with u_boot_console.log.section('Test Case 4-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:Old' in ''.join(output)
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+ 'u-boot-env raw 0x150000 0x200000"',
+ 'efidebug capsule esrt'])
+
+ # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+ assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output)
+ assert 'ESRT: fw_version=5' in ''.join(output)
+ assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
+
+ verify_content(u_boot_console, '100000', 'u-boot:New')
+ verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+ def test_efi_capsule_auth5(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
+ 0x100000-0x150000: U-Boot binary (but dummy)
+
+ If the capsule is signed but fw_version is lower than lowest
+ supported version, the authentication should fail and the firmware
+ not be updated.
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test115']
+ with u_boot_console.log.section('Test Case 5-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 5-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
index 710d992..ad2b1c6 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
@@ -8,7 +8,15 @@
"""
import pytest
-from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+from capsule_common import (
+ setup,
+ init_content,
+ place_capsule_file,
+ exec_manual_update,
+ check_file_removed,
+ verify_content,
+ do_reboot_dtb_specified
+)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('efi_capsule_firmware_raw')
@@ -34,69 +42,23 @@
should pass and the firmware be updated.
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test11']
with u_boot_console.log.section('Test Case 1-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
- # initialize content
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old'
- % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test11' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test11 $filesize'
- % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test11' in ''.join(output)
-
- # reboot
- mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
- u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
- + '/test_sig.dtb'
- u_boot_console.restart_uboot()
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
with u_boot_console.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test11' in ''.join(output)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test11' not in ''.join(output)
-
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:New' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:New')
def test_efi_capsule_auth2(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -108,73 +70,25 @@
not be updated.
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test12']
with u_boot_console.log.section('Test Case 2-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
- # initialize content
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old'
- % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test12' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test12 $filesize'
- % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test12' in ''.join(output)
-
- # reboot
- mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
- u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
- + '/test_sig.dtb'
- u_boot_console.restart_uboot()
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
with u_boot_console.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test12' in ''.join(output)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
-
- # deleted any way
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test12' not in ''.join(output)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:Old' in ''.join(output)
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
def test_efi_capsule_auth3(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -185,70 +99,94 @@
should fail and the firmware not be updated.
"""
disk_img = efi_capsule_data
+ capsule_files = ['Test02']
with u_boot_console.log.section('Test Case 3-a, before reboot'):
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'printenv -e PlatformLangCodes', # workaround for terminal size determination
- 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
- 'efidebug boot order 1',
- 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'env save'])
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
- # initialize content
- output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'fatload host 0:1 4000000 %s/u-boot.bin.old'
- % CAPSULE_DATA_DIR,
- 'sf write 4000000 100000 10',
- 'sf read 5000000 100000 10',
- 'md.b 5000000 10'])
- assert 'Old' in ''.join(output)
-
- # place a capsule file
- output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
- 'fatwrite host 0:1 4000000 %s/Test02 $filesize'
- % CAPSULE_INSTALL_DIR,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' in ''.join(output)
-
- # reboot
- mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
- u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
- + '/test_sig.dtb'
- u_boot_console.restart_uboot()
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
with u_boot_console.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
- # make sure that dfu_alt_info exists even persistent variables
- # are not available.
- output = u_boot_console.run_command_list([
- 'env set dfu_alt_info '
- '"sf 0:0=u-boot-bin raw 0x100000 '
- '0x50000;u-boot-env raw 0x150000 0x200000"',
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' in ''.join(output)
-
- # need to run uefi command to initiate capsule handling
- output = u_boot_console.run_command(
- 'env print -e Capsule0000', wait_for_reboot = True)
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
# deleted anyway
- output = u_boot_console.run_command_list([
- 'host bind 0 %s' % disk_img,
- 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
- assert 'Test02' not in ''.join(output)
+ check_file_removed(u_boot_console, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
+
+ def test_efi_capsule_auth4(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
+ 0x100000-0x150000: U-Boot binary (but dummy)
+
+ If the capsule is properly signed, the authentication
+ should pass and the firmware be updated.
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test111', 'Test112']
+ with u_boot_console.log.section('Test Case 4-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
output = u_boot_console.run_command_list([
- 'sf probe 0:0',
- 'sf read 4000000 100000 10',
- 'md.b 4000000 10'])
- assert 'u-boot:Old' in ''.join(output)
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
+ 'u-boot-env raw 0x150000 0x200000"',
+ 'efidebug capsule esrt'])
+
+ # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
+ assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
+ assert 'ESRT: fw_version=5' in ''.join(output)
+ assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
+
+ # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT.
+ assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output)
+ assert 'ESRT: fw_version=10' in ''.join(output)
+ assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
+
+ verify_content(u_boot_console, '100000', 'u-boot:New')
+ verify_content(u_boot_console, '150000', 'u-boot-env:New')
+
+ def test_efi_capsule_auth5(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
+ 0x100000-0x150000: U-Boot binary (but dummy)
+
+ If the capsule is signed but fw_version is lower than lowest
+ supported version, the authentication should fail and the firmware
+ not be updated.
+ """
+ disk_img = efi_capsule_data
+ capsule_files = ['Test113']
+ with u_boot_console.log.section('Test Case 5-a, before reboot'):
+ setup(u_boot_console, disk_img, '0x0000000000000004')
+ init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(u_boot_console, capsule_files)
+
+ do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 5-b, after reboot'):
+ if not capsule_early:
+ exec_manual_update(u_boot_console, disk_img, capsule_files)
+
+ check_file_removed(u_boot_console, disk_img, capsule_files)
+
+ verify_content(u_boot_console, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/version.dts b/test/py/tests/test_efi_capsule/version.dts
new file mode 100644
index 0000000..07850cc
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/version.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ firmware-version {
+ image1 {
+ lowest-supported-version = <3>;
+ image-index = <1>;
+ image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+ };
+ image2 {
+ lowest-supported-version = <7>;
+ image-index = <2>;
+ image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0";
+ };
+ image3 {
+ lowest-supported-version = <3>;
+ image-index = <1>;
+ image-type-id = "3673B45D-6A7C-46F3-9E60-ADABB03F7937";
+ };
+ };
+};
diff --git a/tools/Kconfig b/tools/Kconfig
index 539708f..6e23f44 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -157,4 +157,13 @@
help
Look Up Table Sequence
+config TOOLS_MKFWUMDATA
+ bool "Build mkfwumdata command"
+ default y if FWU_MULTI_BANK_UPDATE
+ help
+ This command allows users to create a raw image of the FWU
+ metadata for initial installation of the FWU multi bank
+ update on the board. The installation method depends on
+ the platform.
+
endmenu
diff --git a/tools/Makefile b/tools/Makefile
index d793cf3..a0cd87f 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -251,6 +251,10 @@
$(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid")
hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
+mkfwumdata-objs := mkfwumdata.o lib/crc32.o
+HOSTLDLIBS_mkfwumdata += -luuid
+hostprogs-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata
+
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
# exceptions for files that aren't complaint.
diff --git a/tools/eficapsule.h b/tools/eficapsule.h
index 072a4b5..753fb73 100644
--- a/tools/eficapsule.h
+++ b/tools/eficapsule.h
@@ -113,4 +113,34 @@
struct win_certificate_uefi_guid auth_info;
} __packed;
+/* fmp payload header */
+#define SIGNATURE_16(A, B) ((A) | ((B) << 8))
+#define SIGNATURE_32(A, B, C, D) \
+ (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
+
+#define FMP_PAYLOAD_HDR_SIGNATURE SIGNATURE_32('M', 'S', 'S', '1')
+
+/**
+ * struct fmp_payload_header - EDK2 header for the FMP payload
+ *
+ * This structure describes the header which is preprended to the
+ * FMP payload by the edk2 capsule generation scripts.
+ *
+ * @signature: Header signature used to identify the header
+ * @header_size: Size of the structure
+ * @fw_version: Firmware versions used
+ * @lowest_supported_version: Lowest supported version (not used)
+ */
+struct fmp_payload_header {
+ uint32_t signature;
+ uint32_t header_size;
+ uint32_t fw_version;
+ uint32_t lowest_supported_version;
+};
+
+struct fmp_payload_header_params {
+ bool have_header;
+ uint32_t fw_version;
+};
+
#endif /* _EFI_CAPSULE_H */
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index b71537b..52be1f1 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -41,6 +41,7 @@
{"guid", required_argument, NULL, 'g'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
+ {"fw-version", required_argument, NULL, 'v'},
{"private-key", required_argument, NULL, 'p'},
{"certificate", required_argument, NULL, 'c'},
{"monotonic-count", required_argument, NULL, 'm'},
@@ -60,6 +61,7 @@
"\t-g, --guid <guid string> guid for image blob type\n"
"\t-i, --index <index> update image index\n"
"\t-I, --instance <instance> update hardware instance\n"
+ "\t-v, --fw-version <version> firmware version\n"
"\t-p, --private-key <privkey file> private key file\n"
"\t-c, --certificate <cert file> signer's certificate file\n"
"\t-m, --monotonic-count <count> monotonic count\n"
@@ -402,6 +404,7 @@
*/
static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
unsigned long index, unsigned long instance,
+ struct fmp_payload_header_params *fmp_ph_params,
uint64_t mcount, char *privkey_file, char *cert_file,
uint16_t oemflags)
{
@@ -410,10 +413,11 @@
struct efi_firmware_management_capsule_image_header image;
struct auth_context auth_context;
FILE *f;
- uint8_t *data;
+ uint8_t *data, *new_data, *buf;
off_t bin_size;
uint64_t offset;
int ret;
+ struct fmp_payload_header payload_header;
#ifdef DEBUG
fprintf(stderr, "For output: %s\n", path);
@@ -423,6 +427,7 @@
auth_context.sig_size = 0;
f = NULL;
data = NULL;
+ new_data = NULL;
ret = -1;
/*
@@ -431,12 +436,30 @@
if (read_bin_file(bin, &data, &bin_size))
goto err;
+ buf = data;
+
+ /* insert fmp payload header right before the payload */
+ if (fmp_ph_params->have_header) {
+ new_data = malloc(bin_size + sizeof(payload_header));
+ if (!new_data)
+ goto err;
+
+ payload_header.signature = FMP_PAYLOAD_HDR_SIGNATURE;
+ payload_header.header_size = sizeof(payload_header);
+ payload_header.fw_version = fmp_ph_params->fw_version;
+ payload_header.lowest_supported_version = 0; /* not used */
+ memcpy(new_data, &payload_header, sizeof(payload_header));
+ memcpy(new_data + sizeof(payload_header), data, bin_size);
+ buf = new_data;
+ bin_size += sizeof(payload_header);
+ }
+
/* first, calculate signature to determine its size */
if (privkey_file && cert_file) {
auth_context.key_file = privkey_file;
auth_context.cert_file = cert_file;
auth_context.auth.monotonic_count = mcount;
- auth_context.image_data = data;
+ auth_context.image_data = buf;
auth_context.image_size = bin_size;
if (create_auth_data(&auth_context)) {
@@ -536,7 +559,7 @@
/*
* firmware binary
*/
- if (write_capsule_file(f, data, bin_size, "Firmware binary"))
+ if (write_capsule_file(f, buf, bin_size, "Firmware binary"))
goto err;
ret = 0;
@@ -545,6 +568,7 @@
fclose(f);
free_sig_data(&auth_context);
free(data);
+ free(new_data);
return ret;
}
@@ -644,6 +668,7 @@
unsigned long oemflags;
char *privkey_file, *cert_file;
int c, idx;
+ struct fmp_payload_header_params fmp_ph_params = { 0 };
guid = NULL;
index = 0;
@@ -679,6 +704,10 @@
case 'I':
instance = strtoul(optarg, NULL, 0);
break;
+ case 'v':
+ fmp_ph_params.fw_version = strtoul(optarg, NULL, 0);
+ fmp_ph_params.have_header = true;
+ break;
case 'p':
if (privkey_file) {
fprintf(stderr,
@@ -751,7 +780,7 @@
exit(EXIT_FAILURE);
}
} else if (create_fwbin(argv[argc - 1], argv[argc - 2], guid,
- index, instance, mcount, privkey_file,
+ index, instance, &fmp_ph_params, mcount, privkey_file,
cert_file, (uint16_t)oemflags) < 0) {
fprintf(stderr, "Creating firmware capsule failed\n");
exit(EXIT_FAILURE);
diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c
new file mode 100644
index 0000000..9732a8d
--- /dev/null
+++ b/tools/mkfwumdata.c
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <errno.h>
+#include <getopt.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <u-boot/crc.h>
+#include <unistd.h>
+#include <uuid/uuid.h>
+
+/* This will dynamically allocate the fwu_mdata */
+#define CONFIG_FWU_NUM_BANKS 0
+#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0
+
+/* Since we can not include fwu.h, redefine version here. */
+#define FWU_MDATA_VERSION 1
+
+typedef uint8_t u8;
+typedef int16_t s16;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+
+#include <fwu_mdata.h>
+
+/* TODO: Endianness conversion may be required for some arch. */
+
+static const char *opts_short = "b:i:a:p:gh";
+
+static struct option options[] = {
+ {"banks", required_argument, NULL, 'b'},
+ {"images", required_argument, NULL, 'i'},
+ {"guid", required_argument, NULL, 'g'},
+ {"active-bank", required_argument, NULL, 'a'},
+ {"previous-bank", required_argument, NULL, 'p'},
+ {"help", no_argument, NULL, 'h'},
+ {NULL, 0, NULL, 0},
+};
+
+static void print_usage(void)
+{
+ fprintf(stderr, "Usage: mkfwumdata [options] <UUIDs list> <output file>\n");
+ fprintf(stderr, "Options:\n"
+ "\t-i, --images <num> Number of images (mandatory)\n"
+ "\t-b, --banks <num> Number of banks (mandatory)\n"
+ "\t-a, --active-bank <num> Active bank (default=0)\n"
+ "\t-p, --previous-bank <num> Previous active bank (default=active_bank - 1)\n"
+ "\t-g, --guid Use GUID instead of UUID\n"
+ "\t-h, --help print a help message\n"
+ );
+ fprintf(stderr, " UUIDs list syntax:\n"
+ "\t <location uuid>,<image type uuid>,<images uuid list>\n"
+ "\t images uuid list syntax:\n"
+ "\t img_uuid_00,img_uuid_01...img_uuid_0b,\n"
+ "\t img_uuid_10,img_uuid_11...img_uuid_1b,\n"
+ "\t ...,\n"
+ "\t img_uuid_i0,img_uuid_i1...img_uuid_ib,\n"
+ "\t where 'b' and 'i' are number of banks and number\n"
+ "\t of images in a bank respectively.\n"
+ );
+}
+
+struct fwu_mdata_object {
+ size_t images;
+ size_t banks;
+ size_t size;
+ struct fwu_mdata *mdata;
+};
+
+static int previous_bank, active_bank;
+static bool __use_guid;
+
+static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks)
+{
+ struct fwu_mdata_object *mobj;
+
+ mobj = calloc(1, sizeof(*mobj));
+ if (!mobj)
+ return NULL;
+
+ mobj->size = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * banks) * images;
+ mobj->images = images;
+ mobj->banks = banks;
+
+ mobj->mdata = calloc(1, mobj->size);
+ if (!mobj->mdata) {
+ free(mobj);
+ return NULL;
+ }
+
+ return mobj;
+}
+
+static struct fwu_image_entry *
+fwu_get_image(struct fwu_mdata_object *mobj, size_t idx)
+{
+ size_t offset;
+
+ offset = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) * idx;
+
+ return (struct fwu_image_entry *)((char *)mobj->mdata + offset);
+}
+
+static struct fwu_image_bank_info *
+fwu_get_bank(struct fwu_mdata_object *mobj, size_t img_idx, size_t bnk_idx)
+{
+ size_t offset;
+
+ offset = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) * img_idx +
+ sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * bnk_idx;
+
+ return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset);
+}
+
+/**
+ * convert_uuid_to_guid() - convert UUID to GUID
+ * @buf: UUID binary
+ *
+ * UUID and GUID have the same data structure, but their binary
+ * formats are different due to the endianness. See lib/uuid.c.
+ * Since uuid_parse() can handle only UUID, this function must
+ * be called to get correct data for GUID when parsing a string.
+ *
+ * The correct data will be returned in @buf.
+ */
+static void convert_uuid_to_guid(unsigned char *buf)
+{
+ unsigned char c;
+
+ c = buf[0];
+ buf[0] = buf[3];
+ buf[3] = c;
+ c = buf[1];
+ buf[1] = buf[2];
+ buf[2] = c;
+
+ c = buf[4];
+ buf[4] = buf[5];
+ buf[5] = c;
+
+ c = buf[6];
+ buf[6] = buf[7];
+ buf[7] = c;
+}
+
+static int uuid_guid_parse(char *uuidstr, unsigned char *uuid)
+{
+ int ret;
+
+ ret = uuid_parse(uuidstr, uuid);
+ if (ret < 0)
+ return ret;
+
+ if (__use_guid)
+ convert_uuid_to_guid(uuid);
+
+ return ret;
+}
+
+static int
+fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj,
+ size_t idx, char *uuids)
+{
+ struct fwu_image_entry *image = fwu_get_image(mobj, idx);
+ struct fwu_image_bank_info *bank;
+ char *p = uuids, *uuid;
+ int i;
+
+ if (!image)
+ return -ENOENT;
+
+ /* Image location UUID */
+ uuid = strsep(&p, ",");
+ if (!uuid)
+ return -EINVAL;
+
+ if (strcmp(uuid, "0") &&
+ uuid_guid_parse(uuid, (unsigned char *)&image->location_uuid) < 0)
+ return -EINVAL;
+
+ /* Image type UUID */
+ uuid = strsep(&p, ",");
+ if (!uuid)
+ return -EINVAL;
+
+ if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_uuid) < 0)
+ return -EINVAL;
+
+ /* Fill bank image-UUID */
+ for (i = 0; i < mobj->banks; i++) {
+ bank = fwu_get_bank(mobj, idx, i);
+ if (!bank)
+ return -ENOENT;
+ bank->accepted = 1;
+ uuid = strsep(&p, ",");
+ if (!uuid)
+ return -EINVAL;
+
+ if (strcmp(uuid, "0") &&
+ uuid_guid_parse(uuid, (unsigned char *)&bank->image_uuid) < 0)
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/* Caller must ensure that @uuids[] has @mobj->images entries. */
+static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[])
+{
+ struct fwu_mdata *mdata = mobj->mdata;
+ int i, ret;
+
+ mdata->version = FWU_MDATA_VERSION;
+ mdata->active_index = active_bank;
+ mdata->previous_active_index = previous_bank;
+
+ for (i = 0; i < mobj->images; i++) {
+ ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version,
+ mobj->size - sizeof(uint32_t));
+
+ return 0;
+}
+
+static int
+fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output)
+{
+ struct fwu_mdata_object *mobj;
+ FILE *file;
+ int ret;
+
+ mobj = fwu_alloc_mdata(images, banks);
+ if (!mobj)
+ return -ENOMEM;
+
+ ret = fwu_parse_fill_uuids(mobj, uuids);
+ if (ret < 0)
+ goto done_make;
+
+ file = fopen(output, "w");
+ if (!file) {
+ ret = -errno;
+ goto done_make;
+ }
+
+ ret = fwrite(mobj->mdata, mobj->size, 1, file);
+ if (ret != mobj->size)
+ ret = -errno;
+ else
+ ret = 0;
+
+ fclose(file);
+
+done_make:
+ free(mobj->mdata);
+ free(mobj);
+
+ return ret;
+}
+
+int main(int argc, char *argv[])
+{
+ unsigned long banks = 0, images = 0;
+ int c, ret;
+
+ /* Explicitly initialize defaults */
+ active_bank = 0;
+ __use_guid = false;
+ previous_bank = INT_MAX;
+
+ do {
+ c = getopt_long(argc, argv, opts_short, options, NULL);
+ switch (c) {
+ case 'h':
+ print_usage();
+ return 0;
+ case 'b':
+ banks = strtoul(optarg, NULL, 0);
+ break;
+ case 'i':
+ images = strtoul(optarg, NULL, 0);
+ break;
+ case 'g':
+ __use_guid = true;
+ break;
+ case 'p':
+ previous_bank = strtoul(optarg, NULL, 0);
+ break;
+ case 'a':
+ active_bank = strtoul(optarg, NULL, 0);
+ break;
+ }
+ } while (c != -1);
+
+ if (!banks || !images) {
+ fprintf(stderr, "Error: The number of banks and images must not be 0.\n");
+ return -EINVAL;
+ }
+
+ /* This command takes UUIDs * images and output file. */
+ if (optind + images + 1 != argc) {
+ fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n");
+ print_usage();
+ return -ERANGE;
+ }
+
+ if (previous_bank == INT_MAX) {
+ /* set to the earlier bank in round-robin scheme */
+ previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1;
+ }
+
+ ret = fwu_make_mdata(images, banks, argv + optind, argv[argc - 1]);
+ if (ret < 0)
+ fprintf(stderr, "Error: Failed to parse and write image: %s\n",
+ strerror(-ret));
+
+ return ret;
+}