| commit | 7f1913938984ef6c6a46cb53e003719196d9c5de | [log] [tgz] |
|---|---|---|
| author | Grzegorz Bernacki <gjb@semihalf.com> | Fri Sep 07 18:20:23 2007 +0200 |
| committer | Rafal Jaworowski <raj@semihalf.com> | Fri Sep 07 18:20:23 2007 +0200 |
| tree | 127789e73caeb3464c9941c1f96440031b1e3f6c | |
| parent | 15ee4734e4e08003d73d9ead3ca80e2a0672e427 [diff] |
[PPC440SPe] Improve PCIe configuration space access - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>