| commit | 802bb57a584db2202a47d41ac730fe76ddeb4f33 | [log] [tgz] |
|---|---|---|
| author | Lokesh Vutla <lokeshvutla@ti.com> | Mon Feb 16 10:15:56 2015 +0530 |
| committer | Tom Rini <trini@ti.com> | Mon Feb 16 12:41:40 2015 -0500 |
| tree | 499ccc1cbbb52182227112a9fb7eb37fc7bfafe9 | |
| parent | aa8ac43645243b69faf0e81fab5f0d6fcf4285cf [diff] |
ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>