* Patch by Markus Pietrek, 24 Feb 2004:
NS9750 DevBoard added
* Patch by Pierre AUBERT, 24 Feb 2004
add USB support for MPC5200
* Patch by Steven Scholz, 24 Feb 2004:
- fix MII commands to use values from last command
* Patch by Torsten Demke, 24 Feb 2004:
Add support for the eXalion platform (SPSW-8240, F-30, F-300)
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 888b165..1dc9925 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2003
+ * (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -81,11 +81,22 @@
#endif
+/* USB */
+#if 1
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD 0
+#endif
+
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
- CFG_CMD_I2C | CFG_CMD_EEPROM)
+ CFG_CMD_I2C | CFG_CMD_EEPROM | \
+ ADD_USB_CMD)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
new file mode 100644
index 0000000..5ebc7a9
--- /dev/null
+++ b/include/configs/eXalion.h
@@ -0,0 +1,454 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X 1
+/* #define CONFIG_MPC8240 1 */
+#define CONFIG_MPC8245 1
+#define CONFIG_EXALION 1
+
+#if defined (CONFIG_MPC8240)
+ /* #warning ---------- eXalion with MPC8240 --------------- */
+#elif defined (CONFIG_MPC8245)
+ /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
+#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
+#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
+#else
+#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+/* older kernels need clock in MHz newer in Hz */
+ /* #define CONFIG_CLOCKS_IN_MHZ 1 *//* clocks passsed to Linux in MHz */
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_BOOTDELAY 10
+
+
+ /*#define CONFIG_DRAM_SPEED 66 *//* MHz */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_FAT | \
+ CFG_CMD_ENV | \
+ CFG_CMD_PCI )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP 1 /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 8 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_MISC_INIT_R 1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
+ /* return real value. */
+
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#undef CFG_RAMBOOT
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_DATA_SIZE 128
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+
+#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+
+#if defined (CONFIG_MPC8240)
+#define CFG_FLASH_BASE 0xFFE00000
+#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
+#elif defined (CONFIG_MPC8245)
+#define CFG_FLASH_BASE 0xFFC00000
+#define CFG_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */
+#define CFG_ENV_ADDR 0xFFFC0000
+#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
+
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+
+#define CFG_ALT_MEMTEST 1 /* use real memory test */
+#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
+#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
+
+#define CFG_EUMB_ADDR 0xFC000000
+
+/* #define CFG_ISA_MEM 0xFD000000 */
+#define CFG_ISA_IO 0xFE000000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
+#define FLASH_BASE1_PRELIM 0
+
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
+#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI 1 /* include pci support */
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI 1 /* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100 1
+
+#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
+#define PCI_ENET0_IOADDR 0x80000000
+#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
+#define PCI_ENET1_IOADDR 0x81000000
+#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
+#define PCI_ENET2_IOADDR 0x82000000
+#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
+#define PCI_ENET3_IOADDR 0x83000000
+
+/*-----------------------------------------------------------------------
+ * NS16550 Configuration
+ */
+#define CFG_NS16550 1
+#define CFG_NS16550_SERIAL 1
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 38400
+
+#define CFG_NS16550_REG_SIZE 1
+
+#if (CONFIG_CONS_INDEX == 1)
+#define CFG_NS16550_CLK 1843200 /* COM1 only ! */
+#else
+#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
+#endif
+
+#define CFG_NS16550_COM1 (CFG_ISA_IO + 0x3F8)
+#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C 1 /* To enable I2C support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CFG_HZ 1000
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
+
+ /*#define CONFIG_133MHZ_DRAM 1 *//* For 133 MHZ DRAM only !!!!!!!!!!! */
+
+#if defined (CONFIG_MPC8245)
+/* Bit-field values for PMCR2. */
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
+#define CFG_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
+#endif
+
+/* Bit-field values for MIOCR1. */
+#if !defined (CONFIG_133MHZ_DRAM)
+#define CFG_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
+#endif
+/* Bit-field values for MIOCR2. */
+#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
+ /* - note bottom 3 bits MUST be 0 */
+#endif
+
+/* Bit-field values for MCCR1. */
+#define CFG_ROMNAL 7 /*rom/flash next access time */
+#define CFG_ROMFAL 11 /*rom/flash access time */
+
+/* Bit-field values for MCCR2. */
+#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_REFINT 1300 /* no of clock cycles between CBR */
+#else /* refresh cycles */
+#define CFG_REFINT 750
+#endif
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_BSTOPRE 1023
+#else
+#define CFG_BSTOPRE 250
+#endif
+
+/* Bit-field values for MCCR3. */
+/* the following are for SDRAM only */
+
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_REFREC 9 /* Refresh to activate interval */
+#else
+#define CFG_REFREC 5 /* Refresh to activate interval */
+#endif
+#if defined (CONFIG_MPC8240)
+#define CFG_RDLAT 2 /* data latency from read command */
+#endif
+
+/* Bit-field values for MCCR4. */
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_PRETOACT 3 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 7 /* Activate to Precharge interval */
+#define CFG_ACTORW 5 /* Activate to R/W */
+#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
+#else
+#if 0
+#define CFG_PRETOACT 2 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */
+#define CFG_ACTORW 3 /* Activate to R/W */
+#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
+#endif
+#define CFG_PRETOACT 2 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
+#define CFG_ACTORW 3 /* Activate to R/W */
+#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
+#endif
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
+#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
+#define CFG_REGDIMM 0
+#if defined (CONFIG_MPC8240)
+#define CFG_REGISTERD_TYPE_BUFFER 0
+#elif defined (CONFIG_MPC8245)
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM 0
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ memory bank settings
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x3ff00000
+#define CFG_BANK1_END 0x3fffffff
+#define CFG_BANK1_ENABLE 0
+#define CFG_BANK2_START 0x3ff00000
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x00000000
+#define CFG_BANK4_END 0x00000000
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x00000000
+#define CFG_BANK5_END 0x00000000
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x00000000
+#define CFG_BANK6_END 0x00000000
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x00000000
+#define CFG_BANK7_END 0x00000000
+#define CFG_BANK7_ENABLE 0
+
+/*-----------------------------------------------------------------------
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE 0x01
+
+#if defined (CONFIG_MPC8240)
+#define CFG_ODCR 0xDF /* configures line driver impedances, */
+ /* see 8240 book for bit definitions */
+#elif defined (CONFIG_MPC8245)
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_ODCR 0xFE /* configures line driver impedances - 133MHz */
+#else
+#define CFG_ODCR 0xDE /* configures line driver impedances - 66MHz */
+#endif
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
+ /* currently accessed page in memory */
+ /* see 8240 book for details */
+
+/*-----------------------------------------------------------------------
+ * Block Address Translation (BAT) register settings.
+ */
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI memory */
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+/* values according to the manual */
+#define CONFIG_DRAM_50MHZ 1
+#define CONFIG_SDRAM_50MHZ
+
+#undef NR_8259_INTS
+#define NR_8259_INTS 1
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ */
+#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR CFG_ISA_IO /* base address */
+#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
+#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
+#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
+
+#define CONFIG_ATAPI
+
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#undef CONFIG_IDE_RESET /* reset for ide supported... */
+#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
+
+/*-----------------------------------------------------------------------
+ * DISK Partition support
+ */
+#define CONFIG_DOS_PARTITION
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
new file mode 100644
index 0000000..11d21b2
--- /dev/null
+++ b/include/configs/ns9750dev.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ *
+ * Configuation settings for the NetSilicon NS9750 DevBoard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */
+#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */
+
+#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2)
+#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4)
+#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8)
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+/*@TODO #define CONFIG_STATUS_LED*/
+#define CONFIG_USE_IRQ
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial
+ * data */
+
+/*
+ * Hardware drivers
+ */
+#define CFG_NS9750_UART 1 /* use on-chip UART */
+#define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1 /* Port B */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#if 0 /* @TODO */
+#define CONFIG_COMMANDS \
+ (CONFIG_CMD_DFL | \
+ CFG_CMD_CACHE | \
+ /*CFG_CMD_NAND |*/ \
+ /*CFG_CMD_EEPROM |*/ \
+ /*CFG_CMD_I2C |*/ \
+ /*CFG_CMD_USB |*/ \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_DATE | \
+ CFG_CMD_ELF)
+#else
+#define CONFIG_COMMANDS \
+ (CONFIG_CMD_BDI | \
+ CFG_CMD_NET | \
+ CFG_CMD_PING | \
+ CFG_CMD_CONSOLE | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_LOADS | \
+ CFG_CMD_MEMORY)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
+
+#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.42.30
+#define CONFIG_SERVERIP 192.168.42.1
+
+/*#define CONFIG_BOOTFILE "elinos-lart" */
+/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "NS9750DEV # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */
+
+#define CFG_HZ (CPU_CLK_FREQ/64)
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define NS9750_ETH_PHY_ADDRESS (0x0000)
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+/* TODO */
+#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
+#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
+
+#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* @TODO*/
+#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
+#if 0
+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
+#endif
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
+
+/* @TODO */
+/*#define CFG_ENV_IS_IN_FLASH 1*/
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+#ifdef CONFIG_STATUS_LED
+
+extern void __led_init(led_id_t mask, int state);
+extern void __led_toggle(led_id_t mask);
+extern void __led_set(led_id_t mask, int state);
+
+#endif /* CONFIG_STATUS_LED */
+
+#endif /* __CONFIG_H */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 49951f5..8d4013a 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -90,6 +90,7 @@
#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
+#define MPC5XXX_USB (CFG_MBAR + 0x1000)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
@@ -132,6 +133,7 @@
#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
+#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
/* Local Plus Bus interface */
diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h
new file mode 100644
index 0000000..0918931
--- /dev/null
+++ b/include/ns9750_bbus.h
@@ -0,0 +1,125 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Definitions for BBus usage
+ * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_BBUS_H
+#define FS_NS9750_BBUS_H
+
+#define NS9750_BBUS_MODULE_BASE (0x90600000)
+
+#define get_bbus_reg_addr(c) \
+ ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
+
+/* We have support for 50 GPIO pins */
+
+#define get_gpio_cfg_reg_addr(pin) \
+ get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
+
+/* To Read/Modify/Write a pin configuration register, use it like
+ set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
+ They should be wrapped by cli()/sti() */
+#define set_gpio_cfg_reg_val(pin,cfg) \
+ *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
+ ~NS9750_GPIO_CFG_MASK((pin))) |\
+ NS9750_GPIO_CFG_VAL((pin),(cfg));
+
+#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \
+ NS9750_GPIO_CFG_MA))
+#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4))
+
+#define NS9750_GPIO_CFG_MA (0x0F)
+#define NS9750_GPIO_CFG_INPUT (0x00)
+#define NS9750_GPIO_CFG_OUTPUT (0x08)
+#define NS9750_GPIO_CFG_FUNC_GPIO (0x03)
+#define NS9750_GPIO_CFG_FUNC_2 (0x02)
+#define NS9750_GPIO_CFG_FUNC_1 (0x01)
+#define NS9750_GPIO_CFG_FUNC_0 (0x00)
+
+/* the register addresses */
+
+#define NS9750_BBUS_MASTER_RESET (0x00)
+#define NS9750_BBUS_GPIO_CFG_BASE (0x10)
+#define NS9750_BBUS_GPIO_CTRL_BASE (0x30)
+#define NS9750_BBUS_GPIO_STAT_BASE (0x40)
+#define NS9750_BBUS_MONITOR (0x50)
+#define NS9750_BBUS_DMA_INT_STAT (0x60)
+#define NS9750_BBUS_DMA_INT_ENABLE (0x64)
+#define NS9750_BBUS_USB_CFG (0x70)
+#define NS9750_BBUS_ENDIAN_CFG (0x80)
+#define NS9750_BBUS_ARM_WAKE_UP (0x90)
+
+/* register bit fields */
+
+#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100)
+#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080)
+#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040)
+#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020)
+#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010)
+#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008)
+#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004)
+#define NS9750_BBUS_MASTER_RESET_USB (0x00000002)
+#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001)
+
+/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
+
+#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000)
+#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000)
+#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000)
+#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000)
+#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000)
+#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800)
+#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400)
+#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200)
+#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100)
+#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080)
+#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040)
+#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020)
+#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010)
+#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008)
+#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004)
+#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002)
+#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001)
+
+#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008)
+#define NS9750_BBUS_USB_CFG_SPEED (0x00000004)
+#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003)
+#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
+#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002)
+#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001)
+#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000)
+
+#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000)
+#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080)
+#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040)
+#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020)
+#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010)
+#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008)
+#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004)
+#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002)
+#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001)
+
+#endif /* FS_NS9750_BBUS_H */
diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h
new file mode 100644
index 0000000..ce0c841
--- /dev/null
+++ b/include/ns9750_eth.h
@@ -0,0 +1,526 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @References: [1] NS9750 Hardware Reference, December 2003
+ * [2] Intel LXT971 Datasheet #249414 Rev. 02
+ * [3] NS7520 Linux Ethernet Driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_ETH_H
+#define FS_NS9750_ETH_H
+
+#ifdef CONFIG_DRIVER_NS9750_ETHERNET
+
+#define NS9750_ETH_MODULE_BASE (0xA0600000)
+
+#define get_eth_reg_addr(c) \
+ ((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))
+
+#define NS9750_ETH_EGCR1 (0x0000)
+#define NS9750_ETH_EGCR2 (0x0004)
+#define NS9750_ETH_EGSR (0x0008)
+#define NS9750_ETH_FIFORX (0x000C)
+#define NS9750_ETH_FIFOTX (0x0010)
+#define NS9750_ETH_FIFOTXS (0x0014)
+#define NS9750_ETH_ETSR (0x0018)
+#define NS9750_ETH_ERSR (0x001C)
+#define NS9750_ETH_MAC1 (0x0400)
+#define NS9750_ETH_MAC2 (0x0404)
+#define NS9750_ETH_IPGT (0x0408)
+#define NS9750_ETH_IPGR (0x040C)
+#define NS9750_ETH_CLRT (0x0410)
+#define NS9750_ETH_MAXF (0x0414)
+#define NS9750_ETH_SUPP (0x0418)
+#define NS9750_ETH_TEST (0x041C)
+#define NS9750_ETH_MCFG (0x0420)
+#define NS9750_ETH_MCMD (0x0424)
+#define NS9750_ETH_MADR (0x0428)
+#define NS9750_ETH_MWTD (0x042C)
+#define NS9750_ETH_MRDD (0x0430)
+#define NS9750_ETH_MIND (0x0434)
+#define NS9750_ETH_SA1 (0x0440)
+#define NS9750_ETH_SA2 (0x0444)
+#define NS9750_ETH_SA3 (0x0448)
+#define NS9750_ETH_SAFR (0x0500)
+#define NS9750_ETH_HT1 (0x0504)
+#define NS9750_ETH_HT2 (0x0508)
+#define NS9750_ETH_STAT_BASE (0x0680)
+#define NS9750_ETH_RXAPTR (0x0A00)
+#define NS9750_ETH_RXBPTR (0x0A04)
+#define NS9750_ETH_RXCPTR (0x0A08)
+#define NS9750_ETH_RXDPTR (0x0A0C)
+#define NS9750_ETH_EINTR (0x0A10)
+#define NS9750_ETH_EINTREN (0x0A14)
+#define NS9750_ETH_TXPTR (0x0A18)
+#define NS9750_ETH_TXRPTR (0x0A1C)
+#define NS9750_ETH_TXERBD (0x0A20)
+#define NS9750_ETH_TXSPTR (0x0A24)
+#define NS9750_ETH_RXAOFF (0x0A28)
+#define NS9750_ETH_RXBOFF (0x0A2C)
+#define NS9750_ETH_RXCOFF (0x0A30)
+#define NS9750_ETH_RXDOFF (0x0A34)
+#define NS9750_ETH_TXOFF (0x0A38)
+#define NS9750_ETH_RXFREE (0x0A3C)
+#define NS9750_ETH_TXBD (0x1000)
+
+/* register bit fields */
+
+#define NS9750_ETH_EGCR1_ERX (0x80000000)
+#define NS9750_ETH_EGCR1_ERXDMA (0x40000000)
+#define NS9750_ETH_EGCR1_ERXSHT (0x10000000)
+#define NS9750_ETH_EGCR1_ERXSIZ (0x08000000)
+#define NS9750_ETH_EGCR1_ETXSIZ (0x04000000)
+#define NS9750_ETH_EGCR1_ETXDIAG (0x02000000)
+#define NS9750_ETH_EGCR1_ERXBAD (0x01000000)
+#define NS9750_ETH_EGCR1_ETX (0x00800000)
+#define NS9750_ETH_EGCR1_ETXDMA (0x00400000)
+#define NS9750_ETH_EGCR1_ETXWM (0x00200000)
+#define NS9750_ETH_EGCR1_ERXADV (0x00100000)
+#define NS9750_ETH_EGCR1_ERXINIT (0x00080000)
+#define NS9750_ETH_EGCR1_PHY_MODE_MA (0x0000C000)
+#define NS9750_ETH_EGCR1_PHY_MODE_MII (0x00008000)
+#define NS9750_ETH_EGCR1_PHY_MODE_RMII (0x00004000)
+#define NS9750_ETH_EGCR1_RXCINV (0x00001000)
+#define NS9750_ETH_EGCR1_TXCINV (0x00000800)
+#define NS9750_ETH_EGCR1_RXALIGN (0x00000400)
+#define NS9750_ETH_EGCR1_MAC_HRST (0x00000200)
+#define NS9750_ETH_EGCR1_ITXA (0x00000100)
+
+#define NS9750_ETH_EGCR2_TPTV_MA (0xFFFF0000)
+#define NS9750_ETH_EGCR2_TPCF (0x00000040)
+#define NS9750_ETH_EGCR2_THPDF (0x00000020)
+#define NS9750_ETH_EGCR2_TCLER (0x00000008)
+#define NS9750_ETH_EGCR2_AUTOZ (0x00000004)
+#define NS9750_ETH_EGCR2_CLRCNT (0x00000002)
+#define NS9750_ETH_EGCR2_STEN (0x00000001)
+
+#define NS9750_ETH_EGSR_RXINIT (0x00100000)
+#define NS9750_ETH_EGSR_TXFIFONF (0x00080000)
+#define NS9750_ETH_EGSR_TXFIFOH (0x00040000)
+#define NS9750_ETH_EGSR_TXFIFOE (0x00010000)
+
+#define NS9750_ETH_FIFOTXS_ALL (0x00000055)
+#define NS9750_ETH_FIFOTXS_3 (0x000000d5)
+#define NS9750_ETH_FIFOTXS_2 (0x00000035)
+#define NS9750_ETH_FIFOTXS_1 (0x0000000D)
+#define NS9750_ETH_FIFOTXS_0 (0x00000003)
+
+#define NS9750_ETH_ETSR_TXOK (0x00008000)
+#define NS9750_ETH_ETSR_TXBR (0x00004000)
+#define NS9750_ETH_ETSR_TXMC (0x00002000)
+#define NS9750_ETH_ETSR_TXAL (0x00001000)
+#define NS9750_ETH_ETSR_TXAED (0x00000800)
+#define NS9750_ETH_ETSR_TXAEC (0x00000400)
+#define NS9750_ETH_ETSR_TXAUR (0x00000200)
+#define NS9750_ETH_ETSR_TXAJ (0x00000100)
+#define NS9750_ETH_ETSR_TXDEF (0x00000040)
+#define NS9750_ETH_ETSR_TXCRC (0x00000020)
+#define NS9750_ETH_ETSR_TXCOLC (0x0000000F)
+
+#define NS9750_ETH_ERSR_RXSIZE_MA (0x0FFF0000)
+#define NS9750_ETH_ERSR_RXCE (0x00008000)
+#define NS9750_ETH_ERSR_RXDV (0x00004000)
+#define NS9750_ETH_ERSR_RXOK (0x00002000)
+#define NS9750_ETH_ERSR_RXBR (0x00001000)
+#define NS9750_ETH_ERSR_RXMC (0x00000800)
+#define NS9750_ETH_ERSR_RXCRC (0x00000400)
+#define NS9750_ETH_ERSR_RXDR (0x00000200)
+#define NS9750_ETH_ERSR_RXCV (0x00000100)
+#define NS9750_ETH_ERSR_RXSHT (0x00000040)
+
+#define NS9750_ETH_MAC1_SRST (0x00008000)
+#define NS9750_ETH_MAC1_SIMMRST (0x00004000)
+#define NS9750_ETH_MAC1_RPEMCSR (0x00000800)
+#define NS9750_ETH_MAC1_RPERFUN (0x00000400)
+#define NS9750_ETH_MAC1_RPEMCST (0x00000200)
+#define NS9750_ETH_MAC1_RPETFUN (0x00000100)
+#define NS9750_ETH_MAC1_LOOPBK (0x00000010)
+#define NS9750_ETH_MAC1_TXFLOW (0x00000008)
+#define NS9750_ETH_MAC1_RXFLOW (0x00000004)
+#define NS9750_ETH_MAC1_PALLRX (0x00000002)
+#define NS9750_ETH_MAC1_RXEN (0x00000001)
+
+#define NS9750_ETH_MAC2_EDEFER (0x00004000)
+#define NS9750_ETH_MAC2_BACKP (0x00002000)
+#define NS9750_ETH_MAC2_NOBO (0x00001000)
+#define NS9750_ETH_MAC2_LONGP (0x00000200)
+#define NS9750_ETH_MAC2_PUREP (0x00000100)
+#define NS9750_ETH_MAC2_AUTOP (0x00000080)
+#define NS9750_ETH_MAC2_VLANP (0x00000040)
+#define NS9750_ETH_MAC2_PADEN (0x00000020)
+#define NS9750_ETH_MAC2_CRCEN (0x00000010)
+#define NS9750_ETH_MAC2_DELCRC (0x00000008)
+#define NS9750_ETH_MAC2_HUGE (0x00000004)
+#define NS9750_ETH_MAC2_FLENC (0x00000002)
+#define NS9750_ETH_MAC2_FULLD (0x00000001)
+
+#define NS9750_ETH_IPGT_MA (0x0000007F)
+
+#define NS9750_ETH_IPGR_IPGR1 (0x00007F00)
+#define NS9750_ETH_IPGR_IPGR2 (0x0000007F)
+
+#define NS9750_ETH_CLRT_CWIN (0x00003F00)
+#define NS9750_ETH_CLRT_RETX (0x0000000F)
+
+#define NS9750_ETH_MAXF_MAXF (0x0000FFFF)
+
+#define NS9750_ETH_SUPP_RPERMII (0x00008000)
+#define NS9750_ETH_SUPP_SPEED (0x00000080)
+
+#define NS9750_ETH_TEST_TBACK (0x00000004)
+#define NS9750_ETH_TEST_TPAUSE (0x00000002)
+#define NS9750_ETH_TEST_SPQ (0x00000001)
+
+#define NS9750_ETH_MCFG_RMIIM (0x00008000)
+#define NS9750_ETH_MCFG_CLKS_MA (0x0000001C)
+#define NS9750_ETH_MCFG_CLKS_4 (0x00000004)
+#define NS9750_ETH_MCFG_CLKS_6 (0x00000008)
+#define NS9750_ETH_MCFG_CLKS_8 (0x0000000C)
+#define NS9750_ETH_MCFG_CLKS_10 (0x00000010)
+#define NS9750_ETH_MCFG_CLKS_20 (0x00000014)
+#define NS9750_ETH_MCFG_CLKS_30 (0x00000018)
+#define NS9750_ETH_MCFG_CLKS_40 (0x0000001C)
+#define NS9750_ETH_MCFG_SPRE (0x00000002)
+#define NS9750_ETH_MCFG_SCANI (0x00000001)
+
+#define NS9750_ETH_MCMD_SCAN (0x00000002)
+#define NS9750_ETH_MCMD_READ (0x00000001)
+
+#define NS9750_ETH_MADR_DADR_MA (0x00001F00)
+#define NS9750_ETH_MADR_RADR_MA (0x0000001F)
+
+#define NS9750_ETH_MWTD_MA (0x0000FFFF)
+
+#define NS9750_ETH_MRRD_MA (0x0000FFFF)
+
+#define NS9750_ETH_MIND_MIILF (0x00000008)
+#define NS9750_ETH_MIND_NVALID (0x00000004)
+#define NS9750_ETH_MIND_SCAN (0x00000002)
+#define NS9750_ETH_MIND_BUSY (0x00000001)
+
+#define NS9750_ETH_SA1_OCTET1_MA (0x0000FF00)
+#define NS9750_ETH_SA1_OCTET2_MA (0x000000FF)
+
+#define NS9750_ETH_SA2_OCTET3_MA (0x0000FF00)
+#define NS9750_ETH_SA2_OCTET4_MA (0x000000FF)
+
+#define NS9750_ETH_SA3_OCTET5_MA (0x0000FF00)
+#define NS9750_ETH_SA3_OCTET6_MA (0x000000FF)
+
+#define NS9750_ETH_SAFR_PRO (0x00000008)
+#define NS9750_ETH_SAFR_PRM (0x00000004)
+#define NS9750_ETH_SAFR_PRA (0x00000002)
+#define NS9750_ETH_SAFR_BROAD (0x00000001)
+
+#define NS9750_ETH_HT1_MA (0x0000FFFF)
+
+#define NS9750_ETH_HT2_MA (0x0000FFFF)
+
+/* also valid for EINTREN */
+#define NS9750_ETH_EINTR_RXOVL_DATA (0x02000000)
+#define NS9750_ETH_EINTR_RXOVL_STAT (0x01000000)
+#define NS9750_ETH_EINTR_RXBUFC (0x00800000)
+#define NS9750_ETH_EINTR_RXDONEA (0x00400000)
+#define NS9750_ETH_EINTR_RXDONEB (0x00200000)
+#define NS9750_ETH_EINTR_RXDONEC (0x00100000)
+#define NS9750_ETH_EINTR_RXDONED (0x00080000)
+#define NS9750_ETH_EINTR_RXNOBUF (0x00040000)
+#define NS9750_ETH_EINTR_RXBUFFUL (0x00020000)
+#define NS9750_ETH_EINTR_RXBR (0x00010000)
+#define NS9750_ETH_EINTR_STOVFL (0x00000040)
+#define NS9750_ETH_EINTR_TXPAUSE (0x00000020)
+#define NS9750_ETH_EINTR_TXBUFC (0x00000010)
+#define NS9750_ETH_EINTR_TXBUFNR (0x00000008)
+#define NS9750_ETH_EINTR_TXDONE (0x00000004)
+#define NS9750_ETH_EINTR_TXERR (0x00000002)
+#define NS9750_ETH_EINTR_TXIDLE (0x00000001)
+#define NS9750_ETH_EINTR_RX_MA \
+ (NS9750_ETH_EINTR_RXOVL_DATA | \
+ NS9750_ETH_EINTR_RXOVL_STAT | \
+ NS9750_ETH_EINTR_RXBUFC | \
+ NS9750_ETH_EINTR_RXDONEA | \
+ NS9750_ETH_EINTR_RXDONEB | \
+ NS9750_ETH_EINTR_RXDONEC | \
+ NS9750_ETH_EINTR_RXDONED | \
+ NS9750_ETH_EINTR_RXNOBUF | \
+ NS9750_ETH_EINTR_RXBUFFUL | \
+ NS9750_ETH_EINTR_RXBR )
+#define NS9750_ETH_EINTR_TX_MA \
+ (NS9750_ETH_EINTR_TXPAUSE | \
+ NS9750_ETH_EINTR_TXBUFC | \
+ NS9750_ETH_EINTR_TXBUFNR | \
+ NS9750_ETH_EINTR_TXDONE | \
+ NS9750_ETH_EINTR_TXERR | \
+ NS9750_ETH_EINTR_TXIDLE)
+
+/* for TXPTR, TXRPTR, TXERBD and TXSPTR */
+#define NS9750_ETH_TXPTR_MA (0x000000FF)
+
+/* for RXAOFF, RXBOFF, RXCOFF and RXDOFF */
+#define NS9750_ETH_RXOFF_MA (0x000007FF)
+
+#define NS9750_ETH_TXOFF_MA (0x000003FF)
+
+#define NS9750_ETH_RXFREE_D (0x00000008)
+#define NS9750_ETH_RXFREE_C (0x00000004)
+#define NS9750_ETH_RXFREE_B (0x00000002)
+#define NS9750_ETH_RXFREE_A (0x00000001)
+
+/* PHY definitions (LXT971A) [2] */
+
+#define PHY_COMMON_CTRL (0x00)
+#define PHY_COMMON_STAT (0x01)
+#define PHY_COMMON_ID1 (0x02)
+#define PHY_COMMON_ID2 (0x03)
+#define PHY_COMMON_AUTO_ADV (0x04)
+#define PHY_COMMON_AUTO_LNKB (0x05)
+#define PHY_COMMON_AUTO_EXP (0x06)
+#define PHY_COMMON_AUTO_NEXT (0x07)
+#define PHY_COMMON_AUTO_LNKN (0x08)
+#define PHY_LXT971_PORT_CFG (0x10)
+#define PHY_LXT971_STAT2 (0x11)
+#define PHY_LXT971_INT_ENABLE (0x12)
+#define PHY_LXT971_INT_STATUS (0x13)
+#define PHY_LXT971_LED_CFG (0x14)
+#define PHY_LXT971_DIG_CFG (0x1A)
+#define PHY_LXT971_TX_CTRL (0x1E)
+
+/* CTRL PHY Control Register Bit Fields */
+
+#define PHY_COMMON_CTRL_RESET (0x8000)
+#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
+#define PHY_COMMON_CTRL_SPD_MA (0x2040)
+#define PHY_COMMON_CTRL_SPD_10 (0x0000)
+#define PHY_COMMON_CTRL_SPD_100 (0x2000)
+#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
+#define PHY_COMMON_CTRL_SPD_RES (0x2040)
+#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
+#define PHY_COMMON_CTRL_POWER_DN (0x0800)
+#define PHY_COMMON_CTRL_ISOLATE (0x0400)
+#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
+#define PHY_COMMON_CTRL_DUPLEX (0x0100)
+#define PHY_COMMON_CTRL_COL_TEST (0x0080)
+#define PHY_COMMON_CTRL_RES1 (0x003F)
+
+/* STAT Status Register Bit Fields */
+
+#define PHY_COMMON_STAT_100BT4 (0x8000)
+#define PHY_COMMON_STAT_100BXFD (0x4000)
+#define PHY_COMMON_STAT_100BXHD (0x2000)
+#define PHY_COMMON_STAT_10BTFD (0x1000)
+#define PHY_COMMON_STAT_10BTHD (0x0800)
+#define PHY_COMMON_STAT_100BT2FD (0x0400)
+#define PHY_COMMON_STAT_100BT2HD (0x0200)
+#define PHY_COMMON_STAT_EXT_STAT (0x0100)
+#define PHY_COMMON_STAT_RES1 (0x0080)
+#define PHY_COMMON_STAT_MF_PSUP (0x0040)
+#define PHY_COMMON_STAT_AN_COMP (0x0020)
+#define PHY_COMMON_STAT_RMT_FLT (0x0010)
+#define PHY_COMMON_STAT_AN_CAP (0x0008)
+#define PHY_COMMON_STAT_LNK_STAT (0x0004)
+#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
+#define PHY_COMMON_STAT_EXT_CAP (0x0001)
+
+
+/* AUTO_ADV Auto-neg Advert Register Bit Fields */
+
+#define PHY_COMMON_AUTO_ADV_NP (0x8000)
+#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
+#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
+#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
+#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
+#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
+#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
+#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
+#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
+#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
+#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
+#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
+#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
+#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
+
+/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
+
+#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
+#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
+#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
+#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
+#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
+#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
+#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
+#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
+#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
+#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
+#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
+#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
+#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
+#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
+
+/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
+
+#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
+#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
+#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
+#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
+#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
+#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
+#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
+
+/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
+
+#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
+#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
+#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
+#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
+#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
+#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
+
+/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
+
+#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
+#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
+#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
+#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
+#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
+#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
+
+/* PORT_CFG Port Configuration Register Bit Fields */
+
+#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
+#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
+#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
+#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
+#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
+#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
+#define PHY_LXT971_PORT_CFG_SQE (0x0200)
+#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
+#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
+#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
+#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
+#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
+#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
+#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
+
+/* STAT2 Status Register #2 Bit Fields */
+
+#define PHY_LXT971_STAT2_RES1 (0x8000)
+#define PHY_LXT971_STAT2_100BTX (0x4000)
+#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
+#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
+#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
+#define PHY_LXT971_STAT2_LINK (0x0400)
+#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
+#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
+#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
+#define PHY_LXT971_STAT2_RES2 (0x0040)
+#define PHY_LXT971_STAT2_POLARITY (0x0020)
+#define PHY_LXT971_STAT2_PAUSE (0x0010)
+#define PHY_LXT971_STAT2_ERROR (0x0008)
+#define PHY_LXT971_STAT2_RES3 (0x0007)
+
+/* INT_ENABLE Interrupt Enable Register Bit Fields */
+
+#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
+#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
+#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
+#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
+#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
+#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
+#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
+#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
+
+/* INT_STATUS Interrupt Status Register Bit Fields */
+
+#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
+#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
+#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
+#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
+#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
+#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
+#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
+#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
+
+/* LED_CFG Interrupt LED Configuration Register Bit Fields */
+
+#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
+#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
+#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
+#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
+#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
+#define PHY_LXT971_LED_CFG_RES1 (0x0001)
+
+/* only one of these values must be shifted for each SHIFT_LED? */
+
+#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
+#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
+#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
+#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
+#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
+#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
+#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
+#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
+#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
+#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
+#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
+#define PHY_LXT971_LED_CFG_LINK (0x0004)
+#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
+#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
+#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
+#define PHY_LXT971_LED_CFG_SPEED (0x0000)
+
+/* DIG_CFG Digitial Configuration Register Bit Fields */
+
+#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
+#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
+#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
+#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
+#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
+
+#define PHY_LXT971_MDIO_MAX_CLK (8000000)
+
+/* TX_CTRL Transmit Control Register Bit Fields
+ documentation is buggy for this register, therefore setting not included */
+
+typedef enum
+{
+ PHY_NONE = 0x0000, /* no PHY detected yet */
+ PHY_LXT971A = 0x0013
+} PhyType;
+
+#define PHY_MDIO_MAX_CLK (2500000)
+
+#ifndef NS9750_ETH_PHY_ADDRESS
+# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */
+#endif /* NETARM_ETH_PHY_ADDRESS */
+
+#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
+
+#endif /* FS_NS9750_ETH_H */
diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h
new file mode 100644
index 0000000..44c8ddc
--- /dev/null
+++ b/include/ns9750_mem.h
@@ -0,0 +1,172 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Definitions for Memory Control Module
+ * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_MEM_H
+#define FS_NS9750_SYS_H
+
+#define NS9750_MEM_MODULE_BASE (0xA0700000)
+
+#define get_mem_reg_addr(c) \
+ ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
+
+/* the register addresses */
+
+#define NS9750_MEM_CTRL (0x0000)
+#define NS9750_MEM_STATUS (0x0004)
+#define NS9750_MEM_CFG (0x0008)
+#define NS9750_MEM_DYN_CTRL (0x0020)
+#define NS9750_MEM_DYN_REFRESH (0x0024)
+#define NS9750_MEM_DYN_READ_CFG (0x0028)
+#define NS9750_MEM_DYN_TRP (0x0030)
+#define NS9750_MEM_DYN_TRAS (0x0034)
+#define NS9750_MEM_DYN_TSREX (0x0038)
+#define NS9750_MEM_DYN_TAPR (0x003C)
+#define NS9750_MEM_DYN_TDAL (0x0040)
+#define NS9750_MEM_DYN_TWR (0x0044)
+#define NS9750_MEM_DYN_TRC (0x0048)
+#define NS9750_MEM_DYN_TRFC (0x004C)
+#define NS9750_MEM_DYN_TXSR (0x0050)
+#define NS9750_MEM_DYN_TRRD (0x0054)
+#define NS9750_MEM_DYN_TMRD (0x0058)
+#define NS9750_MEM_STAT_EXT_WAIT (0x0080)
+#define NS9750_MEM_DYN_CFG_BASE (0x0100)
+#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104)
+#define NS9750_MEM_STAT_CFG_BASE (0x0200)
+#define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204)
+#define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208)
+#define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C)
+#define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210)
+#define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214)
+#define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218)
+
+/* the vectored register addresses */
+
+#define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
+#define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
+#define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
+#define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
+
+/* register bit fields */
+
+#define NS9750_MEM_CTRL_L (0x00000004)
+#define NS9750_MEM_CTRL_M (0x00000002)
+#define NS9750_MEM_CTRL_E (0x00000001)
+
+#define NS9750_MEM_STAT_SA (0x00000004)
+#define NS9750_MEM_STAT_S (0x00000002)
+#define NS9750_MEM_STAT_B (0x00000001)
+
+#define NS9750_MEM_CFG_CLK (0x00000010)
+#define NS9750_MEM_CFG_N (0x00000001)
+
+#define NS9750_MEM_DYN_CTRL_NRP (0x00004000)
+#define NS9750_MEM_DYN_CTRL_DP (0x00002000)
+#define NS9750_MEM_DYN_CTRL_I_MA (0x00000180)
+#define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000)
+#define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080)
+#define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100)
+#define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180)
+#define NS9750_MEM_DYN_CTRL_SR (0x00000002)
+#define NS9750_MEM_DYN_CTRL_CE (0x00000001)
+
+
+#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF)
+
+#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003)
+#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001)
+#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002)
+#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003)
+
+#define NS9750_MEM_DYN_TRP_MA (0x0000000F)
+
+#define NS9750_MEM_DYN_TRAS_MA (0x0000000F)
+
+#define NS9750_MEM_DYN_TSREX_MA (0x0000000F)
+
+#define NS9750_MEM_DYN_TAPR_MA (0x0000000F)
+
+#define NS9750_MEM_DYN_TDAL_MA (0x0000000F)
+
+#define NS9750_MEM_DYN_TWR_MA (0x0000000F)
+
+#define NS9750_MEM_DYN_TRC_MA (0x0000001F)
+
+#define NS9750_MEM_DYN_TRFC_MA (0x0000001F)
+
+#define NS9750_MEM_DYN_TXSR_MA (0x0000001F)
+
+#define NS9750_MEM_DYN_TRRD_MA (0x0000000F)
+
+#define NS9750_MEM_DYN_TMRD_MA (0x0000000F)
+
+#define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F)
+
+#define NS9750_MEM_DYN_CFG_P (0x00100000)
+#define NS9750_MEM_DYN_CFG_BDMC (0x00080000)
+#define NS9750_MEM_DYN_CFG_AM (0x00004000)
+#define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80)
+#define NS9750_MEM_DYN_CFG_MD (0x00000018)
+
+#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003)
+
+#define NS9750_MEM_STAT_CFG_PSMC (0x00100000)
+#define NS9750_MEM_STAT_CFG_BSMC (0x00080000)
+#define NS9750_MEM_STAT_CFG_EW (0x00000100)
+#define NS9750_MEM_STAT_CFG_PB (0x00000080)
+#define NS9750_MEM_STAT_CFG_PC (0x00000040)
+#define NS9750_MEM_STAT_CFG_PM (0x00000008)
+#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003)
+#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000)
+#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001)
+#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002)
+
+#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F)
+
+#define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F)
+
+#define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F)
+
+#define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F)
+
+#define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F)
+
+#define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F)
+
+
+#endif /* FS_NS9750_MEM_H */
diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h
new file mode 100644
index 0000000..e6ff3e1
--- /dev/null
+++ b/include/ns9750_ser.h
@@ -0,0 +1,202 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @References: [1] NS9750 Hardware Reference, December 2003
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_SER_H
+#define FS_NS9750_SER_H
+
+#define NS9750_SER_MODULE_BASE (0x90200000)
+
+#define get_ser_reg_addr(c) \
+ ((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
+
+#define get_ser_reg_addr_channel(reg,chan) \
+ get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
+
+/* the register addresses */
+
+#define NS9750_SER_CTRL_A (0x00)
+#define NS9750_SER_CTRL_B (0x04)
+#define NS9750_SER_STAT_A (0x08)
+#define NS9750_SER_BITRATE (0x0C)
+#define NS9750_SER_FIFO (0x10)
+#define NS9750_SER_RX_BUF_TIMER (0x14)
+#define NS9750_SER_RX_CHAR_TIMER (0x18)
+#define NS9750_SER_RX_MATCH (0x1C)
+#define NS9750_SER_RX_MATCH_MASK (0x20)
+#define NS9750_SER_FLOW_CTRL (0x34)
+#define NS9750_SER_FLOW_CTRL_FORCE (0x38)
+
+/* register bit fields */
+
+/* control A register */
+
+#define NS9750_SER_CTRL_A_CE (0x80000000)
+#define NS9750_SER_CTRL_A_BRK (0x40000000)
+#define NS9750_SER_CTRL_A_STICKP (0x20000000)
+#define NS9750_SER_CTRL_A_EPS (0x10000000)
+#define NS9750_SER_CTRL_A_PE (0x08000000)
+#define NS9750_SER_CTRL_A_STOP (0x04000000)
+#define NS9750_SER_CTRL_A_WLS_MA (0x03000000)
+#define NS9750_SER_CTRL_A_WLS_5 (0x00000000)
+#define NS9750_SER_CTRL_A_WLS_6 (0x01000000)
+#define NS9750_SER_CTRL_A_WLS_7 (0x02000000)
+#define NS9750_SER_CTRL_A_WLS_8 (0x03000000)
+#define NS9750_SER_CTRL_A_CTSTX (0x00800000)
+#define NS9750_SER_CTRL_A_RTSRX (0x00400000)
+#define NS9750_SER_CTRL_A_RL (0x00200000)
+#define NS9750_SER_CTRL_A_LL (0x00100000)
+#define NS9750_SER_CTRL_A_RES (0x000CF000)
+#define NS9750_SER_CTRL_A_DTR (0x00020000)
+#define NS9750_SER_CTRL_A_RTS (0x00010000)
+#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00)
+#define NS9750_SER_CTRL_A_ERXDMA (0x00000100)
+#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0)
+#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E)
+#define NS9750_SER_CTRL_A_ETXDMA (0x00000001)
+
+/* control B register */
+
+#define NS9750_SER_CTRL_B_RDM1 (0x80000000)
+#define NS9750_SER_CTRL_B_RDM2 (0x40000000)
+#define NS9750_SER_CTRL_B_RDM3 (0x20000000)
+#define NS9750_SER_CTRL_B_RDM4 (0x10000000)
+#define NS9750_SER_CTRL_B_RBGT (0x08000000)
+#define NS9750_SER_CTRL_B_RCGT (0x04000000)
+#define NS9750_SER_CTRL_B_MODE_MA (0x00300000)
+#define NS9750_SER_CTRL_B_MODE_UART (0x00000000)
+#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000)
+#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000)
+#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000)
+#define NS9750_SER_CTRL_B_BITORDR (0x00080000)
+#define NS9750_SER_CTRL_B_RES (0x0007703F)
+#define NS9750_SER_CTRL_B_RTSTX (0x00008000)
+#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0)
+
+/* status A register */
+
+#define NS9750_SER_STAT_A_MATCH1 (0x80000000)
+#define NS9750_SER_STAT_A_MATCH2 (0x40000000)
+#define NS9750_SER_STAT_A_MATCH3 (0x20000000)
+#define NS9750_SER_STAT_A_MATCH4 (0x10000000)
+#define NS9750_SER_STAT_A_BGAP (0x08000000)
+#define NS9750_SER_STAT_A_CGAP (0x04000000)
+#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000)
+#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000)
+#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000)
+#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000)
+#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000)
+#define NS9750_SER_STAT_A_DCD (0x00080000)
+#define NS9750_SER_STAT_A_RI (0x00040000)
+#define NS9750_SER_STAT_A_DSR (0x00020000)
+#define NS9750_SER_STAT_A_CTS (0x00010000)
+#define NS9750_SER_STAT_A_RBRK (0x00008000)
+#define NS9750_SER_STAT_A_RFE (0x00004000)
+#define NS9750_SER_STAT_A_RPE (0x00002000)
+#define NS9750_SER_STAT_A_ROVER (0x00001000)
+#define NS9750_SER_STAT_A_RRDY (0x00000800)
+#define NS9750_SER_STAT_A_RHALF (0x00000400)
+#define NS9750_SER_STAT_A_RBC (0x00000200)
+#define NS9750_SER_STAT_A_RFULL (0x00000100)
+#define NS9750_SER_STAT_A_DCDI (0x00000080)
+#define NS9750_SER_STAT_A_RII (0x00000040)
+#define NS9750_SER_STAT_A_DSRI (0x00000020)
+#define NS9750_SER_STAT_A_CTSI (0x00000010)
+#define NS9750_SER_STAT_A_TRDY (0x00000008)
+#define NS9750_SER_STAT_A_THALF (0x00000004)
+#define NS9750_SER_STAT_A_TBC (0x00000002)
+#define NS9750_SER_STAT_A_TEMPTY (0x00000001)
+
+#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
+ NS9750_SER_STAT_A_ROVER | \
+ NS9750_SER_STAT_A_RPE )
+#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
+ NS9750_SER_STAT_A_RBRK | \
+ NS9750_SER_STAT_A_RRDY | \
+ NS9750_SER_STAT_A_RHALF | \
+ NS9750_SER_STAT_A_RBC | \
+ NS9750_SER_STAT_A_DCDI | \
+ NS9750_SER_STAT_A_RII | \
+ NS9750_SER_STAT_A_DSRI | \
+ NS9750_SER_STAT_A_CTSI )
+#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
+ NS9750_SER_STAT_A_THALF | \
+ NS9750_SER_STAT_A_TBC | \
+ NS9750_SER_STAT_A_TEMPTY )
+/* bit rate register */
+
+#define NS9750_SER_BITRATE_EBIT (0x80000000)
+#define NS9750_SER_BITRATE_TMODE (0x40000000)
+#define NS9750_SER_BITRATE_RXSRC (0x20000000)
+#define NS9750_SER_BITRATE_TXSRC (0x10000000)
+#define NS9750_SER_BITRATE_RXEXT (0x08000000)
+#define NS9750_SER_BITRATE_TXEXT (0x04000000)
+#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000)
+#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000)
+#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000)
+#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000)
+#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000)
+#define NS9750_SER_BITRATE_TXCINV (0x00800000)
+#define NS9750_SER_BITRATE_RXCINV (0x00400000)
+#define NS9750_SER_BITRATE_TCDR_MA (0x00180000)
+#define NS9750_SER_BITRATE_TCDR_1 (0x00000000)
+#define NS9750_SER_BITRATE_TCDR_8 (0x00080000)
+#define NS9750_SER_BITRATE_TCDR_16 (0x00100000)
+#define NS9750_SER_BITRATE_TCDR_32 (0x00180000)
+#define NS9750_SER_BITRATE_RCDR_MA (0x00070000)
+#define NS9750_SER_BITRATE_RCDR_1 (0x00000000)
+#define NS9750_SER_BITRATE_RCDR_8 (0x00020000)
+#define NS9750_SER_BITRATE_RCDR_16 (0x00040000)
+#define NS9750_SER_BITRATE_RCDR_32 (0x00060000)
+#define NS9750_SER_BITRATE_TICS (0x00010000)
+#define NS9750_SER_BITRATE_RICS (0x00008000)
+#define NS9750_SER_BITRATE_N_MA (0x00007FFF)
+
+/* receive buffer gap timer */
+
+#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */
+#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */
+#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
+
+/* receive character gap timer */
+
+#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000)
+#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF)
+
+/* receive match */
+
+#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000)
+#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000)
+#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00)
+#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF)
+
+/* receive match mask */
+
+#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
+#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
+#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
+#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
+
+#endif /* FS_NS9750_SER_H */
diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h
new file mode 100644
index 0000000..c563cad
--- /dev/null
+++ b/include/ns9750_sys.h
@@ -0,0 +1,215 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Definitions for SYS Control Module
+ * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_SYS_H
+#define FS_NS9750_SYS_H
+
+#define NS9750_SYS_MODULE_BASE (0xA0900000)
+
+#define get_sys_reg_addr(c) \
+ ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
+
+/* the register addresses */
+
+#define NS9750_SYS_AHB_GEN (0x0000)
+#define NS9750_SYS_BRC_BASE (0x0004)
+#define NS9750_SYS_AHB_TIMEOUT (0x0014)
+#define NS9750_SYS_AHB_ERROR1 (0x0018)
+#define NS9750_SYS_AHB_ERROR2 (0x001C)
+#define NS9750_SYS_AHB_MON (0x0020)
+#define NS9750_SYS_TIMER_COUNT_BASE (0x0044)
+#define NS9750_SYS_TIMER_READ_BASE (0x0084)
+#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4)
+#define NS9750_SYS_INT_CFG_BASE (0x0144)
+#define NS9750_SYS_ISRADDR (0x0164)
+#define NS9750_SYS_INT_STAT_ACTIVE (0x0168)
+#define NS9750_SYS_INT_STAT_RAW (0x016C)
+#define NS9750_SYS_TIMER_INT_STAT (0x0170)
+#define NS9750_SYS_SW_WDOG_CFG (0x0174)
+#define NS9750_SYS_SW_WDOG_TIMER (0x0178)
+#define NS9750_SYS_CLOCK (0x017C)
+#define NS9750_SYS_RESET (0x0180)
+#define NS9750_SYS_MISC (0x0184)
+#define NS9750_SYS_PLL (0x0188)
+#define NS9750_SYS_ACT_INT_STAT (0x018C)
+#define NS9750_SYS_TIMER_CTRL_BASE (0x0190)
+#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0)
+#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4)
+#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0)
+#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4)
+#define NS9750_SYS_GEN_ID (0x0210)
+#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214)
+
+/* the vectored register addresses */
+
+#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c))
+#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c))
+#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c))
+#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c))
+/* CS_DYN start with 4 */
+#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2)
+#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2)
+/* CS_STATIC start with 0 */
+#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2)
+#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2)
+#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c))
+
+/* register bit fields */
+
+#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001)
+
+/* need to be n*8bit to BRC channel */
+#define NS9750_SYS_BRC_CEB (0x00000080)
+#define NS9750_SYS_BRC_BRF_MA (0x00000030)
+#define NS9750_SYS_BRC_BRF_100 (0x00000000)
+#define NS9750_SYS_BRC_BRF_75 (0x00000010)
+#define NS9750_SYS_BRC_BRF_50 (0x00000020)
+#define NS9750_SYS_BRC_BRF_25 (0x00000030)
+
+#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000)
+#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF)
+
+#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000)
+#define NS9750_SYS_AHB_ERROR2_AER (0x00020000)
+#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000)
+#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000)
+#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000)
+#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00)
+#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0)
+#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038)
+#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007)
+
+#define NS9750_SYS_AHB_MON_EIC (0x00800000)
+#define NS9750_SYS_AHB_MON_MBII (0x00400000)
+#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0)
+#define NS9750_SYS_AHB_MON_MBLDC (0x00000020)
+#define NS9750_SYS_AHB_MON_SERDC (0x00000010)
+#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C)
+#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000)
+#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004)
+#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008)
+#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003)
+#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000)
+#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001)
+#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002)
+
+/* need to be n*8bit to Int Level */
+
+#define NS9750_SYS_INT_CFG_IE (0x00000080)
+#define NS9750_SYS_INT_CFG_IT (0x00000020)
+#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F)
+
+#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF)
+
+#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080)
+#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020)
+#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005)
+
+#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380)
+#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000)
+#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080)
+#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100)
+#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180)
+#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200)
+#define NS9750_SYS_CLOCK_BBC (0x00000040)
+#define NS9750_SYS_CLOCK_LCC (0x00000020)
+#define NS9750_SYS_CLOCK_MCC (0x00000010)
+#define NS9750_SYS_CLOCK_PARBC (0x00000008)
+#define NS9750_SYS_CLOCK_PC (0x00000004)
+#define NS9750_SYS_CLOCK_MACC (0x00000001)
+
+#define NS9750_SYS_RESET_SR (0x80000000)
+#define NS9750_SYS_RESET_I2CW (0x00100000)
+#define NS9750_SYS_RESET_CSE (0x00080000)
+#define NS9750_SYS_RESET_SMWE (0x00040000)
+#define NS9750_SYS_RESET_EWE (0x00020000)
+#define NS9750_SYS_RESET_PI3WE (0x00010000)
+#define NS9750_SYS_RESET_BBT (0x00000040)
+#define NS9750_SYS_RESET_LCDC (0x00000020)
+#define NS9750_SYS_RESET_MEMC (0x00000010)
+#define NS9750_SYS_RESET_PCIAR (0x00000008)
+#define NS9750_SYS_RESET_PCIM (0x00000004)
+#define NS9750_SYS_RESET_MACM (0x00000001)
+
+#define NS9750_SYS_MISC_REV_MA (0xFF000000)
+#define NS9750_SYS_MISC_PCIA (0x00002000)
+#define NS9750_SYS_MISC_VDIS (0x00001000)
+#define NS9750_SYS_MISC_BMM (0x00000800)
+#define NS9750_SYS_MISC_CS1DB (0x00000400)
+#define NS9750_SYS_MISC_CS1DW_MA (0x00000300)
+#define NS9750_SYS_MISC_MCCM (0x00000080)
+#define NS9750_SYS_MISC_PMSS (0x00000040)
+#define NS9750_SYS_MISC_CS1P (0x00000020)
+#define NS9750_SYS_MISC_ENDM (0x00000008)
+#define NS9750_SYS_MISC_MBAR (0x00000004)
+#define NS9750_SYS_MISC_IRAM0 (0x00000001)
+
+#define NS9750_SYS_PLL_PLLBS (0x02000000)
+#define NS9750_SYS_PLL_PLLFS_MA (0x01800000)
+#define NS9750_SYS_PLL_PLLIS_MA (0x00600000)
+#define NS9750_SYS_PLL_PLLND_MA (0x001F0000)
+#define NS9750_SYS_PLL_PLLSW (0x00008000)
+#define NS9750_SYS_PLL_PLLBSSW (0x00000200)
+#define NS9750_SYS_PLL_FSEL_MA (0x00000180)
+#define NS9750_SYS_PLL_CPCC_MA (0x00000060)
+#define NS9750_SYS_PLL_NDSW_MA (0x0000001F)
+
+#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF)
+
+#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000)
+#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200)
+#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0)
+#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040)
+#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080)
+#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0)
+#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100)
+#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140)
+#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180)
+#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0)
+#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030)
+#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010)
+#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020)
+#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008)
+#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004)
+#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002)
+#define NS9750_SYS_TIMER_CTRL_REN (0x00000001)
+
+#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008)
+#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004)
+#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002)
+#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001)
+
+#endif /* FS_NS9750_SYS_H */